Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (1t) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer.

Abstract: An inorganic nanocomposite is prepared by obtaining a solution of a soluble hydrazine-based metal chalcogenide precursor; dispersing a nanoentity in the precursor solution; applying a solution of the precursor containing the nanoentity onto a substrate to produce a film of the precursor containing the nanoentity; and annealing the film of the precursor containing the nanoentity to produce the metal chalcogenide nanocomposite film comprising at least one metal chalcogenide and at least one molecularly-intermixed nanoentity on the substrate. The process can be used to prepare field-effect transistors and photovoltaic devices.

Abstract: Solar cells, methods for manufacturing a quantum dot layer for a solar cell, and methods for manufacturing solar cells are disclosed. An example method for manufacturing a quantum dot layer for a solar cell includes providing an electron conductor layer, providing a quantum dot chemical bath deposition solution, controlling the temperature of the quantum dot chemical bath deposition solution to a temperature of about 30° C. or greater, and immersing the electron conductor layer in the quantum dot chemical bath deposition solution for about 1-10 hours. The quantum dot chemical bath deposition solution may include CdSe.

Abstract: Affords AlxGa(1-x)As (0?x?1) substrates epitaxial wafers for infrared LEDs, infrared LEDs, methods of manufacturing AlxGa(1-x)As substrates, methods of manufacturing epitaxial wafers for infrared LEDs, and methods of manufacturing infrared LEDs, whereby a high level of transmissivity is maintained, and through which, in the fabrication of semiconductor devices, the devices prove to have superior light output characteristics. An AlxGa(1-x)As substrate (10a) as disclosed is an AlxGa(1-x)As substrate (10a) furnished with an AlxGa(1-x)As layer (11) having a major surface (11a) and, on the reverse side from the major surface (11a), a rear face (11b), and is characterized in that in the AlxGa(1-x)As layer (11), the amount fraction x of Al in the rear face (11b) is greater the amount fraction x of Al in the major surface (11a). The AlxGa(1-x)As substrate (10a) may additionally be provided with a GaAs substrate (13), contacting the rear face (11b) of the AlxGa(1-x)As layer (11).

Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.

Abstract: A solution of a hydrazine-based precursor of a metal chalcogenide is prepared by adding an elemental metal and an elemental chalcogen to a hydrazine compound. The precursor solution can be used to form a film. The precursor solutions can be used in preparing field-effect transistors, photovoltaic devices and phase-change memory devices.

Abstract: The invention has for its object to provide a process of synthesizing high-purity hBN crystal bodies on a robust substrate even under normal pressure. The inventive process of producing hexagonal boron nitride crystal bodies is characterized by comprising a preparation step of preparing a mixture of a boron nitride raw material and a metal solvent comprising a transition metal, a contact step of bringing a sapphire substrate in contact with the mixture, a heating step of heating the mixture, and a recrystallization step of recrystallizing at normal pressure a melt obtained in the heating step. It is also characterized by using as the metal solvent a transition metal selected from the group consisting of Fe, Ni, Co, and a combination thereof, and at least one substance selected from the group consisting of Cr, TiN and V without recourse to any sapphire substrate.

Abstract: Embodiments of the invention are provided for a thin film stack containing a plurality of epitaxial stacks disposed on a substrate and a method for forming such a thin film stack. In one embodiment, the epitaxial stack contains a first sacrificial layer disposed over the substrate, a first epitaxial film disposed over the first sacrificial layer, a second sacrificial layer disposed over the first epitaxial film, and a second epitaxial film disposed over the second sacrificial layer. The thin film stack may further contain additional epitaxial films disposed over sacrificial layers. Generally, the epitaxial films contain gallium arsenide alloys and the sacrificial layers contain aluminum arsenide alloys. Methods provide the removal of the epitaxial films from the substrate by etching away the sacrificial layers during an epitaxial lift off (ELO) process. The epitaxial films are useful as photovoltaic cells, laser diodes, or other devices or materials.

Abstract: The invention relates to a method for depositing at least one semiconductor layer on at least one substrate in a processing chamber (2). Said semiconductor layer is composed of several components which are evaporated by non-continuously injecting a liquid starting material (3) or a starting material (3) dissolved in a liquid into a tempered evaporation chamber (4) with the aid of one respective injector unit (5) while said vapor is fed to the processing chamber by means of a carrier gas (7). The inventive method is characterized in that the mass flow rate parameters, such as the preliminary injection pressure, the injection frequency, the pulse/pause ratio, and the phase relation between the pulses/pauses and the pulses/pauses of the other injector unit(s), which determine the progress of the mass flow rate of a first silicon-containing starting material and a germanium-containing second starting material (3) through the associated injector unit (5), are individually adjusted or varied.

Abstract: The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. A variety of combinations of nanoparticles, such as Au and CdS nanoparticles, may be used to form a necklace. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V. The present invention also provides methods for constructing such a device.

Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1.

Abstract: A structure and method of forming same, comprising a low threading density alloy graded layer, deposited according to a deposition temperature profile in correspondence with increasing alloy composition. In one embodiment, a first substantially relaxed alloy graded layer is deposited while varying a deposition temperature according to a first temperature profile. A second substantially relaxed alloy graded layer is deposited over the first graded layer while varying a deposition temperature according to a second temperature profile. Preferably, the minimum signed rate of change of the second temperature profile is less than the maximum signed rate of change of the first temperature profile.

Abstract: A thin film semiconductor and a method of its fabrication use induced crystallization and aggregation of a nanocrystal seed layer to form a merged-domain layer. The nanocrystal seed layer is deposited onto a substrate surface within a defined boundary. A reaction temperature below a boiling point of a reaction solution is employed. A thin film metal-oxide transistor and a method of its production employ the thin film semiconductor as a channel of the transistor. The merged-domain layer exhibits high carrier mobility.

Abstract: A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing a solar grade wafer mold defining an interior for receiving the slurry; introducing the slurry into the solar grade wafer mold; precipitating the silicon powder from the slurry to form a preform of the solar grade silicon wafer; and crystallizing the preform to make the solar grade silicon wafer.

Abstract: A forming method for a film pattern, includes: forming a first bank layer on a substrate; forming a second bank layer on the first bank layer; patterning the first bank layer and the second bank layer thereby forming a bank having a pattern formation region including a first pattern formation region and a second pattern formation region which is connected to the first pattern formation region and has a width which is wider than that of the first pattern formation region; and forming the film pattern by depositing a functional liquid onto the pattern formation region which has been demarcated by the bank, wherein a first bank formation material and a second bank formation material are both materials including a siloxane bonds as a main chain, and the second bank formation material is a material including a fluorine bonds as a side chain.

Abstract: The object of the present invention is to provide a semiconductor layer formation material from which a semiconductor layer having a high carrier transport ability can be made, a method of forming a semiconductor element having a semiconductor layer having a high carrier transport ability, a semiconductor element formed by the semiconductor element manufacturing method, an electronic device provided with the semiconductor element, and electronic equipment having a high reliability. The semiconductor layer formation material includes a semiconductor material, porous particles each having a number of pores, and a dispersion medium, wherein the semiconductor material is existed in the semiconductor layer formation material in such a state that at least a part of the semiconductor material is filled in the pores of the porous particles. According to the semiconductor layer formation material it is possible to form a semiconductor layer having a high carrier transport ability can be made.

Abstract: A deposition method which deposits a CdS buffer layer on a surface of a solar cell from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited in a deposition chamber by heating the surface of the solar cell absorber to cause the transfer of heat from the solar cell absorber layer to at least a portion of the process solution that is in contact with the surface. Used solution is cooled, and replenished in a solution container and redirected into the deposition chamber.

Abstract: A method of assembling large numbers of nanoscale structures in pre-determined ways using fluids or capillary lithography to control the patterning and arrangement of the individual nanoscale objects and nanostructures formed in accordance with the inventive method are provided. In summary, the current method uses the controlled dispersion and evaporation of fluids to form controlled patterns of nanoscale objects or features anchored on a substrate, such as nanoscale fibers like carbon nanotubes.

Abstract: This provides a semiconductor laser device of a high light output efficiency, which is high in current confinement effect, small in leak current, and favorable in temperature property, and indicates a low threshold current, and can effectively confine laser light to a stripe region, and is favorable in beam profile. This semiconductor laser device (100) includes the laminated structure of an n-AlInP clad layer (103), a superlattice active layer section (104), a p-AlInP first clad layer (105), a GaInP etching stop layer (106) are formed, and on top of that, there are a p-AlInP second clad layer (107), a GaInP protective layer (108) and a p-GaAs contact layer (109), which are processed into a stripe-shaped ridge.

Abstract: A two-phase thermal method for the preparation of cadmium sulfide quantum dots where a cadmium source, a sulfur source and a capping agent are heated in water and water-insoluble organic solvents forming a two-phase system. By means of varying reaction time, cadmium sulfide quantum dots of different sizes can be prepared. Quantum dots already obtained can be used as crystal seeds in the reaction of newly added reaction precursor to give larger sized quantum dots with a size distribution similar to that of the initial crystal seeds so as to realize the control of quantum dot size. The quantum dots obtained in the present invention have relatively narrow size distribution, and emit royal purple or blue light under ultraviolet lamp, with a photoluminescence quantum efficiency of from 3 to 60%.

Abstract: A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing a solar grade wafer mold defining an interior for receiving the slurry; introducing the slurry into the solar grade wafer mold; precipitating the silicon powder from the slurry to form a preform of the solar grade silicon wafer; and crystallizing the preform to make the solar grade silicon wafer.

Abstract: An identification code drawing method of drawing an identification code on a substrate includes: cleaning the substrate by using a cleaning unit; performing lyophobization for the substrate; discharging liquid droplets of functional liquid, into which particles of metal or metal oxide are dispersed, from nozzles of a first liquid droplet discharging head onto a region of the substrate having been subjected to the lyophobization, on the basis of liquid droplet discharge data for drawing the identification code; and heating the liquid droplets adhered on the substrate by using a heating unit or drying the liquid droplets adhered on the substrate by using a drying unit.

Abstract: A method of fabricating a pattern on a substrate, comprises the steps of: depositing; such as by ink-jet printing, multiple drops of a first liquid material as a first deposit (15) on the substrate: depositing, such as by ink-jet printing, multiple drops of a second liquid material (17) as a second deposit on the substrate, and in contact with the first material (15) while the first material is liquid, the first and second liquid materials being mutually immiscible; and producing on the substrate a solid deposit from at least one of said liquid materials. In a preferred embodiment, the method comprises ink-jet printing multiple drops of liquid material immiscible with said second liquid material as a third deposit (16) on the substrate, the third deposit (16) being spaced from the first (15) by a predetermined gap and the second deposit (17) applied in said gap overlapping the first and third deposits (15, 16).

Abstract: A process for fabricating at least one semiconductor layer of an electronic device including: performing on a composition including a hydrolyzable zinc compound a number of activities including: (a) hydrolyzing at least a portion of the hydrolyzable zinc compound to form zinc oxide; (b) liquid depositing; and (c) optionally heating, wherein the activities (a), (b), and (c) are each accomplished a number of times in any effective arrangement, resulting in the at least one semiconductor layer comprising the zinc oxide.

Abstract: A method for improving the luminescent efficiency of semiconductor nanocrystals by surface treatment with a reducing agent to produce an improvement in luminescent efficiency and quantum efficiency without creating changes in the luminescent characteristics of the nanocrystals such as luminescence wavelengths and the distribution thereof.

Abstract: Provided is a product including a group of a plurality of wires, in which longitudinal directions of the wires are arranged in one direction, and a method of producing the same. The longitudinal directions of a plurality of wires each covered with a polymer are arranged in one direction in a solvent, and the plurality of the wires whose longitudinal directions are arranged in one direction is fixed by using the polymer.

Abstract: Homogeneous and dense arrays of nanowires are described. The nanowires can be formed in solution and can have average diameters of 40-300 nm and lengths of 1-3 ?m. They can be formed on any suitable substrate. Photovoltaic devices are also described.

Abstract: It is an object of the present invention to provide a porous body containing an oxide semiconductor in which more efficient photocatalytic reactions and photoelectrode reactions occur. The present invention relates to a porous body having a network structure skeleton wherein 1) the aforementioned skeleton is composed of an inner part and a surface part, 2) the aforementioned inner part is substantially made of carbon material, and 3) all or part of the aforementioned surface part is an oxide semiconductor, and to a manufacturing method therefor.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material. Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.

Abstract: To provide a method for manufacturing a wiring, a conductive layer, a display device, and a semiconductor device, each of which can meet a large sized substrate and which is manufactured with a higher throughput by using a material efficiently, the conductive layer is formed over the substrate having an insulating surface by discharging the conductive material, and heat treatment is performed by a lamp or a laser beam over the conductive layer. Furthermore, the conductive film is formed under reduced pressure according to the present invention.

Abstract: A light-emitting device and optical communication system based on the light-emitting device is disclosed. The light-emitting device is formed in a float-zone substrate. The light-emitting device includes on the substrate lower surface a reflective layer and on the upper surface spaced apart doped regions. The portion of the upper surface between the doped regions is textured and optionally covered with an antireflection coating to enhance light emission. The light-emitting device can operate as a laser or as a light-emitting diode, depending on the reflectivities of the antireflection coating and the reflective layer.

Abstract: A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress to it.

Abstract: To provide a semiconductor device composed of a semiconductor element or a group of semiconductor elements, in which a crystalline semiconductor film having as few grain boundaries as possible in a channel formation region is formed on an insulating surface, which can operate at high speed, which have high current drive performance, and which are less fluctuated between elements.

Abstract: A substrate is patterned by forming an indent region 8 in the surface 10 of a substrate 4 and depositing a liquid material onto the surface 10 at selected locations adjacent to the indent region 8. The liquid material spreads over the surface to an edge of the indent region, at which point further spreading is controlled by the effective enhancement of the contact angle of the liquid material relative to the surface as provided by the indent region.

Abstract: In a semiconductor device fabrication method using a fluidic self-assembly technique in which in a liquid, a plurality of semiconductor elements are mounted in a self-aligned manner on a substrate with a plurality of recessed portions formed therein, protruding potions that are inserted in the respective recessed portions of the substrate are formed in the lower portions of the respective semiconductor elements, the liquid in which the semiconductor elements have been spread is poured over the substrate intermittently, and the substrate is rotated in a period of time in which the liquid is not poured.

Abstract: A manufacturing method of a circuit substrate, in which an electronic circuit is formed on a surface of a base member by a solution jetting device. The manufacturing method comprises: jetting liquid drops of a solution which is supplied into a nozzle having a discharge port with an inner diameter of 0.1 ?m to 100 ?m and includes a plurality of fine particles to form an electronic circuit by melting and sticking to one another and a dispersant for dispersing the fine particles, from the discharge port toward the surface of the base member by applying a voltage of an arbitrary waveform to the solution to charge the solution; and exposing the jetted liquid drops received on the surface of the base member to light or heat to make the fine particles melt and stick to one another.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: An electrode manufacturing method comprises: forming plural protruding portions on a surface of a substrate; introducing first particles having a size that changes according to heat, light, or a first solvent between said plural protruding portions; changing the size of the first particles by applying heat, light, or the first solvent to said first particles; and depositing an electrode material onto the surface of said substrate.

Abstract: A method of manufacturing a device comprising individual thin films including a silicon film, a gate insulating film, a conductive film for a gate electrode, an interlayer insulating film, and a conductive film for an electrode and wiring, comprising: a step of applying a liquid material to form an applied film; and a heat treatment and/or a light irradiating treatment of making the applied film into the silicon film, wherein, as the liquid material, a high-order silane composition comprising a high-order silence formed by photopolymerization by irradiating a silane compound solution having a photopolymerization property with UV rays is used.

Abstract: Metal-grade silicon is melted and solidified in a mold to form a plate-shaped silicon layer and a crystalline silicon layer is made thereon, thereby providing a cheap solar cell without a need for a slicing step.

Abstract: A method for producing a laminate having resin layers and thin metal layers by repeating a process unit comprising a step of laminating a resin layer by applying a resin material, a step of depositing a patterning material on the resin layer and a step of laminating a thin metal layer, predetermined times on a turning support (511), wherein the patterning material is stuck on the surface of the resin layer in a noncontact way. A laminate comprising a large number of laminate units each comprising a resin layer and a thin metal layer divided at an electric insulation stripe part can be produced stably. The laminate is applicable to production of a high performance small capacitor at low cost.

Abstract: In a method of manufacturing oxide thin film by adsorbing or depositing oxide forming starting material on a substrate followed by oxide formation, by using water in a liquid state to manufacture the oxide thin film, the advantages of the ALD method are utilized while resolving the tendency to leave impurities in the oxide film produced that is a drawback thereof, so that oxide thin film can be obtained having a reduced concentration of impurities.

Abstract: A method of coating a semiconductor substrate material with a coating material consisting of the steps of mixing an adhesion promoter with a coating material and applying the mixture to a semiconductor substrate material. The invention also includes means for coating a semiconductor substrate material with a coating material comprising means for mixing adhesion promoters with coating materials and means for applying the mixture of adhesion promoters and coating materials to a semiconductor substrate.

Abstract: A method and an apparatus for growing a layer on one surface of a wafer by liquid phase deposition are provided. At first, a first wafer is putted on a first wafer-holder by its first surface. Then, a growth-liquid vessel having a first opening at the bottom is mounted on the first wafer-holder. Thereafter, a growth liquid is poured into the growth-liquid vessel to expose a second surface of the first wafer to the growth liquid for growing the layer on the second surface of the first wafer. Then, the, first wafer is taken out from the first wafer-holder to obtain a wafer with a layer grown only on one surface.

Abstract: A method is provided to produce thin polycrystalline films having a single predominant crystal orientation. The method is well suited to the production of films for use in production of thin film transistors (TFTs). A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize the amorphous silicon to form a film with a preferred crystal orientation. The crystallized film is then polished to a desired thickness for subsequent processing.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: The present invention provides a method for producing a semiconductor substrate which comprises the steps of growing a first semiconductor layer on a substrate in liquid phase at a properly controlled temperature for eliminating defects and growing a second semiconductor layer on the first semiconductor layer in liquid phase at a higher temperature; a solar cell produced by a method comprising a step of anodizing the surface of the first and second layer side of the semiconductor substrate produced by the liquid-phase growth method; a liquid-phase growth apparatus comprising means for storing a melt, means for changing the temperature of the stored melt, and means for bringing an oxygen-containing substrate into contact with the melt, wherein a substrate is brought into contact with the melt at a temperature so as to suppress the stacking faults contained in the semiconductor layer grown on the surface of the substrate.