Abstract: A silicon wafer for epitaxial growth consisting of a highly boron-doped silicon single crystal wafer, an antimony-doped silicon single crystal wafer or a phosphorus-doped silicon single crystal wafer, which allows easy oxygen precipitation and exhibits high gettering ability in spite of its suppressed oxygen concentration, and an epitaxial silicon wafer in which an epitaxial layer grown by using the aforementioned wafer as a substrate wafer has an extremely low heavy metal impurity concentration are produced with high productivity and supplied. The present invention relates to a boron-doped silicon single crystal wafer having a resistivity of from 10 m&OHgr;·cm to 100 m&OHgr;·cm, an antimony-doped silicon single crystal wafer, or a phosphorus-doped silicon single crystal wafer, which are produced by slicing a silicon single crystal ingot grown by the Czochralski method with nitrogen doping.

Abstract: A first trench is formed in a surface of an n+-type semiconductor substrate that forms a source region. A p-type base region, an n−-type drift region, and an n+-type drain region are deposited in this order in the first trench using epitaxial growth. A second trench extending from the source region to the drift region through the base region is formed in the surface. A gate insulating film and a gate electrode are formed on a surface defining the second trench. The n+-type drain region has a location where growing surfaces come together in epitaxial growth and where a defect is likely to occur, and the gate electrode lacks such a location and thus avoids an increase in normalized ON resistance. Therefore, the breakdown voltage remains high without increasing the ON resistance.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: An oxide film is formed on an insulating substrate by means of a wet type film forming technique such as a sol-gel method, a chemical deposition method or a liquid phase deposition method. Next, the oxide film is patterned according to the shape of interconnections. Then, a metal film made of Ni is formed on an oxide film pattern by such a wet type film forming technique as a wet type plating method. Further, a metal film made of Au that has a low resistance is laminated on the metal film made of Ni by electroless plating, and a metal film made of Cu that has a low resistance and is low cost is laminated on the Au film by electroplating. Thus, by the above method for manufacturing electric interconnections, a large-area interconnection substrate for a display device and an image detector is able to be fabricated at low cost without using a vacuum film forming apparatus.

Abstract: An epitaxial semiconductor crystal plate or wafer capable of attaining increased reliability with enhanced luminance, a manufacturing method thereof, as well as a light-emitting diode (LED). It has been found that epitaxial wafers with enhanced illuminance and increased yield of manufacture can be fabricated by specifically arranging a double-heterostructure epitaxial wafer such that the interface between its p-type clad layer 2 and p-type GaAlAs active layer 3 and that between an n-type GaAlAs clad layer 4 and p-type GaAlAs active layer 3 measure 1×1017 cm−3 or less in oxygen concentration. Also, in order to cause the oxygen concentration near the p-type GaAlAs active layer 3 in layers of the epitaxial wafer to be less than or equal to 1×1017 cm−3, it may be preferable that a nondoped GaAs polycrystal for use as a preselected original material in liquid-phase epitaxial growth be less than or equal to 1×1016 cm−3 or there about.

Abstract: A wafer cassette comprises a holding member having a depression corresponding to the shape of the substrate, and a cover having an opening smaller than the surface size of the substrate. The substrate is to be held in the depression by means of the holding member and the cover, and the substrate is to be covered at its one-side surface, side and all peripheral region of the other-side surface, with the holding member at its depression and with the cover at the edge of its opening. Also disclosed are a liquid-phase growth system and a liquid-phase growth process which make use of the wafer cassette.

Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

Abstract: Metal-grade silicon is melted and solidified in a mold to form a plate-shaped silicon layer and a crystalline silicon layer is made thereon, thereby providing a cheap solar cell without a need for a slicing step.

Abstract: In this invention, one or more metal-containing sources and one or more ammonium halides are heated such that they evaporate into a vacuum environment (except that, in MOMBE, a beam of the organometallic source compound may be created by other means) and made to impinge on a substrate. The materials interact on the substrate to form a film of the desired nitride compound or alloy; the substrate usually will be heated to promote chemical reaction and good film properties such as high crystallinity. Other sources—to provide dopant impurities like silicon or magnesium, for example—would be part of a deposition system envisioned in this invention. Multiple film layers, including quantum wells and superlattices, may be formed using this method, in addition to a single film.

Abstract: A method is designed to manufacture a silicon epitaxial wafer exhibiting sufficient gettering capability from the initial stage of the device process. Specifically, the method is to manufacture the silicon wafer with a nitrogen concentration of at least 1×1012 atoms/cm3 and an oxygen concentration of 10˜18×1017 atoms/cm3 by annealing at a temperature of 800 ˜1,100° C.

Abstract: A method of polishing copper with reduced erosion and dishing by a multi-step polishing technique is provided. In one aspect of the invention, a copper layer is polished at a first removal rate and then polished at a second removal rate less than the first removal rate. In another aspect, a computer readable medium is provided bearing instructions, the instructions arranged, when executed by one or more processors, to cause one or more processors to control a polishing system to polish the substrate surface at a first removal rate on a first platen and then polished at a second removal rate less than the first removal rate on a second platen. Further embodiments of the invention include reducing dishing by: controlling platen rotating speeds; increasing the concentration of active chemicals; and cleaning the polishing pads between substrates.

Abstract: An epitaxial semiconductor wafer characterized by making the P-N junction face which having either flat or uneven face in a manner of uniformed thickness from the top surface, due to making a P or N type first layer by the Chemical Vapor Deposition on the basic plate and also to making a N or P type secondary layer on said first layer, while both of the layers being highly and pure controlled silicon, and the light reflectors being located at the out side of said each P or N type layer for concentrating the incoming light to the P-N junction portion.

Abstract: A method for fabricating a thin film field effect transistor is described in this invention. The active layer of the thin film transistor (TFT) is formed by a low cost chemical bath deposition method. The fabrication procedure includes deposition of a metal layer on an insulating substrate, patterning of the metal layer to form a metal gate, formation of the di-electric layer, deposition of the active layer and formation of source and drain contacts.

Abstract: A method for recycling a used silicon wafer on which ICs have been formed by IC fabrication equipment comprised of first grinding the wafer using a coarse grinding apparatus and then grinding the wafer suing a fine grinding apparatus. The coarse grinding apparatus and the fine grinding apparatus are identical to one another except for the nature of the respective grinding they perform. Deionized water is used during both grinding processes to reduce friction and to control dust. The used wafer is first mounted on a chuck of the coarse grinding apparatus that rotates at a first predetermined speed. A diamond wheel mounted on a grinding wheel holder of the coarse grinding apparatus rotates at a second predetermined speed that is faster than the first speed. The rotating wheel and the rotating wafer are brought into contact with one another and the wafer is ground until a predetermined amount of semiconductor material is removed from the face of the wafer.

Abstract: A process for removing copper from a boron doped, polished silicon wafer which contains copper on its polished surface and in its interior. In the process, the wafer is annealed at a temperature of at least about 75.degree. C. to increase the concentration of copper on the polished surface of the wafer and decrease the concentration of copper in the interior of the wafer. The polished surface of the annealed wafer is then cleaned to reduce the concentration of copper thereon. In addition, the annealing step is carried out at a temperature and a time such that the concentration of copper on the polished surface of the silicon will not increase by a factor of more than two upon storage of the annealed and cleaned wafer at room temperature for a period of 5 months.

Abstract: A method of fabricating bit lines by damascene. A substrate having a first dielectric layer is provided, and a bit line contact is formed within the first dielectric layer. A hard material layer is formed on the first dielectric layer to expose the bit line contact. A second dielectric layer is formed on the hard material layer. An opening and a trench are formed within the second dielectric layer to expose the bit line contact and the hard material layer. A hard material spacer is formed on the sidewall of the opening and the trench. A tungsten silicide layer fills the opening and the trench to serve as a bit line on the bit line contact and an interconnect of the bit line.

Abstract: A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.

Abstract: Disclosed is a method of forming quantum wires for compound semiconductors capable of forming a large number of quantum wires. Quantum wires for compound semiconductors according to the present invention are formed by the following processes. First, a compound semiconductor substrate is provided and Al.sub.X Ga.sub.1-X As layers and GaAs layers are then formed alternately on the substrate to predetermined times to form a quantum well. Next, a plurality of grooves are formed in the upper most GaAs layer to a predetermined depth wherein the grooves are separated with a predetermined space from each other. Stress is applied to the quantum well such that the Al.sub.X Ga.sub.1-X As layers surround the GaAs layers to thereby form a large number of quantum wires.

Abstract: Thermal dye sublimation transfer recording element for receiving sublimable basic dye-precursors, comprising a support having thereon a dye-developing layer containing a dye-developing copolymer having sulfonic acid side-groups that can react with the basic dye-precursor to produce a dye image, characterized in that said dye-developing vinyl copolymer comprises plasticizing comonomers, the weight percentage of plasticizing comonomers in the dye-developing vinyl copolymer being such that the glass transition temperature of the dye-developing vinyl copolymer is between 30.degree. C. and 90.degree. C.