Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.

Abstract: This nitride-based semiconductor light-emitting element includes: a nitride-based semiconductor multilayer structure including a p-type semiconductor region, the nitride-based semiconductor multilayer structure having a growing plane which is an m-plane; and an electrode which is arranged on an AldGaeN layer. The AldGaeN layer is formed of a GaN-based semiconductor. The electrode includes Ag as the principal component and also includes Ge and at least one of Mg and Zn.

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract: A method is provided for forming a dopant profile based on a surface of a wafer-like semiconductor component with phosphorus as a dopant. The method includes the steps of applying a phosphorus dopant source onto the surface, forming a first dopant profile with the dopant source that is present on the surface, removing the dopant source, and forming a second dopant profile that has a greater depth in comparison to the first dopant profile. In order to form an optimized dopant profile, the dopant source is removed after forming the first dopant profile, and precipitates that are crystallized selectively on or in the surface from the precipitates SixPy and SixPyOz are removed.

Abstract: A method for an improved doping process allows for improved control of doping concentrations on a substrate. The method may comprise printing a polymeric material on a substrate in a desired pattern; and depositing a barrier layer on the substrate with a liquid phase deposition process, wherein a pattern of the barrier layer is defined by the polymeric material. The method further comprises removing the polymeric material, and doping the substrate. The barrier layer substantially prevents or reduces doping of the substrate to allow patterned doping regions to be formed on the substrate. The method can be repeated to allow additional doping regions to be formed on the substrate.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.

Abstract: CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.

Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.

Abstract: A first facet of each of a plurality of pyramids on a surface of a workpiece is doped to a first dose while a second facet and a third facet of each of the plurality of pyramids is simultaneously doped to a second dose different than the first dose. The first facets may enable low resistance contacts and the second and third facets may enable higher current generation and an improved blue response. Ion implantation may be used to perform the doping.

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract: An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

Abstract: A method and apparatus for reducing external series resistance (Rext) has been becoming a more dominant component of the total series resistance between the MOSFET source and drain. A significant part of Rext (25-35%) comes from the interface resistance (RC) between the metal (silicide) and source/drain (S/D) silicon diffusion regions. RC is determined by the specific contact resistivity (?c) at the silicide/silicon interface, the S/D silicon sheet resistivity at the silicide/silicon interface (RS/D), and the contact length (LC). The LC has been and will be decreasing by about 30% from one CMOS technology node to the next, resulting in increased RC and Rext. To maintain or reduce RC with respect to state-of-the-art value, one must reduce ?c. This may be accomplished using a metal-dopant alloy having a dopant material that can diffuse into the semiconductor layer during annealing to provide contact and ultralow resistance at the interface.

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract: A method is provided for forming a dopant profile based on a surface of a wafer-like semiconductor component with phosphorus as a dopant. The method includes the steps of applying a phosphorus dopant source onto the surface, forming a first dopant profile with the dopant source that is present on the surface, removing the dopant source, and forming a second dopant profile that has a greater depth in comparison to the first dopant profile. In order to form an optimized dopant profile, the dopant source is removed after forming the first dopant profile, and precipitates that are crystallized selectively on or in the surface from the precipitates SixPy and SixPyOz are removed.

Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.

Abstract: A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: Watercraft automation and aquatic data utilization for aquatic efforts are utilized for fishing and network communication. In one aspect, an anchor point is obtained and a water craft position maintenance routine is actuated to control the watercraft to maintain association with the anchor point. In another aspect, prior aquatic effort data is obtained in association with an anchor point. In yet another, aspect, current aquatic effort data is generated in association with an anchor point. In still another aspect, current aquatic effort data and prior aquatic effort data are utilized for prediction generation. In yet another aspect, current aquatic effort data and prior aquatic effort data are utilized to obtain another anchor point for a watercraft.

Abstract: Watercraft automation and aquatic data utilization for aquatic efforts are utilized for fishing and network communication. In one aspect, an anchor point is obtained and a water craft position maintenance routine is actuated to control the watercraft to maintain association with the anchor point. In another aspect, prior aquatic effort data is obtained in association with an anchor point. In yet another, aspect, current aquatic effort data is generated in association with an anchor point. In still another aspect, current aquatic effort data and prior aquatic effort data are utilized for prediction generation. In yet another aspect, current aquatic effort data and prior aquatic effort data are utilized to obtain another anchor point for a watercraft.

Abstract: Watercraft automation and aquatic data utilization for aquatic efforts are utilized for fishing and network communication. In one aspect, an anchor point is obtained and a water craft position maintenance routine is actuated to control the watercraft to maintain association with the anchor point. In another aspect, prior aquatic effort data is obtained in association with an anchor point. In yet another, aspect, current aquatic effort data is generated in association with an anchor point. In still another aspect, current aquatic effort data and prior aquatic effort data are utilized for prediction generation. In yet another aspect, current aquatic effort data and prior aquatic effort data are utilized to obtain another anchor point for a watercraft.

Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.

Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface. The method further includes depositing an ink on the front substrate surface in a ink pattern, the ink comprising a set of silicon-containing particles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified film ink pattern.

Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.

Abstract: A method for the selective doping of silicon of a silicon substrate (1) for producing a pn-junction in the silicon is characterized by the following steps: a) Providing the surface of the silicon substrate (1) with a doping agent (2) based on phosphorous, b) heating the silicon substrate (1) for creating a phosphorous silicate glass (2) on the surface of the silicon, wherein phosphorous diffuses into the silicon as a first doping (3), c) applying a mask (4) on the phosphorous silicate glass (2), covering the regions (5) that are later highly doped, d) removing the phosphorous silicate glass (2) in the non-masked regions, e) removing the mask (4) from the phosphorous silicate glass (2), f) again heating for the further diffusion of phosphorous from the phosphorous silicate glass (2) into the silicon as a second doping for creating the highly doped regions (5), g); complete removal of the phosphorous silicate glass (2) from the silicon.

Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3, the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate is operatively coupled to the source region and is located offset from the drain region on a side of the source region opposite from the drain region. When the device is in an on state, current tends to flow deeper into the drift region to the offset gate, rather than near the device surface. The drift region preferably includes at least first and second stacked JFETs.

Abstract: In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.

Abstract: CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.

Abstract: An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced into the semiconductor body.

Abstract: Semiconductor devices and methods for fabricating the same are disclosed. The semiconductor device includes gate electrodes having sidewall spacers on a semiconductor substrate, double diffusion drain regions in the semiconductor substrate adjacent to the sidewall spacers, double diffusion junction regions aligned with the gate electrodes, and source/drain regions in the double diffusion junction regions.

Abstract: A laser medium comprises a solid-state host material and dopant species provided within the solid-state host material. A first portion of the dopant species has a first valence state, and a second portion of the dopant species has a second valence state. In an embodiment, a concentration of the first portion of the dopant species decreases radially with increasing distance from a center of the medium, and a concentration of the second portion of the dopant species increases radially with increasing distance from the center of the medium. The laser medium further comprises impurities within the solid-state host material, the impurities converting the first portion of the dopant species having the first valence state into the second portion of dopant species having the second valence state.

Abstract: A manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the method manufacturing costs can be reduced. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch<Lg<Lwell is satisfied; and the channel regions are further formed by diffusing by activation annealing boron as a third impurity, having been implanted by activation annealing into the source regions, into a silicon carbide layer.

Abstract: A method of manufacturing a solar cell. The method includes the steps of providing a substrate, applying a first dopant to a first surface, applying a second dopant to a second surface, covering the doped first surface with a hard mask, applying a third dopant to the substrate side, removing the hard mask, applying a pattern of first electrical contacts to the doping pattern, and applying a pattern of second electrical contacts to the doped second surface, the pattern of second electrical contacts and the doping pattern being straight-lined opposed.

Abstract: Methods for selectively diffusing dopants into a substrate wafer are provided. A liquid precursor is doped with dopants. The liquid precursor is selected from a group comprising monomers, polymers, and oligomers of silicon and hydrogen. The doped liquid precursor is deposited on a surface of the substrate wafer to create a doped film. The doped film is heated on the substrate wafer for diffusing the dopants from the doped film into the substrate wafer at different diffusion rates to create a heavily diffused region and a lightly diffused region in the substrate wafer. The method disclosed herein further comprises selective curing of the doped film on the surface of the substrate wafer. The selectively cured doped film acts as a diffusion source for selectively diffusing the dopants into the substrate wafer.

Abstract: Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.

Abstract: Disclosed are a semiconductor device producing method and a semiconductor device. The semiconductor device producing method is comprised of a step of forming a diffusion suppressing mask composed of at least two of a thick film portion, an opening portion, and a thin film portion, on a surface of a semiconductor substrate; a step of applying dopant diffusing agents containing dopants to the entirety of a surface of the diffusion suppression mask; and a step of diffusing the dopants obtained from the dopant diffusing agents onto the surface of the semiconductor substrate. In the semiconductor device, a high concentration first conductive dopant diffusion layer, a high concentration second conductive dopant diffusion layer, a low concentration first conductive dopant diffusion layer, and a low concentration second conducive dopant diffusion layer are provided on one of the surfaces of the semiconductor substrate.

Abstract: A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.

Abstract: A method for forming a selective emitter of a solar cell and a diffusion apparatus for forming the same are provided. The method includes texturing a surface of a silicon substrate by etching the silicon substrate, coating an impurity solution on the surface of the silicon substrate, injecting a first thermal energy into the whole surface of the silicon substrate, and, while the first thermal energy is injected into the whole surface of the silicon substrate, injecting a second thermal energy by irradiating a laser beam into a partial region of the surface of the silicon substrate.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.

Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm?3 and 2*1017 cm?3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 ?m. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm?3 and 1*1015 cm?3 is reached between a first depth, which is at least 20 ?m, and a second depth, which is at maximum 50 ?m. Such a profile of the doping concentration is achieved by using aluminium diffused layers as the at least two sublayers.

Abstract: A high-voltage semiconductor device and a method for making the same are provided. A high-voltage semiconductor device and a low-voltage semiconductor device are formed in a single substrate, a photolithography process that is required to form a high-voltage well region is omitted, and the well region of the high-voltage semiconductor is formed together with the well region of the low-voltage semiconductor device formed in another photolithography process.

Abstract: A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from th

Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.