Abstract: A semiconductor arrangement and a method for manufacturing the semiconductor arrangement are provided, which arrangement and method allow an improvement in the current-carrying capacity for given chip dimensions. The semiconductor arrangement includes trenches introduced in the interior of the chip, which trenches reduce power loss and improve the heat dissipation of the chip, as well as reduce the forward voltage of diode.

Abstract: As impurity ions for forming a channel, heavy ions are implanted multiple times at a dose such that no dislocation-loop defect layer is caused to be formed, and an annealing process is performed after each ion implantation process has been carried out, thereby forming a heavily doped channel layer having a steep retro-grade impurity profile.

Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.

Abstract: The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for forming a mask layer having a through-hole provided in the position where a tunnel window is to be formed, on top of said gate insulator film; a step for forming an impurity region in the vicinity of the surface of said semiconductor substrate by introducing an impurity using the mask layer; and a step for forming a tunnel insulator film on the surface of the semiconductor substrate, using a mask layer. In the present invention, the position in which the source is formed and the position in which the tunnel window is formed are determined by means of the position of the same through-hole. Therefore, the manufacturing error in the distance between the tunnel window and the source can be nullified.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of germanium, where the concentration of germanium decreases between a first depth and a second depth in the base. According to this exemplary embodiment, the base of the heterojunction bipolar transistor further comprises a concentration of a diffusion suppressant of a base dopant, where the concentration of the diffusion suppressant decreases between a third depth and a fourth depth so as to counteract a change in band gap in the base between the first depth and the second depth. For example, the diffusion suppressant can be carbon and the base dopant can be boron. For example, the concentration of diffusion suppressant may decrease between the third depth and fourth depth so as to counteract the change in band gap at approximately the second depth.

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract: Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric field can be chosen to have approximately the same magnitude in all of the compensation regions.

Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.

Abstract: A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p−n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Abstract: Disclosed are apparatus and methods for forming abrupt junctions in semiconductor devices. Initially, a substrate (200) is implanted with an amorphizing element (208) in a desired area (300), rendering the melting point of the desired area lower than the melting point of the substrate surrounding the desired area. A desired dopant (302) is implanted into the desired area, and the desired area is then annealed by an energy source (402, 506) such that only the desired area melts, allowing the dopant to diffuse throughout only the desired area.

Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.

Abstract: A method for forming a thin film transistor with lightly doped drain structure comprising the steps of forming a gate insulating layer and a gate electrode on a polysilicon layer; forming a photoresist layer with a predetermined thickness on the gate electrode and on a portion of the polysilicon layer; and implanting first conductive type impurities into the polysilicon layer so as to form a first ion-implant region and a second ion-implant region, wherein the doping concentration of the second ion-implant region is higher than that of the first ion-implant region.

Abstract: A low noise microwave MOSFET fabricated with source-side halo implantation. The dopant concentration has an asymmetrical horizontal profile along the channel from the source to the drain.

Abstract: A method for varying the resistance along a conductive layer. The method including the step of removing at least a portion of a resistance-altering constituent diffused within the conductive layer.

Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.

Abstract: To form an impurity diffusion layer on only one side of a semiconductor substrate at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is perfomed on them, or at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is performed on them and then the semiconductor substrate and the diffusion protecting plate are arranged such that those sides on which the impurity diffusion has been performed face each other and a second impurity diffusion is performed. The diffusion protecting plate may be replaced by a semiconductor substrate. The first and second impurity diffusions may be performed using an impurity of the same conductivity type.

Abstract: A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.

Abstract: A semiconductor device includes a silicon layer. The silicon layer includes a lower silicon layer and an upper silicon layer which is formed on the lower layer. A concentration of impurities in the upper silicon layer is higher than that of the lower silicon layer.

Abstract: A semiconductor integrated circuit device comprises an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed so as to surround a part of the substrate 1, in which a p−-type well is formed, a p−-type well 15-1 formed in the substrate 1, a p−-type well 15-2 formed in a part of the substrate 1, which is surrounded by the n-type well, an embedded n-type well 12-1 formed below the p-type well 15-1, and an n-type well 12-2 which is formed below the p−-type well 15-2 and which is connected to the n-type well 8-2. Thus, it is possible to provide a semiconductor integrated circuit device capable of suppressing the increase of the number of photolithography steps and reducing the manufacturing costs.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.

Abstract: A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

Abstract: A method of forming a triple well structure. A first photoresist layer is formed on a substrate having a first conductive type. A first ion implantation process is performed to form a first well, which has the first conductive type but a dopant concentration of the first well is higher than a dopant concentration of the substrate. The first photoresist layer is baked. A second ion implantation process is performed through the baked first photoresist layer to form a first doped region under the first well. The first doped region has a second conductive type. After removing the first photoresist layer, a second photoresist layer is formed on the substrate. A third ion implantation process is performed to form a second doped region in the substrate around the first well and to form a second well in the substrate. The second doped region and the second well have the second conductive type. The second doped region and the first doped region together surround the first well.

Abstract: A method of making a semiconductor device includes performing a doping implant through a layer of dielectric material. The implanting through dielectric material enables use of high-energy implants to form shallow doped regions. Other implanting steps may also be combined with the implanting through the dielectric material.

Abstract: A transistor of a second conductivity type is of an LMOS structure, and a transistor of a first conductivity type is of an LDMOS structure. The transistor of the first conductivity type has a drain base layer which functions in the same manner as a drain offset diffusion layer and is formed in a substrate separately from a source base diffusion layer. The transistor of the first conductivity type has a stably high breakdown voltage and a low on-state resistance as with the transistor of the second conductivity type.

Abstract: In a semiconductor thin-film formation process comprising feeding a semiconductor thin-film material gas into a discharge space, and applying a high-frequency power thereto to cause plasma to take place and decompose the material gas to form an amorphous semiconductor thin film on a desired substrate, the high-frequency power is applied changing its power density continuously or stepwise from a high power density to a low power density and thereafter again changing the power density continuously or stepwise from a low power density to a high power density, to form a semiconductor thin film made different in film quality in the direction of layer thickness while retaining the same conductivity type This process enables formation of high-quality semiconductor thin films by plasma CVD.

Abstract: The object of the invention is to reduce an outer circumferential edge removing width of the SOI wafer when a bonded SOI wafer is made and prevent deposition of polysilicon at the outer circumference of the SOI layer when an epitaxial layer is grown. An SOI layer is formed by the steps of forming an oxide film on a surface of at least one silicon wafer of two silicon wafers, bonding the other silicon wafer through said oxide film at a room temperature, the wafers are heat treated in oxidizing atmosphere, thereafter an outer periphery of a bond wafer is removed from an outer peripheral edge of the bond wafer up to a region between bonding ends through bonding at a room temperature and heat treatment bonding ends and making the bond wafer into a thin film of desired thickness.

Abstract: The invention relates to a method of iteratively, selectively tuning the impedance of integrated semiconductor devices, by modifying the dopant profile of a region of low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of higher dopant concentration through the melting action of a focussed heating source, for example a laser. In particular the method is directed to increasing the dopant concentration of the region of lower dopant concentration, but may also be adapted to decrease the dopant concentration of the region.

Abstract: A method of providing a field effect transistor includes depositing a layer of a laser-reflective material on a substrate which has an active region and an inactive region; selectively removing portions of the deposited layer disposed over the active region; exposing laser energy to activate dopants in the active region; and stripping the deposited layer.

Abstract: This invention discloses a novel method for fabricating solar cells. Using the existing screen-printing, masking or photolithography techniques, a P-type or N-type diffusion source is coated on the sites of an N-type or P-type silicon wafer desired for forming electrodes. Then, a low dose P-type or N-type diffusion source is in situ diffused into the N-type or P-type silicon wafer together with the P-type or N-type diffusion source coated on the N-type or P-type silicon wafer in the furnace. Thereafter, a P−/P+ or N−/N+ diffusion region is formed within the N-type or P-type silicon wafer. Finally, electrodes aligned to the P+ or N+ diffusion region are formed by means of screen-printing. Then, a solar cell with high photocurrent and low series resistance can be obtained.

Abstract: In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.

Abstract: A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region hav

Abstract: A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.

Abstract: The invention describes a method of fabricating the integration of high-voltage devices and low-voltage devices. The ion implantation steps for forming the isolation doping regions and the drafting doping regions in the high-voltage device are used to form simultaneously the anti-punch-through regions in the low-voltage device. The production of the integrated circuit is then finished with other process steps.

Abstract: In a process for adjusting the carrier lifetime in a semiconductor component (1) by means of particle irradiation (P), at least two defect regions (10, 11, 12, 13) are produced in the semiconductor component (1). In this process, a particle beam (P), consisting of particles (a, b, c, d) with at least approximately the same initial energy, is acted on by at least one means (2), before reaching the semiconductor component (1), in such a way that the particles (a, b, c, d) subsequently have different energy values, at least two energy value groups being distinguishable. It is thereby possible, with a single particle irradiation operation, to produce an arbitrary number of defect regions whose arrangement and weighting is arbitrarily selectable.

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract: Bridged, doped zones are formed in a semiconductor. A silicon nitride layer is deposited and structured on a semi-conductor region with a predetermined dopant concentration. The structure is subjected to thermal oxidation, with the result that at least one oxide region and at least two oxide-free regions, which are separated from one another by the oxide region, are produced on the surface of the semiconductor region. A dopant is introduced into the oxide-free regions and driven into the semiconductor region. A coherent zone is thus produced in the semiconductor region with a dopant concentration at least ten times the dopant concentration of the semiconductor region. This produces a coherent zone having a high dopant concentration which is bridged by the oxide region which separates the oxide-free regions on the surface of the semiconductor region.

Abstract: A structure and method for forming a semiconductor structure includes forming a plurality of device layers on a substrate (the device layers including a blocking layer having a thickness correlating to a magnitude of implant attenuation), removing the blocking layer from selected devices of the semiconductor, and implanting an impurity into the substrate, the device layers and partially through the blocking layer.

Abstract: A method for altering a dopant front profile of a dopant in a wafer is disclosed. An initial wafer is provided with an upper doped layer and a lower undoped layer. An oxide layer is grown over a portion of the wafer while a second portion of the wafer remains oxide-free. The wafer is then exposed to a substantially non-growth enhancement diffusion environment that contains the dopant at a given flow rate, but lacks additional materials which would cause growth on the exposed portions of wafer. After a predetermined amount of diffusion is allowed to occur, the wafer is removed from the diffusion environment and the oxide layer is removed.

Abstract: Methods of forming power semiconductor devices having merged split-well body regions include the steps of forming a semiconductor substrate containing a drift region of first conductivity type (e.g., N-type) therein extending to a first face thereof. First and second split-well body regions of second conductivity type (e.g., P-type) may also be formed at spaced locations in the drift region. First and second source regions of first conductivity type are also formed in the first and second split-well body regions, respectively. A central body/contact region of second conductivity type is also formed in the drift region, at a location intermediate the first and second split-well body regions. The central body/contact region preferably forms non-rectifying junctions with the first and second split-well body regions and a P-N rectifying junction with the drift region at a central junction depth which is less than the maximum well junction depths of the split-well body regions.

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Abstract: A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the gate and the diffused resistor, forming a masking layer over the insulating layer that covers the resistor region and includes an opening above the active region, applying an etch using the masking layer as an etch mask so that unetched portions of the insulating layer over the active region form spacers in close proximity to opposing sidewalls of the gate and an unetched portion of the insulating layer over the resistor region forms a resistor-protect insulator, and forming a source and a drain in the active region. In this manner, a single insulating layer provides both sidewall spacers for the gate and a resistor-protect insulator for the diffused resistor.

Abstract: The present invention provides a method of etching microelectronic structures. The method utilizes an ion implantation device projecting ions into a silicon semiconductor or conducting substrate to selectively damage the surface causing damage differential. This process is highly controllable and directable, allowing fine manipulation of the substrate surface. After the ion implantation has destroyed selected portions of the surface, standard etching techniques known in the art can be used to selectively remove the damaged portions of the surface. The advantage of this technique is that it confers upon relatively imprecise prior art etching techniques a high degree of precision. Such techniques can be used to create isolation trenches by filling the surface with electrically isolating materials which isolate one semiconductor device from another.

Abstract: A semiconductor processing method of forming an NMOS field effect transistor includes, a) providing a projecting mesa of semiconductive material from a bulk semiconductor substrate, the mesa defining a semiconductor substrate floor and walls rising upwardly therefrom; b) providing a gate dielectric layer and a gate atop the semiconductive mesa; c) providing a pair of opposing LDD regions within the semiconductive mesa, the respective LDD regions running along one of the mesa walls; and d) providing source and drain diffusion regions within the bulk semiconductor substrate floor which respectively interconnect with the opposing LDD regions of the mesa. NMOS field effect transistors are also disclosed.

Abstract: A semiconductor device comprises a semiconductor substrate; a transfer transistor including a gate electrode formed on the semiconductor substrate through a gate insulation film, and a first diffused layer formed in the semiconductor substrate on both sides of the gate electrode; an insulation film which covers an upper surface of the transfer transistor and in which a contact hole reaching the first diffused layer is opened; a capacitor formed on the insulation film and connected to the first diffused layer through the contact hole; a second diffused layer formed in the semiconductor substrate below the contact hole and being the same conduction type as the first diffused layer; and a third diffused layer formed in the semiconductor substrate below the contact hole, formed extending to a region which is deeper than the first and the second diffused layers, and having the same conduction type as the first diffused layer.

Abstract: A method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses is disclosed.

Abstract: A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.

Abstract: To ensure bulk breakdown when the mesa diode with a positive bevel angle is reverse biased, the diffused region is formed with thinner edge portions. This eliminates corner or edge effects which create conditions of high electric field, resulting in decreased breakdown voltage and clamping voltage levels. The edges of the surface of epitaxial region are covered with a narrow oxide layer prior to diffusion. The middle portion of the surface remains uncovered. Diffusing through the oxide results in a diffused region which is thinner along the edges of the device than in the interior region below the exposed surface portion. The oxide thickness controls the depth of the edge diffusion.

Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi

Abstract: A laser doping process comprising: irradiating a laser beam operated in a pulsed mode to a single crystal semiconductor substrate of a first conductive type in an atmosphere of an impurity gas which imparts the semiconductor substrate a conductive type opposite to said first conductive type and incorporating the impurity contained in said impurity gas into the surface of said semiconductor substrate, thereby modifying the type and/or the intensity of the conductive type thereof. Provides devices having a channel length of 0.5 .mu.m or less and impurity regions 0.1 .mu.m or less in depth.

Abstract: A two stage threshold adjust implantation process is performed after field oxidation to avoid the effects of dopant redistribution and segregation. At any of several steps in a manufacturing process, only routine implant energy and dose adjustments are required to create a first and a second dopant profile (110, 120) that result in the reduction of edge leakage and threshold voltage sensitivity to device layer thickness of a semiconductor device on a semiconductor on insulator substrate.