Abstract: Provided is a method for depositing a metal thin film by atomic layer deposition (ALD) using an organometallic complex as a source material and without using radical species such as plasma and ozone, which have a possibility of deactivation. The method is an atomic layer deposition (ALD) method for metal thin films which includes: a process of supplying an organometallic complex having an aromatic anionic ligand and/or an alkyl ligand into a reaction chamber in which a substrate is installed; and a process of supplying a mixture gas containing a nucleophilic gas and an electrophilic gas into the reaction chamber, the ALD method substantially not using either one of a gas in a plasma or radical state and a gas containing oxygen atoms.

Abstract: Systems and methods of reducing outgassing of a substance within a reaction chamber of a reactor are disclosed. Exemplary methods include depositing a barrier layer within the reaction chamber and using a scavenging precursor to react with species on a surface of the reaction chamber. Exemplary systems include gas-phase deposition systems, such as atomic layer deposition systems, which include a barrier layer source and/or a scavenging precursor source fluidly coupled to a reaction chamber of the system.

Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Abstract: A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

Abstract: The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.

Abstract: A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer.

Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing (100) platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing (102) platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming (104) a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating (105) the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Abstract: Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds.

Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.

Abstract: Methods and compositions for the deposition of ternary oxide films containing ruthenium and an alkali earth metal.

Abstract: Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.

Abstract: A method for manufacturing a ZnO based compound semiconductor device including a contact for a p-type ZnO based compound semiconductor electrode is provided. The method includes forming a stacked body including a substrate, and an n-type ZnO based semiconductor layer and a p-type ZnO based semiconductor layer on the substrate, with the p-type ZnO based semiconductor layer exposed to outside. The stacked body is subjected to heat treatment so that a surface temperature of the p-type ZnO based semiconductor layer is in the range of 250° C. to 500° C. After the heat treatment, a p-side metal electrode is formed on the p-type ZnO based semiconductor layer at a temperature lower than 550° C. And an n-side metal electrode is formed on the n-type ZnO based semiconductor layer.

Abstract: A method is disclosed for fabricating an LED The method includes providing an LED chip having an epitaxial region comprising at least a p-type layer and an n-type layer, an ohmic contact formed on at least one of the p-type layer or the n-type layer, and a bond pad formed on the ohmic contact. The bond pad has a total volume less than about 3×10?5 mm3. The LED chip is bonded to a submount via thermocompression or thermosonic bonding.

Abstract: A method for manufacturing electrodes on a semiconducting material of type II-VI or on a compound of this material. The electrodes are preferably in gold or platinum and are formed by electrochemical deposition of gold or platinum from a solution of gold or platinum chloride in pure hydrochloric acid.

Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.

Abstract: Disclosed is a method for fabricating a MOS transistor. The present method includes the steps of: (a) forming a gate electrode including a gate insulating layer and a polysilicon gate conductive layer on an active region in a semiconductor substrate; (b) forming a metal layer over the substrate including the gate electrode; (c) heat-treating the substrate to form a polycide layer on a top surface and sidewalls of the gate electrode; (d) removing an unreacted portion of the metal layer; (e) removing the polycide layer from the top surface and sidewalls of the gate electrode, thus reducing a width of the gate electrode; and (f) forming source and drain regions in the active region adjacent to the gate electrode.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: A semiconductor component (1) has a semiconductor chip (5) and a semiconductor component carrier (3) with external connection strips (12, 13, 15). The semiconductor chip (5) has a first electrode (6) and a control electrode (7) on its top side (8) and a second electrode (9) on its rear side (10). The semiconductor chip (5) is fixed by its top side (8) in flip-chip arrangement (11) on a first and a second external connection strip (12, 13) for the first electrode (6) and the control electrode (7). The second electrode (9) is electrically connected to at least one third external connection strip (15) via a bonding tape (14).

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.

Abstract: A power Schottky rectifier device having pluralities of trenches are disclosed. The Schottky barrier rectifier device includes field oxide region having p-doped region formed thereunder to avoid premature of breakdown voltage and having a plurality of trenches formed in between field oxide regions to increase the anode area thereto increase forward current capacity or to shrinkage the planar area for driving the same current capacity. Furthermore, the trenches have rounded corners to alleviate current leakage and LOCOS region in the active region to relief stress during the bonding process. The processes for power Schottky barrier rectifier device including termination region formation need only three masks and thus can gain the benefits of cost down.

Abstract: A method for fabricating a semiconductor device for reducing coupling noise resulting from high integration of devices, comprises the steps of forming a plurality of metal wiring leads spaced from each other by a predetermined distance and arranged on a semiconductor substrate having a predetermined under layer; forming an insulating interlayer on an entire surface of the semiconductor substrate so that the metal wiring leads are covered with the insulating interlayer; and ion-implanting conductive impurities having a plurality opposite to each other into side end layers of the insulating interlayer disposed between the metal wiring leads so as to reduce the internal charges electrified due to an applied external electric field.

Abstract: A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.

Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.

Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.

Abstract: A Schottky diode structure and a method of making the same are disclosed. The method comprises following steps: firstly, a semiconductor substrate having a first conductive layer and an epi-layer doped with the same type impurities is provided. Then a first oxide layer is form on the epi layer. A patterning step to pattern first oxide layer and recess the epi layer (optional) is then followed to define guard rings. After stripping the photoresist pattern, a polycrystalline silicon layer formation is then followed. A boron and/or BF2+ ion implant is then performed. Subsequently, a high temperature drive in process and oxidation process to oxidize the polycrystalline silicon layer and drive ions is then carried out. A second mask and etch steps are then performed to open the active regions. A metallization process is then done. A third mask and etch steps are then implemented to define anode. Finally, a backside metal layer is then formed and serves as a cathode.

Abstract: A WN film serving as an adhesive layer is deposited over the sidewalls and bottom surface of a hole in a silicon oxide film where an information storage capacitor is to be formed. A Ru film to serve as a lower electrode for the information storage capacitor is formed above the WN film by CVD using Ru(HFAC)3, H2O and H2 as ingredients, so that a ratio of partial pressure of H2O to H2 is controlled to be in the area below a curve (a). When the Ru film is formed by CVD utilizing hydrolysis, the film quality of the Ru film can be enhanced. The ratio of partial pressure of H2O to H2 is controlled, whereby oxidation of the Ru film can be suppressed. When it is controlled to be in the area below a curve (b) to form the Ru film, oxidation of the WN film can be suppressed.

Abstract: A WN film serving as an adhesive layer is deposited over the sidewalls and bottom surface of a hole in a silicon oxide film where an information storage capacitor is to be formed. A Ru film to serve as a lower electrode for the information storage capacitor is formed above the WN film by CVD using Ru(HFAC)3, H2O and H2 as ingredients, so that a ratio of partial pressure of H2O to H2 is controlled to be in the area below a curve (a). When the Ru film is formed by CVD utilizing hydrolysis, the film quality of the Ru film can be enhanced. The ratio of partial pressure of H2O to H2 is controlled, whereby oxidation of the Ru film can be suppressed. When it is controlled to be in the area below a curve (b) to form the Ru film, oxidation of the WN film can be suppressed.

Abstract: A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.

Abstract: High quality epitaxial layers of monocrystalline oxide materials (24) are grown overlying monocrystalline substrates such as large silicon wafers (22) using RHEED information to monitor the growth rate of the growing film. The monocrystalline oxide layer (24) may be used to form a compliant substrate for monocrystalline growth of additional layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (24) on a silicon wafer (22) spaced apart from the silicon wafer (22) by an amorphous interface layer of silicon oxide (28). The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (24).

Abstract: Method for forming a Schottky contact in a semiconductor device includes a step of preparing an n type GaN group compound semiconductor layer, such as AlxGa1-xN and InxGa1-xN. At least one metal layer including a ruthenium component layer is formed on the n type GaN group compound semiconductor layer as a rectifying junction metal. The rectifying junction metal may be used as a gate of a field effect transistor, or an electrode of a Schottky diode. The ruthenium oxide has a low cost, is stable to heat and chemical, and has excellent electric characteristics. The application of the ruthenium oxide to the rectifying junction metal enhances performances, such as UV ray detection, of electronic devices and optical devices operable at an elevated temperature.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof.

Abstract: A method of making a flat capacitor includes forming at least one recess on an inside surface of a metal foil blank, leaving a surrounding peripheral flange. A coating performing as an electrode of the capacitor is applied to the inside surface of the metal foil blank and an ion-permeable separator is placed on that inside surface of the metal foil blank. A substantially planar anode with a protruding lead is placed in the recess with the lead extending through a hole of the metal foil blank. Thereafter, the metal foil blank is folded along a line intersecting the hole so that the anode is sandwiched between parts of the separator and the separator is in contact with the coating on the inside surface of the metal foil blank. In the folding process, parts of the peripheral flange of the metal foil blank are brought into contact with each other and these parts are sealed to each other to form a hermetically sealed metal foil case of the capacitor.

Abstract: When films of Ru(C2H5C5H4)2 are formed on a substrate by means of a thermal CVD method, the films are also deposited on members around the substrate, resulting in the formation of particles on the substrate and hence a reduction in the manufacturing yield. Thus, it is necessary to clean the interior of the reaction chamber, but in a conventional cleaning process, a cleaning time is long and hence manufacturing efficiency is low, increasing manufacturing costs. To improve these, a method of manufacturing semiconductor devices according to the present invention includes: a deposition process for forming a film containing Ru on a substrate in a reaction chamber; and a cleaning process for supplying a ClF3 gas to the reaction chamber so as to remove films, which were deposited on an inner surface of the reaction chamber in the deposition process, through thermochemical reactions.

Abstract: Power combining amplifiers using two different monocrystalline materials in a monolithic device are provided. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: A method for producing a Schottky diode formed of a doped guard ring in an edge area of the Schottky contact is described. The guard ring is produced by depositing a high barrier material, especially made of platinum, on the surface of the semiconductor layer. The surface is provided with a structured masking layer beforehand, and which is subsequently etch-backing.

Abstract: A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

Abstract: Ohmic and rectifying contacts to a TaC layer on an n-type or p-type area of an SiC substrate are formed by depositing a WC layer over the TaC layer, followed by a metallic W layer. Such contacts are stable to at least 1150° C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy through a dielectric layer.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: By providing an area where an Au film 28b is removed and a Ti film 28a is exposed along the plane tangent to the side where the p-n junction of a semiconductor chip is exposed, sticking of the Au film 28b to the chip side or protruding of the film as a flash from the side is prevented, which normally provides a starting place for creep of a solder 42 on the chip side, which in turn causes p-n junction short-circuiting when dividing of chips.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: A schottky diode is formed of a sintered barrier metal layer which contacts a lightly doped silicon surface. The barrier metal layer is formed of palladium as well as a small quantity of another metal whose choice is determined by the desired value of the barrier height of the resulting schottky diode. A small quantity of platinum is selected to increase the barrier height, and a small quantity of nickel is selected to decrease the barrier height. A contact metal, which may include a tri-metal layer of titanium, nickel and silver, is formed atop the sintered schottky barrier layer. The resulting process also allows for control of reverse hot leakage current.

Abstract: Metallic osmium on SiC (either .beta. or .alpha.) forms a contact that remains firmly attached to the SiC surface and forms an effective barrier against diffusion from the conductive metal. On n-type SiC, Os forms an abrupt Schottky rectifying junction having essentially unchanged operating characteristics to at least 1050.degree. C. and Schottky diodes that remain operable to 1175.degree. C. and a barrier height over 1.5 ev. On p-type SiC, Os forms an ohmic contact with specific contact resistance of <10.sup.-4 ohm-cm.sup.2. Ohmic and rectifying contacts to a TiC layer on a SiC substrate are formed by depositing a WC layer over the TiC layer, followed by a metallic W layer. Such contacts are stable to at least 1150.degree. C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy.

Abstract: A method for forming a Schottky diode structure is disclosed. The method includes the steps of: a) Providing a substrate; b) forming a rare-earth containing layer over the substrate; and c) forming a metal layer over the rare-earth containing layer. The Schottky diode structure with a rare-earth containing layer has the properties of high-temperature stability, high Schottky barrier height (SBH), and low reverse leakage current.

Abstract: A II-VI group compound semiconductor device includes a semiconductor substrate, a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer formed on the semiconductor substrate, and an electrode layer formed on the semiconductor layer, the electrode layer containing an additive element of Cd or Te and a metal which can form a eutectic alloy with the additive element, thus achieving an electrode layer having a small contact resistance, especially an electrode layer with an ohmic contact.