Abstract: A processing apparatus includes a wafer cassette table, a wafer carrying-out mechanism, a wafer table, a frame housing unit, a frame carrying-out mechanism, a frame table, a tape sticking unit, a tape-attached frame conveying mechanism, a tape pressure bonding unit, a frame unit carrying-out mechanism, a reinforcing part removing unit, a ring-free unit carrying-out mechanism, and a frame cassette table. The wafer carrying-out mechanism includes a Bernoulli chuck mechanism that jets gas to the back surface of the wafer and generates a negative pressure. The gas jetted by the Bernoulli chuck mechanism is inert gas. The wafer carrying-out mechanism jets the inert gas from the Bernoulli chuck mechanism to suppress oxidation of the back surface of the wafer when the wafer is carried out.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

Abstract: A method of processing a wafer includes a protective member affixing step of affixing a protective member whose area covers a face side or a reverse side of the wafer to the wafer, and after the protective member affixing step has been carried out, a ring-shaped stiffener removing step of removing a ring-shaped stiffener from the wafer. The ring-shaped stiffener removing step includes a ring-shaped stiffener separating step of dividing the wafer along an outer circumference of a device region to separate the device region and the ring-shaped stiffener from each other, and after the ring-shaped stiffener separating step has been carried out, a removing step of processing the ring-shaped stiffener with a grindstone to remove the ring-shaped stiffener from the wafer while a processing fluid is being supplied to the wafer.

Abstract: Systems, methods, and devices are provided herein for burners. In one aspect, a burner is provided comprising at least one air pipe; at least one fuel pipe; a plurality of groups of mixing units disposed at a downstream end of the burner, wherein each of the plurality of groups of mixing units is arranged coaxially and adjacent to one another, and each group of mixing units comprises at least one fuel channel connected to the at least one fuel pipe and at least one air channel connected to the at least one air pipe, wherein an outlet of the at least one fuel channel and an outlet of the at least one air channel are angled at a certain degree relative to one another such that the fuel flowing out of the outlet of the at least one fuel channel is mixed with the air flowing out of the outlet of the at least one air channel, thereby achieving multiple-stage mixing of the air and fuel.

Abstract: One example provides a microelectromechanical systems (MEMS) device that includes a number of silicon die over-molded with an overmold material, a number of active areas formed on the silicon die, the active areas including at least one sensor to sense a number of attributes of a fluid introduced to the at least one sensor, and a fan-out layer coupled to the silicon die, the fan-out layer including a number of fluid channels formed therein that interface with active areas of the silicon die and allow the fluid to flow to the at least one sensor.

Abstract: A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of side-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: The present disclosure includes bonded wafer structures and methods of forming bonded wafer structures. One example of a forming a bonded wafer structure includes providing a first wafer (202, 302) and a second wafer (204, 304) to be bonded together via a bonding process that has a predetermined wafer gap (216, 316) associated therewith, and forming a mesa (215, 315, 415) on the first wafer (202, 302) prior to bonding the first wafer (202, 302) and the second wafer (204, 304) together, wherein a height (220, 320, 420) of the mesa (215, 315, 415) is determined based on a target element gap (217, 317) associated with the bonded wafer structure.

Abstract: The present disclosure provides a substrate processing apparatus including: a substrate processing chamber configured to process a substrate on which a target layer to be removed is formed on the surface of an underlying layer; a substrate holding unit provided in the substrate processing chamber and configured to hold the substrate; a mixed liquid supplying unit configured to supply a mixed liquid of sulfuric acid and hydrogen peroxide to the substrate held by the substrate holding unit in a mixing ratio of the hydrogen peroxide and a temperature that does not damage the underlying layer while removing the target layer; and an OH-group supplying unit configured to supply a fluid containing OH-group to the substrate in an amount that does not damage the underlying layer when the mixed liquid and the OH-group are mixed on the substrate.

Abstract: Trenches may be formed in layers on a semiconductor substrate for defining electrical components for an electronic device, such as an amplifier. A polishing step may be performed after formation of the trenches and deposition of other layer(s) to define regions for resistors, capacitors, or other elements in a metal layer on a semiconductor substrate. The polishing step may create discontinuities in metal layers on the semiconductor substrate that define electrically isolated regions corresponding to the resistors, capacitor, and other components of the electronic device.

Abstract: Provided are a porous nanostructure and a method of manufacturing the same. The porous nanostructure includes a plurality of pores disposed on an exterior surface of a nanostructure, wherein at least a portion of the plurality of pores extend inside the nanostructure.

Abstract: Systems and methods for transferring a micro device from a carrier substrate are disclosed. In an embodiment, a mass transfer tool includes an articulating transfer head assembly, a carrier substrate holder, and an actuator assembly to adjust a spatial relationship between the articulating transfer head assembly and the carrier substrate holder. The articulating transfer head assembly may include an electrostatic voltage source connection and a substrate supporting an array of electrostatic transfer heads.

Abstract: A trimming circuit is configured to carry out a trimming operation on a device portion of an integrated circuit device. The trimming circuit includes: shunt fuses wherein each shunt fuse is coupled in parallel to a trimming resistance, further resistances wherein each further resistance is coupled in parallel to a respective shunt fuse. The circuit is configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation.

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware design rule check for an electronic design. Various embodiments identify one or more sets of multiple-exposure grids and identify or generate a data structure by using the one or more sets of grids to store design data of shape ends of various ends. Various embodiments perform constant time design rule checking by performing a constant time search process on the data structure to look up from the data structure one or more violations of one or more design rules which include at least one directional design rule. Some aspects are directed at fixing a design rule violation by using at least some grids of the one or more sets of grids.

Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

Abstract: A showerhead electrode assembly for use in a capacitively coupled plasma processing apparatus comprising a heat transfer plate. The heat transfer plate having independently controllable gas volumes which may be pressurized to locally control thermal conductance between a heater member and a cooling member such that uniform temperatures may be established on a plasma exposed surface of the showerhead electrode assembly.

Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: An rf MEMS system has a semiconductor substrate, e.g., silicon. The system also has a control module provided overlying one or more first regions of the semiconductor substrate according to a specific embodiment. The system also has a base band module provided overlying one or more second regions of the semiconductor substrate and an rf module provided overlying one or more third regions of the semiconductor substrate. The system also has one or more MEMS devices integrally coupled to at least the rf module.

Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: A resin sealing method for a plurality of semiconductor chips. The resin sealing method includes a chip holding sheet attaching step of attaching a chip holding sheet through an adhesive ring to a support substrate, a semiconductor chip attaching step of attaching the front side of each semiconductor chip to an adhesive layer constituting the chip holding sheet in an area corresponding to the inside of the adhesive ring, a resin sealing step of sealing all of the semiconductor chips with a mold resin, a support substrate removing step of removing the support substrate from the chip holding sheet on which the semiconductor chips are attached and sealed with the mold resin, and a chip holding sheet peeling step of peeling the chip holding sheet from the front side of each semiconductor chip sealed with the mold resin.

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.

Abstract: Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: A method of producing an electronic module with at least one electronic component and one carrier. A structure is provided on the carrier so that the electronic component can take a desired target position relative to the structure. The structure is coated with a liquid meniscus suitable for receiving the electronic component. Multiple electronic components are provided at a delivery point for the electronic components. The carrier, with the structure, is moved nearby and opposite to the delivery point, where the delivery point delivers one of the electronic components without contact, while the structure on the carrier is moving near the delivery point, so that after a phase of free movement the electronic component at least partly touches the material, and the carrier, with the structure, is moved to a downstream processing point, while the electronic component aligns itself to the structure on the liquid meniscus.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: A solar cell module manufacturing device is disclosed. The device includes a wire supply portion, a correction portion, and a cutting portion. The supply portion includes a bobbin and wiring material on the bobbin. The correction portion corrects curvature of the wiring material. The correction portion comprises a first pulley that comes in contact with the wiring material which is drawn from the bobbin. The first pulley comprises at a periphery thereof a first groove. The first groove comprises a first basal surface and a pair of first inclined surfaces which are arranged on both sides of the first basal surface. An inclination angle ?1 of the first inclined surface relative to the first basal surface being less than or equal to an inclination angle ?2 of the wiring material which is drawn from the supply portion relative to the first basal surface.

Abstract: A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.

Abstract: A method of fabricating a spin-current switched magnetic memory element includes providing a wafer having a bottom electrode, forming a plurality of layers, such that interfaces between the plurality of layers are formed in situ, in which the plurality of layers includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers, lithographically defining a pillar structure from the plurality of layers, and forming a top electrode on the pillar structure.

Abstract: There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.

Abstract: A compact sensor with which particles floating in the air can be easily detected. A sensor having a microstructure which detects a detection object by contact is used. A microstructure has an opening to be a detection hole corresponding to the size of a detection object, and a pair of electrodes having a bridge structure are provided thereabove or thereunder so as to partially contact with each other.

Abstract: A multi-chip light emitting device (LED) uses a low-cost carrier structure that facilitates the use of substrates that are optimized to support the devices that require a substrate. Depending upon the type of LED elements used, some of the LED elements may be mounted on the carrier structure, rather than on the more expensive ceramic substrate. In like manner, other devices, such as sensors and control elements, may be mounted on the carrier structure as well. Because the carrier and substrate structures are formed independent of the encapsulation and other after-formation processes, these structures can be tested prior to encapsulation, thereby avoiding the cost of these processes being applied to inoperative structures.

Abstract: A solar cell module manufacturing device is disclosed. The device includes a wire supply portion, a correction portion, and a cutting portion. The supply portion includes a bobbin and wiring material on the bobbin. The correction portion corrects curvature of the wiring material. The correction portion comprises a first pulley that comes in contact with the wiring material which is drawn from the bobbin. The first pulley comprises at a periphery thereof a first groove. The first groove comprises a first basal surface and a pair of first inclined surfaces which are arranged on both sides of the first basal surface. An inclination angle ?1 of the first inclined surface relative to the first basal surface being less than or equal to an inclination angle ?2 of the wiring material which is drawn from the supply portion relative to the first basal surface.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.

Abstract: A method and system for assembling a quasicrystalline heterostructure. A plurality of particles is provided with desirable predetermined character. The particles are suspended in a medium, and holographic optical traps are used to position the particles in a way to achieve an arrangement which provides a desired property.

Abstract: A method and system for estimating context offsets for run-to-run control in a semiconductor fabrication facility is described. In one embodiment, contexts associated with a process are identified. The process has one or more threads, and each thread involves one or more contexts. A set of input-output equations describing the process is defined. Each input-output equation corresponds to a thread and includes a thread offset expressed as a summation of individual context offsets. A state-space model is created that describes an evolution of the process using the set of input-output equations. The state-space model allows to estimate individual context offsets.

Abstract: A method is disclosed for the fabrication of a tunable radio frequency (RF) power output filter that includes fabricating a core body and then forming a plastically deformable metallic shell over the exterior surface of the core body.

Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.

Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.

Abstract: An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.

Abstract: A photovoltaic structure is provided. The photovoltaic structure has photovoltaic elements that can be electrically connected to one another to reduce mismatch. The photovoltaic elements can be electrically connected based on sorting the photovoltaic elements by irradiance level, minimizing mismatch, or maximizing output power. Where sorting is used, the photovoltaic elements can be connected in a serpentine arrangement.