Abstract: A method for aligning a substrate to a process center of a support mechanism is provided. The method includes determining substrate thickness after substrate processing at a plurality of orientations and at a plurality of radial distances from a geometric center of the substrate. The method also includes deriving a set of process rate values from substrate thickness and process duration. The method further includes creating for a process rate an off-centered plot, which represents a substantially concentric circle whose points are a circumference of the off-centered plot having substantially the first process rate. The method yet also includes applying a curve-fitting equation to the off-centered plot to determine a set of parameters. The method yet further includes teaching a set of robot arms the set of parameters, thereby enabling the set of robot arms to align another substrate that is supported by the support mechanism with the process center.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: A solid-state imaging device according to one embodiment includes a plurality of signal output units. Each of the plurality of signal output units includes a first input terminal electrode group that includes a plurality of terminal electrodes for inputting a reset signal, a hold signal, a horizontal start signal, and a horizontal clock signal and a first output terminal electrode that provides output signals. The solid-state imaging device further includes a second input terminal electrode group that includes a plurality of terminal electrodes for receiving the reset signal, the hold signal, the horizontal start signal, and the horizontal clock signal, a plurality of switches that switch an electrode group which is connected with integrating circuits, holding circuits, and a horizontal shift register between the first input terminal electrode group and the second input terminal electrode group, and a second output terminal electrode.

Abstract: A photoelectric conversion module and a method of manufacturing the same are disclosed. The photoelectric conversion module may include a light-receiving substrate in which a first functional layer having a photoelectrode is formed, a counter substrate that faces the light-receiving substrate and is electrically coupled to the light-receiving substrate and in which a second functional layer having a counter electrode is formed. The photoelectric conversion module may include a sealant formed between the light-receiving substrate and the counter substrate and positioned so as to divide a plurality of unit photoelectric cells formed between the light-receiving substrate and the counter substrate. The photoelectric conversion module may include a plurality of interconnection units electrically connecting adjacent unit photoelectric cells.

Abstract: An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is adjacent to an inner edge of the second die. Each relocated bond pad is coupled to a corresponding bond pad on the second die through a respective bonding wire. The first die further includes a plurality of original bond pads. The redistribution layer further includes at least one intermediate bond pad electrically interconnected through a respective conductive trace to a corresponding original bond pad. Each intermediate bond pad is electrically connected to a corresponding relocated bond pad through a respective bond wire.

Abstract: A semiconductor fabricating method including: placing the semiconductor wafer having a film thereon inside of a chamber; generating plasma; detecting a quantity of interference lights for each of at least two wavelengths obtained from a surface of the wafer for a predetermined time period during the etching of the wafer; detecting a first time point at which the detected quantity of interference lights for one of the two wavelengths becomes a maximum and a second time point at which the detected quantity of interference lights for the other wavelength becomes a minimum; determining a state of etching based on a result of comparing a predetermined value with an interval between the first and second time points, wherein both time points are detected by using outputs of a detector for detecting a quantity of the interference lights; and controlling etching in accordance with the determining.

Abstract: Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance.

Abstract: Size reduction and high integration of each of the laminated substrates are achieved, while forming an excellent wiring which electrically connects the substrates to each other. A conductive ink, i.e., an ink, containing a conductive material is used, and in a state where a voltage is applied between a print head and a substrate unit, an ink droplet of the conductive ink is discharged from the print head, while relatively shifting the substrate unit and the print head substantially parallel to at least the upper surface of the substrate. Thus, a conductive layer which electrically connects electrodes to each other between the substrates is formed.

Abstract: A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network.

Abstract: A semiconductor oxidation apparatus is provided with a sealable oxidation chamber defined by walls, a base provided within the oxidation chamber and configured to support a semiconductor sample, a supply part configured to supply water vapor into the oxidation chamber to oxidize a specific portion of the semiconductor sample, a monitoring window provided in one of the walls of the oxidation chamber and disposed at a position capable of confronting the semiconductor sample supported on the base, a monitoring part provided outside the oxidation chamber and capable of confronting the semiconductor sample supported on the base via the monitoring window, and an adjusting part configured to adjust a distance between the base and the monitoring part.

Abstract: A method and system for assembling a quasicrystalline heterostructure. A plurality of particles is provided with desirable predetermined character. The particles are suspended in a medium, and holographic optical traps are used to position the particles in a way to achieve an arrangement which provides a desired property.

Abstract: A micro fluidic device comprises a laminate structure, comprising a plurality of individual layers. At least one layer comprises a micro fluidic channel structure and at least on one side of said layer a further layer is arranged comprising a three-dimensional (3D) micro structure such that the 3D micro structure is influencing a flow characteristic of a fluid within the micro fluidic channel structure.

Abstract: A solid-state imaging device includes the following elements. A photoelectric conversion section is arranged in a semiconductor layer having a first surface through which light enters the photoelectric conversion section. A signal circuit section is arranged in a second surface of the semiconductor layer opposite to the first surface. The signal circuit section processes signal charge obtained by photoelectric conversion by the photoelectric conversion section. A reflective layer is arranged on the second surface of the semiconductor layer opposite to the first surface. The reflective layer reflects light transmitted through the photoelectric conversion section back thereto. The reflective layer is composed of a single tungsten layer or a laminate containing a tungsten layer.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the inductor of the semiconductor device; disposing the inductor and the external inductor so as to face each other via the ferromagnetic film therebetween; and in a state in which the inductor and the external inductor face each other, transmitting and receiving the signals between the inductor and the external inductor by electromagnetic induction.

Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.

Abstract: Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDSon) and the thermal performance of the semiconductor package. Such a configuration also lowers costs relative to similar semiconductor packages that use wirebonded connections. Other embodiments are described.

Abstract: A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.

Abstract: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus.

Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance.

Abstract: A method of producing standoffs in an injection molded solder (IMS) mold, which possesses cavities, each of which is filled with a solder paste using standard techniques, such as screening or IMS. This solder paste is heated to a reflow temperature at which the solder melts and forms a ball or sphere. Since solder pastes are known to reduce in volume due to the therein contained organic material burning off, the remaining solder ball will be significantly lower in volume than that of the cavity. A solder material having a lower melting point is then filled into the cavities about the solder balls. The mold and solder metal are then allowed to cool, resulting in the formation of a solid sphere of metal in the cavity surrounded by solder material of a lower melting point, which, upon transfer to a wafer, form the standoffs.

Abstract: A semiconductor device has a plurality of interconnect layers each including a plurality of interconnect lines. The semiconductor device includes a dielectric film (HDP film) formed by means of high density plasma-enhanced CVD and including an edge formed on the side surface of the topmost-layer interconnect lines, a silicon oxide film formed by modifying a SOG film on the HDP film between adjacent two of the topmost-layer interconnect lines in the element forming region, and a passivation film formed to cover the HDP film and the topmost-layer interconnect lines.

Abstract: A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.

Abstract: A semiconductor device, wherein: a first fabricating option provides a plurality of user configurations to configure the device functionality; and a second fabricating option hard-wires a said functional configuration, the second option comprising a plurality of common masks and fewer processing steps compared to the first option.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including two or more semiconductor dies which are electrically connected to an underlying substrate through the use of conductive wires, some of which may be fully or partially encapsulated by an adhesive or insulating layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate are first and second semiconductor dies. The first semiconductor die and a portion of the substrate are covered by an adhesive layer. The second semiconductor die, the adhesive layer and a portion of the substrate are in turn covered by a package body of the semiconductor package.

Abstract: Some problems related to processing workpieces are presented along with solutions to one or more of the problems. One embodiment of the invention comprises a sensor apparatus for collecting data representing one or more process conditions used for processing a workpiece. Another embodiment of the present invention is a combination comprising a sensor apparatus and a process tool for applications such as chemical mechanical planarization of workpieces and chemical mechanical polishing of workpieces.

Abstract: A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate.

Abstract: A processing method for a wafer includes: preparing a wafer which has a device region having plural devices formed on a surface of the wafer; and a peripheral reinforcing portion which is integrally formed around the device region and has a projection projecting outwardly on a rear surface of the wafer. The processing method further includes: holding the wafer on a holding surface of a rotatable holding table such that the rear surface of the wafer is exposed and the surface of the wafer closely contacts the holding table. The processing method further includes: thinning the peripheral reinforcing portion by cutting and removing at least the projection of the peripheral reinforcing portion of the wafer by using a cutting tool having a rotational shaft parallel to the holding surface, while rotating the wafer by rotating the holding table after the holding of the wafer. The peripheral reinforcing portion is thinned so as to have a thickness equal to or thinner than that of the device region by the thinning.

Abstract: A method of fabricating a component-embedded board including detecting, before the board is covered with an insulating layer, the actual position of an electronic component formed on the surface of the board, calculating a displacement between the design position of the electronic component and the actual position of the electronic component on the surface of the board, and for holding the displacement as displacement data, and correcting, based on the displacement data, design data to be used for processing the board after the board is covered with the insulating layer.

Abstract: A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing or active elements, or may selectively cover only certain of the device's elements. Further, coupling the metal or mechanical-quality, doped polysilicon to the same voltage source as the device's substrate contact may place the conductive layer at the voltage of the substrate, which may function as a Faraday shield, attracting undesired, migrating ions from interfering with the output of the device.

Abstract: Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be separated. The operation of a control unit and a driving unit may position a laser unit such that a laser beam may be irradiated at the damaged and/or defective metal bump. An X-ray inspection unit may obtain information about the damaged and/or defective metal bump.

Abstract: A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product pattern; boring sampling contact holes in the interconnect-changing insulator so as to make bare a part of the intermediate product pattern to define sampling sites; delineating evaluation interconnects on the interconnect-changing insulator so that each of the evaluation interconnects can electrically connected to at least one of the sampling sites of intermediate product pattern; and measuring an electrical resistance between subject sampling sites through the evaluation interconnects so as to detect a product defect in the intermediate product pattern.

Abstract: Projecting elongate stub walls are provided on the planar surfaces of a substrate at positions where bonding of the substrate to a clamping lid or base is to be carried out. On firing of the substrate, the surfaces thereof are mechanically processed but since the stub walls protrude from the substrate, the grinding and polishing tools make contact with the surfaces of these stub walls, rather than with the entire substrate surface. As a result, the area of the substrate to be processed is minimised and problems with dishing and erosion are alleviated. This allows the clamping lid, or frame to be bonded, using conventional conductive adhesive processes, avoiding the cracking and stress problems associated with non-uniformity of the surface of the ceramic substrates.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits (52, 52?) combined with associated drive or sense transistors (53, 141) to form an integrated MRAM array. The MRAM array has lower electrodes (602, 150, 160, 162) of the MRAM bits (52, 52?) formed substantially directly on a source or drain region (56, 142, 152-2) of associated drive or sense transistors (53, 141), so that the intervening vias (302, 34, 36) and underlying interconnects layers (332, 35) of the prior art (20) can be eliminated. An interconnect layer (65) is provided above the MRAM bit (52, 52?) and transistor (53, 141) combination (50, 125, 129, 133) for coupling upper electrodes (41, 164) of the MRAM bits (52, 52?) and other electrodes (601, 58, 152-1, 152-3, 186-1, 186-3) of the transistors (53, 141) to other elements of the array.

Abstract: In one aspect, a method for configuring a ball grid array is disclosed. The method may include identifying a number of balls for use in a ball grid array, determining a number of rows and a number of columns for the ball grid array, and populating the ball grid array at least in part with a plurality of ball-space groupings. The method may also include allocating an unpopulated portion of an area bounded by the at least one first outside row, the at least one second outside row, the at least one first outside column, and the at least one second outside column, to be free of balls. The method may also include routing a signal line from a ball of at least one ball-space grouping to a space of the at least one ball-space grouping and routing the signal line to a substrate layer through a via.

Abstract: A multi-chip module (MCM) includes a first die and a second die. The first die supports a plurality of predetermined functions. The second die is coupled to the first die and comprises at least an option pad configured for a bonding option. The first die performs a predetermined function according to a bonding status of the option pad of the second die.

Abstract: A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of line processing of the memory device.

Abstract: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.

Abstract: The invention provides isolated NUE (nitrogen utilization efficiency) nucleic acids and their encoded proteins. The present invention provides methods and compositions relating to altering nitrogen utilization and/or uptake in plants. The invention further provides recombinant expression cassettes, host cells, and transgenic plants.

Abstract: An integrated circuit device and method. A substrate having contacts has a plurality of capacitors thereon. A plurality of fusible links selectively connect the plurality of capacitors to one another and selected ones of the capacitors to the contacts. In this manner, for example, the capacitance value can be adjusted to tune an antenna mounted on the substrate during testing of the integrated circuit device.

Abstract: A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate.

Abstract: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

Abstract: A method is provided for manufacturing a semiconductor device that includes a multilayer wiring structure in which insulating layers and wiring layers each with a plurality of conductor lines are alternately stacked on each other. The method includes steps of forming a first wiring layer on a first insulating layer, detecting a defect in the first wiring layer on the first insulating layer, and determining whether or not the defect is to be irradiated with a focused ion beam, according to a detection result. If it is determined that the defect is to be irradiated, the defect is irradiated with a focused ion beam and then a second insulating layer is formed on the first wiring layer disposed on the first insulating layer. If it is determined that the defect is not to be irradiated with a focused ion beam, the second insulating layer is formed on the first wiring layer disposed on the first insulating layer without irradiating the defect.

Abstract: A system and process for manufacturing custom printed circuit boards on pre-provided substrates, wherein the substrate is pre-provided with standard integrated circuits. The standard integrated circuits are pre-provided on the substrate in a conventional manner, such as by standard integrated circuit technologies, in many different packing technologies. The user designs the custom printed circuit board using a design tool to perform one or more specific electronic functions, based on the pre-provided electronic devices, and/or custom designed and direct printed electronic devices. The electronic devices includes transistors, resistors, capacitors, among other types of devices. The system and process allows users to customize standard “generic” circuit boards with some known electronic functions for their own particular application. Examples of such uses include displays, the automotive industry and many others.

Abstract: A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

Abstract: A power circuit package includes a base including a substrate, a plurality of interconnect circuit layers over the substrate with each including a substrate insulating layer patterned with substrate electrical interconnects, and via connections extending from a top surface of the substrate to at least one of the substrate electrical interconnects; and a power semiconductor module including power semiconductor devices each including device pads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure including a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections.