Abstract: In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.

Abstract: Some embodiments of the invention are directed to techniques for electrochemically fabricating multi-layer three-dimensional structures where selective patterning of at least one or more layers occurs via a mask which is formed using data representing cross-sections of the three-dimensional structure which has been modified to place it in a polygonal form which defines only regions of positive area. The regions of positive area are regions where structural material is to be located or regions where structural material is not to be located depending on whether the mask will be used, for example, in selectively depositing a structural material or a sacrificial material. The modified data may take the form of adjacent or slightly overlapped relative narrow rectangular structures where the width of the structures is related to a desired formation resolution. The spacing between centers of adjacent rectangles may be uniform or may be a variable.

Abstract: A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly.

Abstract: Methods of selectively and epitaxially forming a silicon-containing material on a substrate surface contained within a process chamber are provided. In one or more embodiments, the pressure in the process chamber is reduced during deposition of material on the substrate and increased during etching of material from the substrate. According to an embodiment, process gases are flowed into the chamber through first zone and a second zone to provide a ratio of the amount of gas flowed to the first zone and the amount of gas flowed to the second zone. In one or more embodiments, the first zone is an inner radial zone and the second zone is an outer radial zone, and ratio of inner zone gas flow to outer zone gas flow is less during deposition than during etching. According to one or more embodiments, the selective epitaxial process includes repeating a cycle of a deposition and then an etching process, and an optional purge until the desired thickness of an epitaxial layer is grown.

Abstract: A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed.

Abstract: This invention provides a semiconductor film manufacturing method using a new separation technique and applications thereof. The semiconductor film manufacturing method of this invention includes a separation layer forming a step of hetero-epitaxially growing a separation layer (2) on a seed substrate (1), a semiconductor film forming step of forming a semiconductor film (3) on the separation layer (2), and a separation step of separating, by using the separation layer (2), the semiconductor film (3) from a composite member (Ia) formed in the semiconductor film forming step.

Abstract: There is provided a monocrystalline gallium nitride localized substrate suitable for manufacturing electronic-optical united devices in which electronic devices and optical devices are mixedly mounted on the same silicon substrate. An area in which monocrystalline gallium nitride 410 is grown is locally present on a silicon substrate 100 by forming silicon carbide 200 on the silicon substrate 100 to locally form the monocrystalline gallium nitride 410 on the above-mentioned silicon carbide 200. Silicon nitride 220 is used as a mask in forming the above-mentioned monocrystalline gallium nitride 410.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a primary storage node contact plug at an upper part of the exposed landing plug at a lower part of the storage node contact hole; and filling the storage node contact hole with a conductive film to form a secondary storage node contact plug. In result, the size of a storage node contact may be increase to cause the contact resistance to decrease, without any loss of the interlayer insulating film to a cleaning solution.

Abstract: The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

Abstract: An image sensor and a method for fabricating the same are disclosed, to improve a contact quality between a contact plug and a source diffusion layer.

Abstract: A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first contact and defining an interface between the pinning layer and the source region, wherein the pinning layer has donor-type surface states in a conduction band. A method including forming a transistor structure including a gate electrode on a substrate and source and drain regions formed in the substrate; depositing a pinning layer having donor-type surface states on the source and drain regions such that an interface is defined between the pinning layer and the respective one of the source and drain regions; and forming a first contact to the source region and a second contact to the drain region.

Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A silicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces.

Abstract: A thin film capacitor is provided which includes a single crystal high dielectric constant dielectric layer. The thin film capacitor has a single crystal silicon substrate, a single crystal intermediate layer epitaxially grown on the single crystal silicon substrate, a single crystal lower electrode epitaxially grown on the single crystal intermediate layer, a single crystal high dielectric constant dielectric layer epitaxially grown on the lower electrode layer, an upper electrode layer formed above the single crystal high dielectric constant dielectric layer, and a plurality of conductor terminals connected to the lower electrode layer and upper electrode layer at a plurality of positions.

Abstract: A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask layer having a sacrificial support structure. The SiN mask is removed and then a breakthrough etch is applied to remove an underlying pad oxide layer. A PSG layer defining a width of each of the fins on a sidewall of each of the support structures is deposited on each of the support structures. At least two fins each having a narrow fin pitch of about 0.25 ?m. are formed. The fins provide a seed layer for at least two selective epitaxially raised source and drain regions, wherein each raised source-drain associated with each fin are interconnected thus forming a source pad and a drain pad.

Abstract: A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.

Abstract: The invention provides a substrate for an electronic device including a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation and which contains a metal oxide having a perovskite structure, a method for manufacturing a substrate for an electronic device, and an electronic device provided with such a substrate for an electronic device. A substrate for an electronic device includes a Si substrate, a buffer layer which is formed by epitaxial growth on the Si substrate and which contains a metal oxide having a NaCl structure, and a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation on the buffer layer and which contains a metal oxide having a perovskite structure. The Si substrate is preferably a (100) substrate or a (110) substrate from which a natural oxidation film is not removed.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; forming a capacitor insulation layer on the etch stop layer; forming an opening exposing the conductive region by selectively etching the capacitor insulation layer and the etch stop layer; growing a selective epitaxial growth (SEG) layer in the conductive region exposed through the opening; forming a metal layer for a capacitor bottom electrode along a profile provided with the opening; forming an isolated capacitor bottom electrode by removing the metal layer until the capacitor insulation layer is exposed; and removing the capacitor insulation layer, thereby making the capacitor bottom electrode have a cylinder type structure.

Abstract: An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: The invention generally teaches a method for depositing a silicon film or silicon germanium film on a substrate comprising placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600° C. to about 900° C. while maintaining a pressure in the range from about 0.1 Torr to about 200 Torr. A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment teaches a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods may include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Abstract: The present invention relates to a method of manufacturing a semiconductor wafer that includes providing a substrate of a single crystalline first material that has an unfinished or rough surface, and epitaxially growing at least one layer of a second material directly on the unfinished or rough surface of the first material. The second material has a lattice that is different from that of the first material and the epitaxial growing of the second material is advantageously performed before a final surface finishing step on the unfinished or rough surface of the substrate to increase bonding between the materials.

Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

Abstract: In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germanium source, a first etchant and a carrier gas and depositing a second silicon-containing layer by exposing the first silicon-containing layer to a second process gas comprising SiH4 and a second etchant. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing a first silicon-containing layer on the substrate surface with a first germanium concentration of about 15 at % or more.

Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Abstract: A method and system to reduce the resistance of refractory metal layers by controlling the presence of fluorine contained therein. The present invention is based upon the discovery that when employing ALD techniques to form refractory metal layers on a substrate, the carrier gas employed impacts the presence of fluorine in the resulting layer. As a result, the method features chemisorbing, onto the substrate, alternating monolayers of a first compound and a second compound, with the second compound having fluorine atoms associated therewith, with each of the first and second compounds being introduced into the processing chamber along with a carrier gas to control a quantity of the fluorine atoms associated with the monolayer of the second compound.

Abstract: The invention provides a method of producing a structure of a thin layer of semiconductor material on a support substrate. The thin layer is obtained from a donor substrate and includes an upper layer of semiconductor material. The method includes forming on the upper layer a bonding layer of a material that accepts diffusion from an element of the material of the upper layer, bonding the donor substrate from the side on which the bonding layer is formed on the upper layer to the support substrate, and diffusing the element from the upper layer into the bonding layer to homogenize the concentration of the element in the bonding layer and the upper layer. The result is that the thin layer of the structure is joined by the bonding layer to the upper layer.

Abstract: Nanochannel electrophoretic and electrochemical devices having selectively-etched nanolaminates located in the fluid transport channel. The normally flat surfaces of the nanolaminate having exposed conductive (metal) stripes are selectively-etched to form trenches and baffles. The modifications of the prior utilized flat exposed surfaces increase the amount of exposed metal to facilitate electrochemical redox reaction or control the exposure of the metal surfaces to analytes of large size. These etched areas variously increase the sensitivity of electrochemical detection devices to low concentrations of analyte, improve the plug flow characteristic of the channel, and allow additional discrimination of the colloidal particles during cyclic voltammetry.

Abstract: A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure is treated. The treat step is that the removal rate of the insulation surface is faster than the removal rate of the epitaxial layer. Then, a metal layer on the epitaxial layer is formed. Finally, heating the epitaxial layer forms silicide. The treatment step prevents the insulation surface from the formation of the silicide so as to reduce the degradation of device characteristics.

Abstract: Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.

Abstract: In a method of fabricating local interconnection, a selective epitaxial growth seed layer pattern is formed on a region of a semiconductor substrate where a local interconnection is to be formed. A selective epitaxial layer is formed by performing epitaxial growth on the resultant structure. The resistance of the selective epitaxial layer is reduced to complete the local interconnection.

Abstract: A method and system to reduce the resistance of refractory metal layers by controlling the presence of fluorine contained therein. The present invention is based upon the discovery that when employing ALD techniques to form refractory metal layers on a substrate, the carrier gas employed impacts the presence of fluorine in the resulting layer. As a result, the method features chemisorbing, onto the substrate, alternating monolayers of a first compound and a second compound, with the second compound having fluorine atoms associated therewith, with each of the first and second compounds being introduced into the processing chamber along with a carrier gas to control a quantity of the fluorine atoms associated with the monolayer of the second compound.

Abstract: A multi-point calibration standards and a method of fabricating calibration standards which are used to quantify the dose or concentration of a dopant or impurity in a silicon matrix. The calibration standards include a set of calibration standard wafers for each dopant or impurity to be quantified. On each calibration standard wafer in the set is provided a silicon matrix incorporated with one of various concentrations, by weight, of the dopant or impurity in the silicon. The atomic concentration of the dopant or impurity in the silicon on each wafer in the set is measured. A calibration curve is then prepared in which the silicon/dopant or silicon/impurity ratio on each calibration standard wafer in the set is plotted versus the atomic concentration of the dopant or impurity in the silicon on the wafer.

Abstract: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013?1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface.

Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.

Abstract: A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure.

Abstract: A lithography method for fabricating structures of etch-resistant metal-semiconductor compound on a substrate with sub-micrometer scale resolutions is described. Superposed layers of metal and semiconductor capable of reacting with each other to form etch-resistant metal/semiconductor compound are deposited on the substrate. Radiation from a X-ray/EUV source propagates through a patterned X-ray transparent/EUV reflective mask and is projected on the superposed metal and semiconductor layers. The X-ray transparent mask includes X-ray absorbing patterns imparted to the X-ray radiation while the EUV reflective mask includes EUV absorbing patterns also imparted to the EUV radiation. The energy of X-ray/EUV photons is absorbed locally by the metal and semiconductor layers. Absorption of this energy induces a reaction between the two layers responsible for the formation of etch-resistant metal/semiconductor compound with structures corresponding to the patterns imparted to the radiation by the X-ray/EUV mask.

Abstract: A process for epitaxially coating the front surface of a semiconductor wafer in a CVD reactor, the front surface of the semiconductor wafer being exposed to a process gas which contains a source gas and a carrier gas, and the back surface of the semiconductor wafer being exposed to a displacement gas, wherein the displacement gas contains no more than 5% by volume of hydrogen, with the result that diffusion of dopants out of the back surface of the semiconductor wafer, which is intensified by hydrogen, is substantially avoided. With this process, it is possible to produce a semiconductor wafer with a substrate resistivity of ?100 m?cm and a resistivity of the epitaxial layer of >1 ?cm without back-surface coating, the epitaxial layer of which semiconductor wafer has a resistance inhomogeneity of <10%.

Abstract: There is provided a method of producing multiple semiconductor components on a substrate, said method comprising the steps of: forming a predetermined relief pattern on a surface of said substrate; and epitaxially depositing a layer formed of a mixture of two or more Group III elements and two or more Group V elements on said surface; wherein said relief pattern results in said layer deposited in a single step forming with a different ratio between said Group V elements within areas having different relief pattern characteristics so as to provide different band gaps within said different areas.

Abstract: This invention concerns nanoscale products, such as electronic devices fabricated to nanometer accuracy. It also concerns atomic scale products. These products may have an array of electrically active dopant atoms in a silicon surface, or an encapsulated layer of electrically active donor atoms. In a further aspect the invention concerns a method of fabricating such products. The methods include forming a preselected array of donor atoms incorporated into silicon. Encapsulation by growing silicon over a doped surface, after desorbing the passivating hydrogen. Also, using an STM to view donor atoms on the silicon surface during fabrication of a nanoscale device, and measuring the electrical activity of the donor atoms during fabrication of a nanoscale device. Such products and processes are useful in the fabrication of a quantum computer, but could have many other uses.

Abstract: An efficient method of fabricating a high-quality microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a microstructure fabricated from such method.

Abstract: In a method for forming a contact on semiconductor surface, a crystalline silicon surface is first oxidized, following which an aluminium layer is deposited onto the oxide layer. A layer of amorphous silicon is then deposited onto the aluminium layer. The structure is then heated to a temperature below the aluminium/silicon eutectic temperature to locally reduce the oxide layer in regions where the quality/density of the oxide layer is lower. Simultaneously, the amorphous silicon penetrates into the aluminium layer, in which it has a high mobility. With continued heating, the aluminium penetrates completely through the oxide layer in localized regions, exposing the crystalline silicon surface. The exposed silicon surface provides a sight for nucleating epitaxial growth, which occurs rapidly as silicon within the aluminium continuously feeds the solid phase epitaxial growth process.

Abstract: A method for adjusting with high precision the width of gaps between micromachined structures or devices in an epitaxial reactor environment. Providing a partially formed micromechanical device, comprising a substrate layer, a sacrificial layer including silicon dioxide deposited or grown on the substrate and etched to create desired holes and/or trenches through to the substrate layer, and a function layer deposited on the sacrificial layer and the exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Cleaning residues from the surface of the device, then epitaxially depositing a layer of gap narrowing material selectively on the surfaces of the device. The selection of deposition surfaces determined by choice of materials and the temperature and pressure of the epitaxy carrier gas.

Abstract: According to one example method of fabricating a semiconductor memory device, an isolation layer and a capping layer are formed on a silicon substrate, sequentially. By an epitaxial silicon growth process, an epitaxial active region is formed. A gate insulation layer and a gate electrode are then formed on the epitaxial active region, sequentially. Subsequently, a bit line contact plug and a storage node contact plug are epitaxially formed on the epitaxial active region. A lower interlayer insulation layer is formed on the resultant structure and planarized. An upper interlayer insulation layer is formed on the lower interlayer insulation layer and a bit line is formed therein. An additional upper interlayer insulation layer is then formed on the entire surface of the resultant structure and a storage node electrode is formed through the additional upper and the upper interlayer insulation layer to be connected to the storage node contact.

Abstract: Methods for manufacturing semiconductor devices are disclosed. In a disclosed method, a first nitride layer and a device isolation oxide layer are etched to thereby expose a portion of a silicon substrate where an active region is to be formed. An epitaxial growth is performed on the active region and a first oxide layer is deposited thereon. Portions of the first oxide layer where a source and a drain are to be formed are etched. The first oxide layer deposited on the portions where the source and the drain are to be formed is then etched. An epitaxial growth is performed on the portions where the source and the drain are to be formed to thereby form the source and the drain. A second nitride layer is deposited thereon. A portion of the first oxide layer located where a gate is to be formed is etched using a gate mask. A third nitride layer is deposited on the source, the drain, and the exposed active region and then etched back to thereby form a nitride layer to control a length of the gate.