Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: A second main surface of the copper plate is opposite a first main surface of the copper plate, and is bonded to a silicon nitride ceramic substrate by the bonding layer. A first portion and a second portion of an end surface of the copper plate form an angle of 135° to 165° on an outside of the copper plate. An extended plane of the first portion and the second main surface form an angle of 110° to 145° a side where the second portion is located. A distance from the second main surface to an intersection of the first portion and the second portion in a direction of a thickness of the copper plate is 10 to 100 ?m. The second main surface extends beyond the extended plane of the first portion by a distance of 10 ?m or more.

Abstract: The present disclosure provides a method and system for manufacturing a semiconductor layer. The method includes: placing a first wafer in a cavity to form a metal film on the first wafer; before forming the metal film, the temperature inside the cavity is a first temperature; transferring the first wafer on which the metal film has been formed out of the cavity; the temperature in the cavity is a second temperature, and the second temperature is greater than the first temperature; introducing an inert gas into the cavity to cool the cavity, such that the temperature in the cavity is equal to the first temperature; after the temperature in the cavity is equal to the first temperature, placing a second wafer in the cavity to form the metal film on the second wafer. The manufacturing method can reduce the defects on the surface of the metal film.

Abstract: A microelectronic device has a die with a first electrically conductive pillar, and a second electrically conductive pillar, mechanically coupled to the die. The microelectronic device includes a first electrically conductive extended head electrically coupled to the first pillar, and a second electrically conductive extended head electrically coupled to the second pillar. The first pillar and the second pillar have equal compositions of electrically conductive material, as a result of being formed concurrently. Similarly, the first extended head and the second extended head have equal compositions of electrically conductive material, as a result of being formed concurrently. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor. A second plate may be located in the die, between the first plate and the die, or on an opposite of the first plate from the die.

Abstract: A method of making a semiconductor device includes plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure. The method further includes planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer. The method further includes depositing a second conductive material over the first passivation layer, wherein the second conductive material is different from the first conductive material, and the second conductive material is electrically connected to the first conductive material in the opening. The method further includes patterning the second conductive material to define a redistribution line (RDL).

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the semiconductor substrate, a conductive plug filling a first portion of the via and a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug.

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the semiconductor substrate, a conductive plug filling a first portion of the via and a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug.

Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

Abstract: A photovoltaic device includes an inorganic substrate having a surface; an organic monolayer disposed onto the surface of the inorganic substrate, the inorganic monolayer having the following formula: ˜X—Y, wherein X is an oxygen or a sulfur; Y is an alkyl chain, an alkenyl chain, or an alkynyl chain; and X covalently bonds to the surface of the inorganic substrate by a covalent bond; a doped organic material layer disposed onto the organic monolayer; and a conductive electrode disposed onto a portion of the doped organic material.

Abstract: A photovoltaic device includes an inorganic substrate having a surface; an organic monolayer disposed onto the surface of the inorganic substrate, the inorganic monolayer having the following formula: ˜X—Y, wherein X is an oxygen or a sulfur; Y is an alkyl chain, an alkenyl chain, or an alkynyl chain; and X covalently bonds to the surface of the inorganic substrate by a covalent bond; a doped organic material layer disposed onto the organic monolayer; and a conductive electrode disposed onto a portion of the doped organic material.

Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.

Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

Abstract: The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry comprising O2, SO2 and a hydrogen halide. For example, a dry develop chemistry comprising a gas comprising O2 and a gas comprising SO2 and a gas comprising HBr may be used to remove exposed areas of a carbon-based mask. The addition of HBr to the conventional O2 and SO2 dry develop chemistry enables a user to tune the critical dimension by growing, trimming and/or sloping the sidewalls and to enhance sidewall passivation and reduce sidewall bowing.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a metal contact that includes a heavy alkaline earth metal on an n-type semiconductor layer. The heavy alkaline earth metal may underlie a metal layer and/or a capping layer. Related semiconductor devices are also provided.

Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.

Abstract: A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the barrier such that copper wiring is formed in the recess, etching the wiring such that surface of the wiring is recessed from surface of the insulating layer, and removing the barrier from the surface of the insulating layer such that the surface of the insulating layer is exposed. The etching includes positioning the structure removed down to the barrier in organic compound atmosphere having vacuum state, and irradiating oxygen gas cluster ion beam on the surface of the wiring to anisotropically etch the wiring.

Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

Abstract: A method for manufacturing a chip package is provided. The method includes: forming an electrically insulating material over a chip side; selectively removing at least part of the electrically insulating material thereby forming a trench in the electrically insulating material, depositing electrically conductive material in the trench wherein the electrically conductive material is electrically connected to at least one contact pad formed over the chip side; forming an electrically conductive structure over the electrically insulating material, wherein at least part of the electrically conductive structure is in direct physical and electrical connection with the electrically conductive material; and depositing a joining structure over the electrically conductive structure.

Abstract: A method of making a pillar structure includes forming a first under-bump-metallurgy (UBM) layer formed on a pad region of a substrate, wherein the first UBM layer includes sidewalls. The method further includes forming a second UBM layer on the first UBM layer, wherein the second UBM layer includes a sidewall surface, an area of the first UBM layer is greater than an area of the second UBM layer. The method further includes forming a copper-containing pillar on the second UBM layer, wherein the copper-containing pillar includes a sidewall surface and a top surface. The method further includes forming a protection structure on the sidewall surface of the copper-containing pillar and on an entirety of the sidewall surface of the second UBM layer, wherein the protection structure does not cover the sidewalls of the first UBM layer, and the protection structure is a non-metal material.

Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.

Abstract: A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a first metallization layer comprising a first metal, a second metallization layer comprising a second metal different from the first metal, and a first intermetallic compound (IMC) layer between the first metallization layer and the second metallization layer, the first IMC layer comprising the first metal and the second metal.

Abstract: According to an embodiment, a semiconductor device, includes a substrate, an inter-layer insulating layer provided above the substrate, a first interconnect provided in a first trench, and a second interconnect provided in a second trench. The first interconnect is made of a first metal, and the first trench is provided in the inter-layer insulating layer on a side opposite to the substrate. The second interconnect is made of a second metal, and the second trench is provided in the inter-layer insulating layer toward the substrate. A width of the second trench is wider than a width of the first trench. A mean free path of electrons in the first metal is shorter than a mean free path of electrons in the second metal, and the first metal is a metal, an alloy or a metal compound, including at least one nonmagnetic element as a constituent element.

Abstract: Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.

Abstract: A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.

Abstract: There is provided a semiconductor device manufacturing method for forming a step-shaped structure in a substrate by etching the substrate having thereon a multilayer film and a photoresist film on the multilayer film and serving as an etching mask. The multilayer film is formed by alternately layering a first film having a first permittivity and a second film having a second permittivity different from the first permittivity. The method includes a first process for plasma-etching the first film by using the photoresist film as a mask; a second process for exposing the photoresist film to hydrogen-containing plasma; a third process for trimming the photoresist film; and a fourth process for etching the second film by using the trimmed photoresist film and the plasma-etched first film as a mask. The step-shaped structure is formed in the multilayer film by repeatedly performing the first process to the fourth process in this sequence.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A conductive layer is deposited on the substrate. A patterned hard mask is formed on the conductive layer and then a patterned photoresist is formed on the patterned hard mask and the conductive layer. A local metal catalyst layer is formed on the conductive layer in the openings of the patterned photoresist. Carbon nanotubes (CNTs) are grown from the local metal catalyst layer. The conductive layer is etched by using the CNTs and the patterned hard mask as etching mask to form metal features. An inter-level dielectric (ILD) layer is deposited between metal features.

Abstract: Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.

Abstract: A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.

Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer dielectric film is provided on the lower-layer wiring and includes a four-layer stacked structure. A contact plug contains aluminum. The contact plug is filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring. Two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole. The taper of two upper layers and the taper of two lower layers have different angles from each other.

Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.

Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.

Abstract: An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, in which the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, at least one thermal expansion buffer layer, a backside metal layer, and at least one oxidation resistant layer, in which the backside metal seed layer is formed of Pd, and the thermal expansion coefficient of the thermal expansion buffer layer is in the range between the thermal expansion coefficients of the backside metal seed layer and of the backside metal layer. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.

Abstract: A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap.

Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

Abstract: A film forming method which generates metal ions from a metal target with a plasma in a processing chamber and attracts the metal ions with a bias to deposit a metal thin film on a target object wherein trenches are formed. The method includes: generating metal ions from a target and attracting the metal ions into a target object with a bias to form a base film in a trench; ionizing a rare gas with the bias in a state where no metal ion is generated and attracting the generated ions into the target object to etch the base film; and plasma sputtering the target to generate metal ions and attracting the metal ions into the object with a high frequency power for bias to deposit a main film as a metal film, while reflowing the main film by heating.

Abstract: An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.

Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

Abstract: A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.

Abstract: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.

Abstract: A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer.

Abstract: According to one embodiment, after forming transistors on a semiconductor substrate, a stopper layer and an interlayer insulating film are formed. Then, a contact hole is formed in the interlayer insulating film and a copper film is formed on the interlayer insulating film to bury the inside of the contact hole with copper. After that, the copper film on the interlayer insulating film is removed by low-pressure CMP polishing or ECMP polishing to planarize a surface thereof to form plugs. Thereafter, a barrier metal, a lower electrode, a ferroelectric film, and an upper electrode are formed. In this manner, a semiconductor device (FeRAM) having a ferroelectric capacitor is formed.

Abstract: A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer.

Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.

Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

Abstract: A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.