Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includes a degassing chamber, a film forming chamber, and a cooing chamber. The degassing chamber 34 is provided for carrying out a degassing process by heating the semiconductor substrate to a degassing temperature. The film forming chamber 40 is provided for forming a metal film on the film formation region in a state in which the semiconductor substrate is heated to a film formation temperature. The cooling chamber 38 is provided for cooling, after completion of the degassing process and before beginning of the formation of the metal film, the semiconductor substrate to a cold temperature being lower than the film formation temperature and in a range of −50° C. to 150° C.

Abstract: A method is disclosed for forming a high aspect ratio submicron VLSI interconnect structure. The method makes use of the high diffusivity of aluminum alloyed with germanium and the low eutectic temperature of the alloy for more uniform filling of interconnect structure openings having high aspect ratios. The method comprises preparing a semiconductor device or portion of a semiconductor device that is to receive electrical contact, covering the semiconductor device with an insulating layer, forming an interconnect structure openings through the insulating layer, depositing a layer of germanium in the interconnect structure opening, and reflow sputtering aluminum or aluminum alloy into the interconnect structure opening. Alternatively, the aluminum or aluminum alloy can be cold sputtered into the interconnect structure opening, followed by a low temperature reflow. The aluminum will readily diffuse to the bottom of the interconnect structure opening, assisted by its high diffusivity with the germanium.

Abstract: For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activated surface of the exposed part is formed in the contact hole, a gas containing an impurity component is supplied to form an impurity adsorption film on the activated surface, and the contact hole is filled with a second electrically conductive layer which electrically contacts the first layer through the contact hole.

Abstract: Disclosed is a method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed in a recess such as a trench, a hole, a via, or a combination of a trench and a hole or via within a dielectric material situated on the substrate assembly of the semiconductor wafer. At least one barrier layer is deposited within the recess. A seed layer helping to promote nucleation, deposition, and growth of a material that will be used to fill up the recess is then deposited on the barrier layer. An electrically conductive layer is then formed upon the seed layer. An energy absorbing layer will then be formed upon the conductor layer, where the energy absorbing layer has a greater thermal absorption capacity than that of the electrically conductive layer.

Abstract: A method for forming a semiconductor device having a capacitor, a resistor and a MOS transistor with characteristics conforming to design. To this end, a polysilicon film (4), a capacitor-dielectric/insulating film (5), a polysilicon film (6) are deposited, and an upper electrode (7) of the capacitor is formed from the polysilicon film (6), and edge portions (7a) of the upper electrode (7) are oxidized. On top of this, an inorganic anti-reflection coating film (9) and a CAP oxide film (10) are deposited and etched to form a mask pattern (12) for forming the capacitor and the resistor. On the other hand, a tungsten silicide film (13), an inorganic anti-reflection coating film (14) and a CAP oxide film (15) are deposited and etched to form a mask pattern (17) for forming a gate electrode. The polysilicon film (4) is etched by using the mask patterns (12) and (17), leaving behind the tungsten silicide film (13) beneath the mask pattern 17.

Abstract: In one aspect, the invention includes a semiconductor processing method of removing water from a material comprising silicon, oxygen and hydrogen, the method comprising maintaining the material at a temperature of at least about 100° C., more preferably at least 300° C., and at a pressure of greater than 1 atmosphere to drive water from the material. In another aspect, the invention includes a semiconductor processing method of forming SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute comprising: a) forming a layer comprising Si(OH)x; b) maintaining the Si(OH)x at a temperature of at least about 300° C. and at a pressure of greater than 1 atmosphere to drive water from the Si(OH)x; and c) converting the Si(OH)x to SiO2, the SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute under the conditions of a buffered oxide etch utilizing 20:1 H2O:HF, at about atmospheric pressure and at a temperature of about 30° C.

Abstract: A metallization process of a semiconductor device is disclosed. The metallization process of a semiconductor device comprising the steps of: providing a semiconductor substrate having a junction region; forming an insulating layer on the upper of the semiconductor substrate; forming a contact hole by patterning the insulating layer so as to expose one portion of the junction region; forming a glue layer on the upper of the insulating layer, and at the bottom and inner surfaces of the contact hole; forming a barrier metal layer on the glue layer; forming an Mg layer as a solid solution layer on the barrier metal layer; forming a metal layer on the Mg layer; and forming a metal wiring layer having more liquidity than that of the metal layer, by melting the Mg layer to the metal.

Abstract: A Ni film for a ground metal film is formed on an insulating substrate by direct current magnetron sputtering process, which prevents occurrence of minute protrusions on a surface of the ground metal film. Next, a Ni film is patterned into a specified interconnection form to obtain a patterned Ni film. Then, an anti-corrosive Au film having low resistance is formed on the patterned Ni film by electroless plating process. Further, an inexpensive Cu film having low resistance is formed on the Au film by electroplating process.

Abstract: A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

Abstract: In aspect, the invention includes a semiconductor processing method comprising: a) forming an electrically insulative layer over a substrate; b) forming an opening within the electrically insulative layer, the opening having a periphery defined at least in part by a bottom surface and a sidewall surface; c) forming a first layer comprising TiN within the opening, the first layer being over the bottom surface and along the sidewall surface; d) forming a second layer comprising elemental Ti over the electrically insulative layer but substantially not within the opening, the second layer having a thickness of less than 50 Å along the sidewall surface and over the bottom surface; and e) forming an aluminum-comprising layer within the opening and over the second layer.

Abstract: In a method of manufacturing a semiconductor device wherein the step of forming a titanium film and a titanium nitride film on an aluminum-based alloy film overlying a substrate is carried out for a plurality of such substrates in succession; the titanium film and the titanium nitride film are formed within an identical chamber by changing a processing gas, and under the condition that, in case of forming the titanium film by sputtering, a titanium target having been employed for the formation of the titanium nitride film is used. Thus, the formation of an aluminum-titanium alloy layer attributed to a heat treatment at or above 400° C. can be suppressed to enhance an electromigration immunity.

Abstract: A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.

Abstract: A method for improving the fabrication of a transistor barrier layer that utilizes an ion bombardment treatment after the formation of the titanium nitride layer for reducing contact resistance and preventing tungsten plug stringer generation. The method comprises the step of patterning a transistor to form vias, and then depositing a titanium/titanium nitride layer over the transistor surface using a collimator sputtering method. Next, an ion bombardment treatment is carried out, and then a rapid thermal processing operation is performed. Finally, tungsten is deposited to fill the vias follow by a planarization. This invention is able to lower contact resistance because titanium in the titanium layer will not react with gaseous ammonia or nitrogen in the reacting chamber to form a high resistance titanium nitride layer during rapid thermal processing operation.

Abstract: A first convex portion and a second convex portion are formed on a semiconductor substrate at a prescribed interval, an impurity diffusing region is formed on an upper portion of the semiconductor substrate placed between the first and second convex portions, and a thinned first polysilicon film is formed on the impurity diffusing region and the first and second convex portions. Thereafter, arsenic ions are implanted into the first polysilicon film to make the first polysilicon film conductive. Thereafter, a second polysilicon film having a film thickness larger than that of the first polysilicon film is formed, and phosphorus ions are implanted into the second polysilicon film to make the second polysilicon film conductive. Thereafter, a tungsten silicide film is formed on the second polysilicon film, and the tungsten silicide film and the first and second polysilicon films are patterned.

Abstract: A method of manufacturing a semiconductor device utilizing a multi-chamber apparatus comprises the steps of forming a metal film on an insulating layer under the lower pressure within a film forming apparatus and reflowing the metal film on the insulating film, after transferring the semiconductor substrate to a reflow apparatus from the film forming apparatus under the vacuum atmosphere of 1.3×10−6 Pa or less, by simultaneously heating a plurality of semiconductor substrates under the vacuum atmosphere of 1.3×10−6 Pa or less.

Abstract: A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.

Abstract: A method of fabricating a plug etches back the first plug material layer to form a dished surface on the first plug material layer and then performs a second coverage step. A second plug material layer is formed to fill the dished surface and a hole. Thus, the slurry cannot fill the hole during chemical mechanical polishing nor can slurry react with the plug material or the first metallic layer. The reliability of the plug according to the present invention is increased. The thickness of the second plug material layer is thinner than the plug material layer of the conventional method. The thickness is decreased by about 60% when compared with the conventional method, which decreases fabrication costs.

Abstract: An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug.

Abstract: The present invention provides an effective barrier layer for improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. In one aspect of the invention, a feature is filled by first depositing a barrier layer onto a substrate having high aspect ratio contacts or vias formed thereon. The barrier layer is preferably comprised of Ta, TaNx, W, WNx, or combinations thereof. A CVD conformal metal layer is then deposited over the barrier layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal layer is deposited onto the previously formed CVD conformal metal layer at a temperature below that of the melting point temperature of the metal to allow flow of the CVD conformal layer and the PVD metal layer into the vias.

Abstract: A method for forming Dual Damascene structures wherein a via is etched to an element to be contacted, a non-photoreactive protective layer is deposited in the via, and an intersecting trench is formed. The protective layer is then removed, together with any residual debris resulting from the trench formation. The protective layer enhances reliability of the electrical contact at the bottom of the via.

Abstract: A method for forming self-aligned raised source and drain regions on a semiconductor wafer includes the steps of defining a substrate, growing a first layer of dielectric material over the substrate, depositing a layer of polysilicon over the first layer of dielectric material, patterning and forming at least one gate, depositing a second layer of dielectric material over the gate and the first dielectric layer and masking the second dielectric layer to define a source region and a drain region. The method also includes the steps of anisotropically etching to form sidewall spacers contiguous with the gate, collimated sputtering to deposit a layer of silicon, and implanting ions into the deposited silicon.

Abstract: A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.

Abstract: Upon forming a groove and a connection hole by a dual damascene process, there is a problem in that the connection hole has a bowing shape, and it is difficult to form a shape of the connection hole in a good and stable manner. A process for producing a multi-layer wiring structure is provided, which comprises a step of forming an inter level dielectric film 15 covering a lower layer wiring 14; a step of forming a connection hole 16 in the inter level dielectric film 15 to reach the lower layer wiring 14; a step of forming an inter metal dielectric film 17 filling the connection hole 16 on the inter level dielectric film 15, with an insulating material having an etching rate larger than an etching rate of the inter level dielectric film 15; and a step of forming a concave part 18 in the inter metal dielectric film 17, and selectively re-opening the connection hole 16 with respect to the inter level dielectric film in such a manner that the connection hole is continuous to the concave part 18.

Abstract: Various alignment targets are disclosed having improved visibility. A first embodiment includes an alignment target having a first reflective layer of a first material such as tungsten having a roughened surface; and a second layer of a second material, such as aluminum, deposited on the first layer. The surface of the second layer is roughened by conforming with the roughened surface of the first layer to provide both layers with a uniform optical layers. The edges of the second layer provides an optical signal to contrast between the two layers for alignment. A second embodiment includes an alignment target with a plurality of parallel elongated trenches; a first material fills each of the trenches; and a patterned layer of a second material is deposited on top the elongated trenches and the insulator layer.

Abstract: Interconnects for semiconductor devices are formed by forming a reaction control layer on a lower conductive layer of a semiconductor device, forming a reactive metal layer on the reaction control layer, opposite the lower conductive layer, reacting the lower conductive layer with the reactive metal layer, through the reaction control layer, to form an ohmic contact for the semiconductor device, and forming an upper conductive layer on the ohmic contact, opposite the lower conductive layer. Interconnects so formed may provide reduced contact resistance and reduced agglomeration of the ohmic contact region, independent of reaction temperatures. The reactive metal layer is preferably a refractory metal and the reaction control layer is preferably a refractory metal compound. The upper conductive layer is also preferably a refractory metal.

Abstract: A metal interconnect layer that fills in a via hole formed by first depositing a first Al--Cu film on the sidewalls of the via hole at a low temperature and a low sputtering power and then depositing a second Al--Cu film on the first Al--Cu film at a high temperature and high sputtering power. Sputtering is performed in two steps at low and high temperatures within the same sputtering chamber. The deposition at low temperature and low sputtering power provides good coverage in the via hole, and the deposition at high temperature and high sputtering power reduces the process time.

Abstract: A contact interface having a substantially continuous profile along a bottom and lower sides of the active surface of the semiconductor substrate formed within a contact opening. The contact interface is formed by depositing a layer of conductive material, such as titanium, using both a high bias deposition and a low bias deposition. The high bias and low bias deposition may be effected as a two-step deposition or may be accomplished by changing the bias from a high level to a low level during deposition, or vice versa. The conductive material is converted to a silicide by an annealing process to form the contact interface.

Abstract: A die including a corrosion monitoring feature is described. The die includes: (i) a surface including an active die region and a scribeline region that is adjacent the active die region; (ii) an insulating layer disposed above the surface and includes a first corrosion sensitive metal plug and a second corrosion sensitive metal plug in the scribeline region; and (iii) a metallization layer positioned above the insulating layer, the first corrosion sensitive metal plug and the second corrosion sensitive metal plug in the scribeline region and the metallization layer disposed above second corrosion sensitive metal plug is patterned to provide the metallization layer with a first opening extending from a top surface of the metallization layer down to a top surface of the second corrosion sensitive metal plug such that a solvent introduced above the top surface of the metallization layer flows into the second corrosion sensitive metal plug disposed below through the first opening in the metallization layer.

Abstract: Conductive structures, conductive lines, conductive SRAM lines, integrated circuitry, SRAM cells, and methods of forming the same are described. In one embodiment, a substrate is provided and a layer comprising TiN is physical vapor deposited over the substrate having greater than or equal to about 90% by volume <200> grain orientation. In another embodiment, at least two components are electrically connected by forming a layer of TiN over a substrate having the desired by-volume concentration of <200> grain orientation, and etching the layer to form a conductive line. In a preferred embodiment, conductive lines formed in accordance with the invention electrically connect at least two SRAM components and preferably form cross-coupling electrical interconnections between first and second inverters of an SRAM cell.

Abstract: An effective barrier layer to chemical attack of fluorine during chemical vapor deposition of tungsten from a tungsten fluoride source gas is fabricated by the present invention. A titanium nitride conformal barrier film can be formed by in-situ nitridation of a thin titanium film. The substrate is placed in a module wherein the pressure is reduced and the temperature raised to 350.degree. C. to about 700.degree. C. A titanium film is then deposited by plasma-enhanced chemical vapor deposition of titanium tetrahalide and hydrogen. This is followed by formation of titanium nitride on the titanium film by subjecting the titanium film to an nitrogen containing plasma such as an ammonia, an N.sub.2 or an NH.sub.3 /N.sub.2 based plasma. Tungsten is then deposited on the film of titanium nitride by plasma-enhanced chemical vapor deposition.

Abstract: A method is provided for forming metal layers in semiconductor channels or vias by using a very high pressure ionized metal deposition technique which results in improved sidewall step coverage with enhanced subsequent filling of the channel or vias by conductive materials. To obtain the very high pressure in excess of 100 mT, the plasma coil power is increased and the gas flow is increased while maintaining a constant pumping feed in the ionized metal deposition equipment.

Abstract: The present invention generally provides a method for processing a substrate having exposed surfaces of titanium and/or silicon prior to deposition of aluminum. The substrate is positioned adjacent a process zone which provides a nitrogen plasma so that exposed areas of titanium and silicon on the substrate are stuffed with nitrogen to form titanium nitride (TiN) and various compounds of silicon and nitrogen (Si.sub.x N.sub.y), respectively. The nitrogen treated surfaces, i.e, TiN and silicon/nitrogen compounds, are resistant to interaction with aluminum. In this manner, the formation of electrically insulating TiAl.sub.3 and/or the spiking of silicon is reduced or eliminated.

Abstract: A method for forming a copper structure with reduced dishing, using a self-aligned copper electroplating process. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer has a trench therein. A barrier layer is formed over the dielectric layer, a seed layer is formed on the barrier layer, and an insulating layer is formed on the seed layer. The insulating layer is patterned so as to expose the seed layer on the bottom and sidewalls of the trench, preferably using the trench photo mask. A copper layer is selectively electroplated onto the exposed seed layer on the bottom and sidewalls of the trench, while the insulating layer prevents copper deposition outside of the trench. The copper layer, the insulating layer, and the seed layer are planarized, stopping at the dielectric layer. Because of the self-aligned copper geometry, the copper suffers reduced dishing.

Abstract: A structure and method incorporating a CVD TiN barrier layer 230 over the aluminum plug 220 in order to prevent the high plug resistance caused by the blanket metal film stack 240, 250, and 260 deposition process. Unlike physical vapor deposited (PVD) TiN, CVD TiN 230 does not react with the aluminum 220 during annealing. CVD TiN has also been shown to be a better diffusion barrier for aluminum than PVD TiN. In addition, CVD TiN will disrupt any unfavorable grain boundary propagation through the aluminum plug which may act as a source of electromigration failure. Therefore, the CVD TiN 230 can increase the electromigration resistance, without increasing the contact/via resistance.

Abstract: A method for preserving the integrity of the underlying metal lines during planarization by inserting a nitride layer as an etch stop in an oxide-nitride-oxide dielectric layer underlying a spin-on polymer is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines wherein a gap is formed between the conducting lines. A first dielectric layer is deposited over the surfaces of the conducting lines wherein the first dielectric layer contains an etch stop layer wherein the gap remains between the conducting lines. A second dielectric layer is deposited overlying the first dielectric layer wherein the gap is filled by the second dielectric layer. The second dielectric layer is etched back so that the second dielectric layer remains only within the gap wherein the etch stop layer preserves the integrity of the underlying conducting lines.

Abstract: The multilevel interconnection forming method of the present invention comprises the following. A metal film containing aluminum is deposited on an insulating film of a substrate, and the metal film is patterned, to form a wiring layer of a first layer. An interlayer dielectric film forming part of the first layer is formed on an entire surface of the substrate, such that the interlayer dielectric film covers the wiring layer from upside. A hole is formed at a predetermined position of the interlayer dielectric film such that the hole reaches the wiring layer of the first layer. Aluminum is selectively deposited and filled into the hole by a CVD method, such that the aluminum is filled at a volume ratio smaller than 100% with respect to the hole. An active metal film is formed on an entire upper surface of an interlayer dielectric film including the hole filled with the aluminum. A metal layer containing aluminum is formed on the active metal film.

Abstract: A three elemental compound for diffusion barrier layer having a superior diffusion barrier characteristics manufactured by forming the compound between the silicon diffused into the diffusion barrier layer and the two elemental compound for diffusion barrier layer before the metal wire layer penetrates into the diffusion barrier layer to reach the underlying silicon layer, using the different characteristics of the diffusion rate as above, is disclosed. A method of forming three elemental compound for diffusion barrier layer according to the present invention comprises a silicon substrate. A silicide layer is deposited on the silicon substrate. A refractory metal nitride layer is then deposited on the silicide layer. A metal wire layer is deposited on the refractory metal nitride layer.

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide. An outer metal layer is formed over the seed layer metal oxide and the conductor metal oxide.

Abstract: A method of making a semiconductor device includes a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer. A transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.

Abstract: A method of forming a conformal aluminum film which is substantially smooth and void free on a refractory metal nitride barrier layer is provided and involves an initial pretreatment of the refractory metal nitride layer by exposing it to a directional gas plasma. An aluminum metal film is then formed over the refractory metal nitride layer. The process may be used to deposit and fill a via, contact, or trench opening with substantially void-free aluminum to provide an electrically conductive path between layers in a semiconductor device.

Abstract: A novel compound PVD target material, suitable for use in the fabrication of cobalt silicide layers on semiconductor devices is disclosed. The compound material is formed by blending an amount of SiO.sub.z with an amount of CoSi.sub.x to form a blended compound material CoSi.sub.x O.sub.y and then compressing and shaping said blended compound material in a hot powder press into an appropriate shape for use in a PVD sputtering chamber. A polysilicon MOSFET gate stack structure and a source/drain salicide structure incorporating the CoSi.sub.x O.sub.y compound material are described. The addition of a small amount of oxide to the cobalt silicide, when sputter deposited, results in an as-deposited film of CoSi.sub.x O.sub.y having smaller grain size and significantly enhanced thermal stability over conventional CoSi.sub.x, and other characteristics desirable in the fabrication of salicide MOSFET structures.

Abstract: The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least one hole, defined by walls, at least partly through a semiconducting material; forming a layer of electrically insulating material to cover said walls; and forming an electrically conductive material on said walls within the channel of the hole. Microelectronic devices containing the micro-post wiring of the present invention are also disclosed herein.

Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: Undesirable counter doping of n.sup.+ /p.sup.+ gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.

Abstract: A process has been developed which allows contact between levels of interconnect metallization structures, to occur without the use of via holes, etched in interlevel insulator layers. The process features creation of a raised tungsten plug structure, used to provide contact between underlying active device regions and an overlying interconnect metallization structure. The tungsten plug structure is formed by photolithographic masking and dry etching procedures, thus avoiding increasing the size of a tungsten seam, in the center of the plug structure. In addition the tungsten definition process, also results in a raised plug structure, allowing subsequent contact of interconnect metallization levels to proceed without the use of etched via holes in interlevel insulator layers.

Abstract: An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches are then filled with a conformal layer of silicon oxide. This is followed by overcoating with a layer of a hard material such as silicon nitride or boron nitride. Next, chemical-mechanical polishing is used to remove the hard layer everywhere except where it has filled the depressions that overlie the trenches. Then, a non-selective etch is used to remove the remaining hard layer material as well as some of the silicon oxide, so that a planar surface is maintained. Finally, chemical-mechanical polishing is used a second time to remove excess silicon oxide from above the trenches' surface.