At Least One Layer Forms A Diffusion Barrier Patents (Class 438/643)
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Publication number: 20130320536Abstract: An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.Type: ApplicationFiled: May 29, 2012Publication date: December 5, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Robert K. Leidy
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Publication number: 20130316531Abstract: Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Inventor: Naoki Takeguchi
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Patent number: 8592306Abstract: A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.Type: GrantFiled: June 21, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Thomas M. Shaw
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Publication number: 20130307154Abstract: Integrated circuits having electrically conductive traces are described. The electrically conductive traces may be formed of multiple electrically conductive layers. One or more of the multiple electrically conductive layers may have a cut formed therein to form a gap in that electrically conductive layer. One or more electrical conductive layers of the electrical conductive traces may bridge the gap.Type: ApplicationFiled: April 1, 2013Publication date: November 21, 2013Applicant: Sand 9, Inc.Inventors: Guiti Zolfagharkhani, Jan H. Kuypers
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Patent number: 8586133Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.Type: GrantFiled: July 2, 2012Date of Patent: November 19, 2013Assignee: Lam Research CorporationInventors: Igor C. Ivanov, Weiguo Zhang, Artur Kolics
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Publication number: 20130299990Abstract: A single metal damascene structure including an insulating layer, a metal filling layer and a barrier layer is provided. The insulating layer has an opening therein, and the metal filling layer is positioned in the opening. The barrier layer is located between the filling metal layer and the insulating layer. The material of the barrier layer includes an alloy, and the ally includes a copper element and at least one another metal.Type: ApplicationFiled: May 14, 2012Publication date: November 14, 2013Applicant: United Microelectronics Corp.Inventor: Chien-Fu Chen
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Publication number: 20130285245Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.Type: ApplicationFiled: March 25, 2013Publication date: October 31, 2013Inventors: Cyril Cabral, Jr., Jeffrey P. Gambino, Qiang Huang, Takeshi Nogami, Kenneth P. Rodbell
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Patent number: 8564132Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.Type: GrantFiled: August 17, 2011Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Daniel C. Edelstein
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Patent number: 8563427Abstract: A semiconductor chip includes a substrate with a barrier region and a conductive diffusion region formed in the substrate and is surrounded by the barrier region. The conductive diffusion region may provide a conductive oath from top of the substrate to bottom of the substrate.Type: GrantFiled: December 29, 2010Date of Patent: October 22, 2013Assignee: SK Hynix Inc.Inventor: Sung Min Kim
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Publication number: 20130273733Abstract: Described are manganese-containing films, as well as methods for providing the manganese-containing films. Doping manganese-containing films with Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V allows for enhanced copper barrier properties of the manganese-containing films. Also described are methods of providing films with a first layer comprising manganese silicate and a second layer comprising a manganese-containing film.Type: ApplicationFiled: April 11, 2013Publication date: October 17, 2013Inventors: Jing Tang, Zhefeng Li, Paul F. Ma, David Thompson
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Patent number: 8552565Abstract: A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.Type: GrantFiled: August 5, 2011Date of Patent: October 8, 2013Inventors: Yu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Long-Sheng Yeou
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Publication number: 20130260553Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.Type: ApplicationFiled: May 13, 2013Publication date: October 3, 2013Inventors: Hui Jae Yoo, Jeffrey D. Bielefeld, Sean W. King, Sridhar Balakrishnan
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Publication number: 20130256841Abstract: The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: CREE, INC.Inventors: Van Mieczkowski, Helmut Hagleitner, William T. Pulz
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Patent number: 8546944Abstract: A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship.Type: GrantFiled: December 22, 2010Date of Patent: October 1, 2013Assignee: Intel CorporationInventor: Kyu S. Min
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Publication number: 20130252417Abstract: A thin film forming method in which a thin film is formed on a surface of a target object to be processed to fill a recess formed in the surface of the target object includes the steps of forming a metal layer for filling on the surface of the target object to fill the recess formed in the surface of the target object and forming a metal film for preventing diffusion on an entire surface of the target object to cover the metal layer for filling. The thin film forming method further includes the step of annealing the target object having the metal film for preventing diffusion formed thereon.Type: ApplicationFiled: September 14, 2012Publication date: September 26, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Tadahiro ISHIZAKA, Jonathan Rullan, Osamu Yokoyama, Atsushi Gomi, Chiaki Yasumuro, Takara Kato, Tatsuo Hatano, Hiroaki Kawasaki
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Publication number: 20130252418Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.Type: ApplicationFiled: May 1, 2013Publication date: September 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: CHARLES L. ARVIN, KENNETH BIRD, CHARLES C. GOLDSMITH, SUNG K. KANG, MINHUA LU, CLARE J. MCCARTHY, ERIC D. PERFECTO, SRINIVASA S.N. REDDY, KRYSTYNA W. SEMKOW, THOMAS A. WASSICK
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Patent number: 8536707Abstract: A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices.Type: GrantFiled: November 29, 2011Date of Patent: September 17, 2013Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: James Wholey, Ray Myron Parkhurst, Marshall Maple
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Patent number: 8536706Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.Type: GrantFiled: December 6, 2012Date of Patent: September 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yumi Hayashi, Atsuko Sakata, Kei Watanabe, Noriaki Matsunaga, Shinichi Nakao, Makoto Wada, Hiroshi Toyoda
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Patent number: 8536050Abstract: In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element.Type: GrantFiled: May 6, 2011Date of Patent: September 17, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Kai Frohberg, Ralf Richter, Torsten Huisinga, Katrin Reiche
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Patent number: 8531035Abstract: A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.Type: GrantFiled: August 31, 2011Date of Patent: September 10, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Tsang-Jiuh Wu
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Publication number: 20130228924Abstract: Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd).Type: ApplicationFiled: February 22, 2013Publication date: September 5, 2013Applicant: SKYWORKS SOLUTIONS, INC.Inventor: Kezia Cheng
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Publication number: 20130221528Abstract: Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including a barrier, a copper (Cu) layer disposed over the barrier, and a first titanium (Ti) layer disposed over the Cu layer. The metalized structure can further include a sputtered titanium tungsten (TiW) layer disposed over the first Ti layer. The barrier can include an assembly of titanium nitride (TiN) and Ti layers. The metalized structure can further include a second Ti layer disposed over the sputtered TiW layer.Type: ApplicationFiled: February 22, 2013Publication date: August 29, 2013Applicant: Skyworks Solutions, Inc.Inventor: Skyworks Solutions, Inc.
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Publication number: 20130221527Abstract: An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Chao-Kun Hu
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Patent number: 8518762Abstract: Provided is a method for manufacturing a semiconductor device having favorable electric characteristics with a high yield. A groove and/or a contact hole reaching a semiconductor region or a conductive region is formed in an insulating film covering the semiconductor region or the conductive region; a first conductive film is formed in the groove and/or the contact hole; the first conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas and to an atmosphere containing water to be fluidized partially or entirely; and a second conductive film is formed over the first conductive film.Type: GrantFiled: June 29, 2011Date of Patent: August 27, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Yuta Endo
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Patent number: 8518819Abstract: A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.Type: GrantFiled: March 16, 2011Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih Chieh Chang, Chih-Chung Chang, Kei-Wei Chen, Ying-Lang Wang
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Publication number: 20130217225Abstract: A method comprising the steps of: forming a copper film (101) on a Cu barrier film (100); forming a mask material (102) on the copper film (101); anisotropically etching the copper film (101) until the Cu barrier film (100) is exposed, using the mask material (102) as a mask; and removing the mask material (102) and subsequently forming a plating film (104) that contains a substance for suppressing copper diffusion on the anisotropically etched copper film (101), using an electroless plating method that utilizes a selective deposition in which catalytic action occurs with respect to the copper film (101) but not the Cu barrier film (100).Type: ApplicationFiled: July 29, 2011Publication date: August 22, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Takashi Hayakawa, Kenichi Hara, Takashi Tanaka
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Publication number: 20130203249Abstract: A method for providing metal filled features in a layer is provided. A metal seed layer is deposited on tops and bottoms of the features. Metal seed layer on tops of the features and overhangs is removed without removing metal seed layer on bottoms of features. An electroless deposition of metal is provided to fill the features, wherein the electroless deposition first deposits on the metal seed layer on bottoms of the features.Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Applicant: LAM RESEARCH CORPORATIONInventor: Praveen Reddy NALLA
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Patent number: 8502381Abstract: A microelectronic topography includes a dielectric layer (DL) with a surface higher than an adjacent bulk metal feature (BMF) and further includes a barrier layer (BL) upon the BMF and extending higher than the DL. Another microelectronic topography includes a BL with a metal-oxide layer having a metal element concentration which is disproportionate relative to concentrations of the element within metal alloy layers on either side of the metal-oxide layer. A method includes forming a BL upon a BMF such that portions of a first DL adjacent to the BMF are exposed, selectively depositing a second DL upon the BL, cleaning the topography thereafter, and blanket depositing a third DL upon the cleaned topography. Another method includes polishing a microelectronic topography such that a metallization layer is coplanar with a DL and further includes spraying a deionized water based fluid upon the polished topography to remove debris from the DL.Type: GrantFiled: January 25, 2011Date of Patent: August 6, 2013Assignee: Lam Research CorporationInventor: Igor C. Ivanov
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Publication number: 20130193518Abstract: Semiconductor devices are provided.Type: ApplicationFiled: September 13, 2012Publication date: August 1, 2013Applicant: SK HYNIX INC.Inventors: Chun Soo KANG, Sang Jin OH
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Publication number: 20130187281Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.Type: ApplicationFiled: March 11, 2013Publication date: July 25, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Kabushiki Kaisha Toshiba
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Publication number: 20130187283Abstract: Provided is a method of manufacturing a semiconductor device of a multilayer wiring structure that comprises a CFx film as an interlayer insulating film, that can make the most of the advantage of the CFx film having a low dielectric constant, and that can prevent degradation of the properties of the CFx film due to CMP. The method of this invention includes (a) forming a CFx film, (b) forming a recess of a predetermined pattern on the CFx film, (c) providing a wiring layer so as to bury the recess and to cover the CFx film, and (d) removing the excess wiring layer on the CFx film other than in the recess by CMP (Chemical Mechanical Polishing), thereby exposing a surface of the CFx film, wherein (e) nitriding the surface of the CFx film is provided before or after (b).Type: ApplicationFiled: October 3, 2011Publication date: July 25, 2013Applicant: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Tadahiro Ohmi, Xun Gu
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Patent number: 8492808Abstract: In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.Type: GrantFiled: July 13, 2011Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventors: Kazuyuki Omori, Kenichi Mori, Naohito Suzumura
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Patent number: 8486773Abstract: A semiconductor film having an impurity region to which at least an n-type or p-type impurity is added and a wiring are provided. The wiring includes a diffusion prevention film containing a conductive metal oxide, and a low resistance conductive film over the diffusion prevention film. In a contact portion between the wiring and the semiconductor film, the diffusion prevention film and the impurity region are in contact with each other. The diffusion prevention film is formed in such a manner that a conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas to form an oxide of a metal material contained in the conductive film, the conductive film in which the oxide of the metal material is formed is exposed to an atmosphere containing water to be fluidized, and the fluidized conductive film is solidified.Type: GrantFiled: June 29, 2011Date of Patent: July 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tetsuhiro Tanaka
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Publication number: 20130178058Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.Type: ApplicationFiled: February 28, 2013Publication date: July 11, 2013Applicants: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: International Business Machines Corporation, Toshiba America Electronic Components, Inc.
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Publication number: 20130168862Abstract: A method of manufacturing a semiconductor memory and a structure of the semiconductor memory device, where the semiconductor memory device includes a material layer and a barrier layer. The barrier layer has a structure in which a horizontal cross-section of an upper portion thereof is larger than that of a lower portion thereof so that a fine pattern may be formed on the material layer using the barrier layer pattern without a structural damage or collapse in etching the underlying material layer.Type: ApplicationFiled: June 8, 2012Publication date: July 4, 2013Inventor: Ha Chang JUNG
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Publication number: 20130161796Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.Type: ApplicationFiled: December 23, 2011Publication date: June 27, 2013Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng
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Patent number: 8461684Abstract: An interconnect structure for integrated circuits incorporates a layer of cobalt nitride that facilitates the nucleation, growth and adhesion of copper wires. The cobalt nitride may deposited on a refractory metal nitride or carbide layer, such as tungsten nitride or tantalum nitride, that serves as a diffusion barrier for copper and also increases the adhesion between the cobalt nitride and the underlying insulator. The cobalt nitride may be formed by chemical vapor deposition from a novel cobalt amidinate precursor. Copper layers deposited on the cobalt nitride show high electrical conductivity and can serve as seed layers for electrochemical deposition of copper conductors for microelectronics.Type: GrantFiled: June 1, 2011Date of Patent: June 11, 2013Assignee: President and Fellows of Harvard CollegeInventors: Roy Gerald Gordon, Hoon Kim, Harish Bhandari
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Patent number: 8461043Abstract: Plug contacts may be formed with barrier layers having thicknesses of less than 50 ? in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide.Type: GrantFiled: April 11, 2011Date of Patent: June 11, 2013Assignee: Micron Technology, Inc.Inventors: Avraham Rozenblat, Shai Haimson, Rotem Drori, Maor Rotlain, Dror Horvitz
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Patent number: 8461683Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.Type: GrantFiled: April 1, 2011Date of Patent: June 11, 2013Assignee: Intel CorporationInventors: Hui Jae Yoo, Jeffery D. Bielefeld, Sean W. King, Sridhar Balakrishnan
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Patent number: 8460989Abstract: Disclosed are methods for forming a metal-containing layer on a substrate. A vapor comprising at least one precursor compound selected from the group consisting of (Cp)V(=NtBu)(NEt2)2; (Cp)V(=NtBu)(NMe2)2; (Cp)V(=NtBu)(NEtMe)2; (Cp)V(?NiPr)(NEt2)2; (Cp)V(?NiPr)(NMe2)2; (Cp)V(?NiPr)(NEtMe)2; (Cp)V(?NC5H11)(NEt2)2; (Cp)V(?NC5H11)(NMe2)2; (Cp)V(?NC5H11)(NEtMe)2; (Cp)Nb(=NtBu)(NEt2)2; (Cp)Nb(=NtBu)(NMe2)2; (Cp)Nb(=NtBu)(NEtMe)2; (Cp)Nb(?NiPr)(NEt2)2; (Cp)Nb(?NiPr)(NMe2)2; (Cp)Nb(?NiPr)(NEtMe)2; (Cp)Nb(?NC5H11)(NEt2)2; (Cp)Nb(?NC5H11)(NMe2)2; and (Cp)Nb(?NC5H11)(NEtMe)2 is provided. At least one reaction gas selected from the group consisting of ozone and water is provided. The vapor and the reaction gas react with the substrate according to a deposition process to form the metal-containing layer on at least one surface of the substrate.Type: GrantFiled: October 6, 2009Date of Patent: June 11, 2013Assignee: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des ProcedesInventors: Nicolas Blasco, Anthony Correia-Anacleto, Audrey Pinchart, Andreas Zauner
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Publication number: 20130143401Abstract: Disclosed methods cap exposed surfaces of copper lines with a layer of metal or metal-containing compound combined with silicon. In some cases, the metal or metal-containing compound forms an atomic layer. In certain embodiments, the methods involve exposing the copper surface first to a metal containing precursor to form an atomic layer of adsorbed precursor or metal atoms, which may optionally be converted to an oxide, nitride, carbide, or the like by, e.g., a pinning treatment. Subsequent exposure to a silicon-containing precursor may proceed with or without metallic atoms being converted.Type: ApplicationFiled: June 1, 2012Publication date: June 6, 2013Inventors: Jengyi Yu, Gengwei Jiang, Pramod Subramonium, Roey Shaviv, Hui-Jung Wu, Nagraj Shankar
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Patent number: 8440515Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.Type: GrantFiled: August 13, 2008Date of Patent: May 14, 2013Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Michael P. Violette, Robert Burke
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Patent number: 8440564Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.Type: GrantFiled: July 17, 2012Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
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Publication number: 20130113102Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Shaoning Yao, Xuesong Li, Samuel S. S. Choi
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Publication number: 20130113105Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).Type: ApplicationFiled: December 28, 2012Publication date: May 9, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
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Publication number: 20130113101Abstract: A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.Type: ApplicationFiled: November 7, 2011Publication date: May 9, 2013Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 8435830Abstract: Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.Type: GrantFiled: March 17, 2010Date of Patent: May 7, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Junho Jeong, Sukhun Choi, Jangeun Lee, Kyunghyun Kim, Sechung Oh, Kyungtae Nam
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Patent number: 8432038Abstract: A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.Type: GrantFiled: May 20, 2010Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Weng-Jin Wu, Yung-Chi Lin, Wen-Chih Chiou
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Patent number: 8431482Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.Type: GrantFiled: January 31, 2012Date of Patent: April 30, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Errol T. Ryan, Xunyuan Zhang
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Patent number: 8424175Abstract: A process for fabricating a piezoactuated storage device having a tip array and a memory media, which includes but is not limited to: etching the regions on the surface of the silicon wafer to produce substantially pyramidal etch pits by anisotropic etching or chemical etching with potassium hydroxide (KOH); growing an oxide layer on a top surface of the silicon wafer and in the substantially pyramidal etch pits to produce oxidation sharpening of the substantially pyramidal etch pits; forming an array of conductive tips of a nanocarbon film of nanostructured carbon material by deposition, wherein the nanostructured carbon material is ultrananocrystalline diamond (UNCD), ta-C, or diamond-like carbon films; and forming an oxygen diffusion barrier layer by deposition of a TiAl, TaAl, or any other oxygen diffusion barrier layer material on the nanocarbon film.Type: GrantFiled: September 10, 2009Date of Patent: April 23, 2013Assignee: UChicago Argonne, LLCInventor: Orlando H. Auciello