Abstract: A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.

Abstract: A method for forming tungsten structures over silicon substrates, including the following steps. A silicon substrate is having a patterned dielectric layer formed thereon defining a tungsten structure opening is provided. The silicon substrate is pre-heated to a temperature of from about 430 to 440° C. A Si-rich WSx layer is formed over the patterned dielectric layer, lining the tungsten structure opening. A WSix nucleation layer is formed over the Si-rich WSix layer. A tungsten bulk layer is formed over the WSix nucleation layer, filling the tungsten structure opening, whereby fluorine attack of the Si substrate is minimized.

Abstract: Within a method for forming a patterned microelectronic layer there is first provided a substrate having an aperture formed therein. There is then formed over the substrate and filling the aperture a blanket microelectronic layer. There is then planarized, while employing a first planarizing method, the blanket microelectronic layer to form a once planarized patterned microelectronic layer within the aperture. There is then thermal annealed, while employing a thermal annealing method, the once planarized patterned microelectronic layer within the aperture to form a thermal annealed once planarized patterned microelectronic layer within the aperture. Finally, there is then planarized, while employing a second planarizing method, the thermal annealed once planarized patterned microelectronic layer within the aperture to form a thermal annealed twice planarized patterned microelectronic layer within the aperture.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: A method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.

Abstract: A method for etching contact openings into a polycide layer including a metal silicide layer and a polysilicon layer comprises providing a substrate that includes a polycide layer, forming a patterned photoresist mask, and etching with a series of plasmas. The etches include a silicide etch, a polycide etch including chlorine gas and nitrogen gas where the nitrogen flow rate is between 20% and about 30% of the sum of the nitrogen flow rate plus the chlorine flow rate, and a poly overetch. A polycide etch with a composition in the specified range will have a polycide selectivity greater than one.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is also over the insulative material outside of the opening. The metal-containing material at least partially fills the opening. At least a portion of both the metal-containing fill material and the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.

Abstract: A method of fabricating copper damascene. In this invention, only crystalline copper metal layer is formed inside the damascene trench and only amorphous copper metal layer is formed outside the damascene trench. During stacking the copper metal layer, copper metal stacks up to form crystalline copper metal with good lattice packing according to the position of the copper seed layer. Conversely, amorphous copper metal is formed in positions where no copper seed layer exists. Since the amorphous copper metal is softer than the crystalline copper metal, lower pressure and the ordinary slurry are used in chemical mechanical polishing to remove amorphous copper metal layer outside the damascene trench, in order to form a flat-surfaced copper damascene structure.

Abstract: An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening, and a conductor core fills the opening over the barrier layer. Self-aligned sub-caps of silicide and/or oxides are formed over the conductor core and then capped by a capping layer which covers the sub-caps and the channel dielectric layer.

Abstract: A method of forming wiring of a uniform film thickness using a damascene process is proposed. Nitride tantalum, copper, another copper, and another nitride tantalum, for example, all constituting conductive films of different polishing rates, are overlayed on the top layer of an insulating film in which one wiring groove and another wiring groove are formed, and, by setting and forming the film thickness of the nitride tantalum, the copper, the other copper, and the other nitride tantalum so that the height of the surface of the nitride tantalum formed on a silicon oxide film excluding the one wiring groove matches the height of the surface of the other nitride tantalum formed on the top layer of the one wiring groove. Subsequently, polishing takes over to complete the forming process.

Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

Abstract: The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.

Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Abstract: For filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic seed layer. The sacrificial layer of protective material is dissolved away from the underlying material by the acidic catalytic solution such that the underlying material is exposed to the acidic catalytic solution.

Abstract: The present invention provides a method of reducing dishing and erosion of a conductive structure in the process of chemical mechanical polishing. The method comprises providing a dielectric layer having at least a via hole thereon. A barrier layer is formed on the dielectric layer and the via hole. A conductive layer, such as copper layer, is formed on the barrier layer and filled into the via hole to form the conductive structure. The partial conductive layer is removed to expose the partial barrier layer. The exposed barrier layer and the conductive structure are polished. The polishing step is implemented by using a reagent whereby a metallic compound is formed on the conductive structure for protecting the conductive structure against dishing and erosion.

Abstract: A planarization method includes providing an aluminum-containing surface and positioning it for contact with a fixed abrasive article in the presence of a composition preferably including a surfactant, a complexant, and an oxidant, wherein the solution has a pH of less than about 10.

Abstract: A method of for electroless copper deposition using a Pd/Pd acetate seeding layer formed in using only two components (Pd acetate and solvent) to form an interconnect for a semiconductor device. The invention has two preferred embodiments. The first embodiment forms a Key seed layer composed of Pd/Pd acetate by a spin-on or dip process for the electroless plating of a Cu plug. The second embodiment forms a Pd passivation cap layer over the Cu plug to prevent the Cu plug from oxidizing.

Abstract: A damascene process for forming a via that leads to a conductive layer on a substrate. A low dielectric constant material layer is formed over the substrate. A low temperature hard mask layer is formed over the low dielectric constant material layer. The low temperature hard mask layer is patterned to form an opening above the conductive layer. Using the low temperature hard mask layer as a mask, the exposed low dielectric constant material layer is etched to form a via hole. An adhesion promoter liner is formed on the interior walls of the via hole. Metallic material is deposited into the via hole to form a via.

Abstract: An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer.

Abstract: A method for polishing a semiconductor wafer, includes the steps of supplying a polishing slurry between a polishing pad and a semiconductor wafer; polishing a surface of the semiconductor wafer with the polishing pad in a CMP process; and controlling the temperature of the polishing slurry to be in a range between 2° C. to 10° C. while the semiconductor wafer is polished.

Abstract: A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.

Abstract: A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of ‘Erosion’ to be prevented, as well as it is capable of being prevented occurrence of ‘micro-scratch’ on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.

Abstract: A method of forming a semiconductor device having a simultaneously formed gate and interconnect therefore, includes preparing a silicon substrate, including isolating active areas thereon; forming an insulating layer in a gate region of an active area; depositing a first barrier metal layer; depositing a gate place-holder layer on the first barrier metal layer; etching the gate place-holder layer and the first barrier metal layer to form a gate stack; building an oxide sidewall about the gate stack; forming a source region and a drain region in the active area; depositing an oxide layer over the structure and etching the oxide layer to form a dual damascene trench to the level of the gate place-holder and to form vias for the source region and drain region; removing the gate place-holder; depositing a second barrier metal layer; depositing copper into the dual damascene trench and the vias; and removing excess copper and all portions of the second barrier metal layer to the level of the last deposited oxide l

Abstract: Photosensitive insulating films are laminated and formed on lower-layer interconnection layers and a connection hole is formed in the photosensitive insulating film, and a interconnection groove is formed on the photosensitive insulating film. The upper-layer interconnection layers are formed in a manner so as to fill the connection hole and the groove. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method thereof having a multi-layer interconnection structure, which have advantages in that the connection hole and a groove are formed by using a simple process, the yield can be improved and the number of processes and the costs can be reduced.

Abstract: Metal CMP with reduced dishing and overpolish insensitivity is achieved with an abrasive-free polishing composition having a pH and oxidation-reduction potential in the domain of passivation of the metal and, therefore, a low static etching rate at high temperatures, e.g., higher than 50° C. Embodiments of the present invention comprise CMP of Cu film without any abrasive using a composition comprising one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, one or more agents to achieve a pH of about 3 to about 10 and deionized water.

Abstract: A semiconductor device having a conductive layer side surface slope of at least 90° and a method for making the same is provided. An interlayer dielectric film and a conductive layer are formed on a semiconductor substrate. The interlayer dielectric film has a side surface slope defining a hole of less than 90°. A conductive layer having a side surface slope of at least 90° is formed in the hole defined by the interlayer dielectric film. The semiconductor device is manufactured by coating a preliminary film on a semiconductor substrate. Patterning the preliminary film forms a preliminary film pattern having a side surface slope of 90°. The interlayer dielectric film is formed on the semiconductor substrate and the preliminary film pattern. Removing some of the interlayer dielectric film exposes an upper surface of the preliminary film pattern.

Abstract: The reliability and elecrtromigration resistance of planarized metallization patterns, e.g., of copper, in-laid in the surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one alloying element for the metal of the features, and then uniformly diffusing at least a minimum amount of the at least one thin layer for a minimum depth below the upper surfaces of the metallization features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: A novel copper damascene method for making metal interconnections on semiconductor integrated circuits was achieved. This method avoids overpolishing into a low-k dielectric fluorine-doped glass which would cause copper-flake defects resulting in intralevel electrical shorts. The method utilizes a stacked hard-mask layer on the doped glass layer consisting of a first polish-stop layer, a sacrificial insulating layer and an upper second polish-stop layer. After etching trenches in the stacked hard-mask layer and the doped glass, a copper layer is deposited to fill the trenches and is polished back to the second polish-stop layer. The high polish-back selectivity of the copper to the second polish-stop layer results in improved polish-back uniformity across the substrate. The relatively thin second polish-stop layer can then be polished back and partially into the sacrificial layer without overpolishing and damaging the underlying first polish-stop layer.

Abstract: A method of manufacturing semiconductor devices is provided for forming a tungsten plug or polysilicon plug and minimizing the step-height of the intermediate insulating layer. An etching composition for this process is also provided as are semiconductor devices manufactured by this process. The method of manufacturing semiconductor devices includes the steps of forming a tungsten film having a certain thickness on an insulating layer and burying contact holes formed in the insulating layer constituting a specific semiconductor structure, and spin-etching the tungsten film using a certain etching composition such that the tungsten film is present only inside the contact holes not existing on the insulating film.

Abstract: Embedded interconnections of copper are formed by forming an insulating layer, forming embedded interconnections of copper in the insulating layer, making an exposed upper surface of the insulating layer and an exposed surface of the embedded interconnections of copper coplanar according to chemical mechanical polishing, and forming a protective silver film on the exposed surface of the embedded interconnections of copper. These steps are repeated on the existing insulating layer thereby to produce multiple layers of embedded interconnections of copper. The exposed surface of the embedded interconnections of copper is plated with silver according to immersion plating.

Abstract: A semiconductor device and a method of making it involve the semiconductor device (10, 71, 101, 121, 151, 201) having a substrate (11, 73, 153) with spaced source and drain regions (13-14, 76-78, 154). A gate section (21, 81-82, 123, 203) projects upwardly from between an adjacent pair of the regions, into an insulating layer (31, 83, 103, 122, 157). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (36, 87, 126), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (41-42, 91-93, 107-108, 138-139, 158) on opposite sides of and immediately adjacent the gate section. A conductive layer (51, 96, 111, 161, 171) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: A novel and improved method of fabricating an integrated circuit, in which special copper films are formed by a combination of physical vapor deposition (PVD), chemical mechanical polish (CMP) and electrochemical copper deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By these techniques, high aspect ratio trenches can be filled with copper without the problem of dishing. A special, selective electrochemical deposition (ECD) of copper metal is utilized taking place only on the seed layer in the trench. This auto-plating or “plate-up” occurs only in the trench and provides good sealing around the trench perimeter and fine copper metal coverage of the trench for subsequent robust interconnects.

Abstract: A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenche

Abstract: A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at least one migration region; applying a layer material; adding a material to the layer material; and performing a heat treatment such that the layer material migrates from the migration region to the target region and a layer which is self-aligned and self-patterned with respect to the target region is formed. The method has the advantage that the layer material, which can often only be etched with difficulty, does not have to be patterned directly. The desired structure of the layer is predetermined by preliminarily structuring the substrate into a target region and a migration region, and is produced by the migration of the layer material as a result of the heat treatment.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening, and a conductor core fills the opening over the barrier layer. Self-aligned sub-caps of silicide and/or oxides are formed over the conductor core and then capped by a capping layer which covers the sub-caps and the channel dielectric layer.

Abstract: A method is disclosed to improve copper barrier and adhesion properties of copper interconnections in integrated circuits. It is shown that combining ion metal plasma (IMP) deposition along with in-situ chemical vapor deposition (CVD) of barrier and adhesion materials provides the desired adhesion of and barrier to diffusion of copper in damascene structures. IMP deposition is performed with tantalum or tantalum nitride while CVD deposition is performed with a binary or a ternary compound from a group consisting of titanium nitride, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, titanium silicon nitride. IMP deposition provides good adhesion of copper to insulator materials, while CVD deposition provides good sidewall coverage in a copper filled trench and a copper seed layer provides good adhesion of bulk copper to adhesion/barrier layer. The IMP/CVD deposited adhesion/barrier layer is thin, thus providing low via resistance.

Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.

Abstract: A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization.

Abstract: In a semiconductor memory device, first insulating films are formed on a semiconductor substrate. Element isolating layers are formed on the semiconductor substrate for isolating element forming regions set at regular intervals in the semiconductor substrate, such that the upper surface of the element isolating layers are located at a higher level than the upper surface of the semiconductor substrate. First conductive layers are formed at regular intervals on the first insulating films. A second insulating film is formed on the element isolating layers and the first insulating film. A second conductive layer, which has a lower surface with irregularities corresponding to the configurations of the element isolating layers and the first conductive layer, and a flat upper surface irrespective of the configurations of the element isolating films and the first conductive layer, is formed on the second insulating film.

Abstract: A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.

Abstract: A method of etching trenches through a low-k material layer using a hard mask wherein the trenches are sized down from the mask size by etching without sacrificing a vertical trench profile is described. A low-k dielectric material is provided over a region to be contacted on a substrate. A hard mask layer is deposited overlying the dielectric material. A mask is formed over the hard mask layer wherein the mask has a first opening of a first width. A second opening is etched in the hard mask layer where it is exposed by the mask wherein the second opening has a second width smaller than the first width and wherein the second opening has inwardly sloping sidewalls. A trench is etched through the dielectric layer to the region to be contacted through the second opening whereby the trench has a width equal to the second width. The trench is filled with a metal layer to complete fabrication of the integrated circuit device.

Abstract: A method for manufacturing an interconnect structure of a semiconductor device includes forming a bottom interconnect layer underlying a dielectric layer and overlying a silicon substrate; forming a through-hole in the dielectric layer to expose the bottom interconnect later; depositing a first barrier metal layer overlying the dielectric layer and on an inner wall of the through-hole; depositing a metal layer on the first barrier metal layer for filling the through-hole; etching the metal layer and the first barrier metal layer until the dielectric film is exposed to thereby form a via plug of the metal layer and the barrier metal layer; depositing a second barrier metal layer on the dielectric film and the via plug; and depositing an interconnect layer of which a main component is aluminum on the second barrier metal layer.

Abstract: Metal wiring in a semiconductor device and method for fabricating the same, the metal wiring including a first interlayer insulating film having a first contact hole to a region of a semiconductor substrate, a barrier metal film on an inside surface of the first contact hole, a second interlayer insulating film having a second contact hole to the barrier metal film formed on the first interlayer insulating film, a contact plug in the first and second contact holes in contact with the barrier metal film, and a metal wiring formed on the second interlayer insulating film in contact with the contact plug, whereby permitting to form a barrier metal film under a contact hole regardless of an aspect ratio and an area of the contact hole.

Abstract: A refractory Metal Nitride and a refractory metal Silicon Nitride layer (64) can be formed using metal organic chemical deposition. More specifically, tantalum nitride (TaN) (64) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET) and ammonia (NH3). By the inclusion of silane (SiH4), tantalum silicon nitride (TaSiN) (64) layer can also be formed. Both of these layers can be formed at wafer temperatures lower than approximately 400° C. with relatively small amounts of carbon (C) within the film. Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) (64) that is relatively conformal and has reasonably good diffusion barrier properties.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.

Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Abstract: The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.