Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.

Abstract: A polymer film including an adhesive layer, which can be peeled off with heat, is bonded to the upper surface of a semiconductor layer. Then, a KrF excimer laser light beam is applied to a surface of a substrate opposite to the semiconductor layer. This causes local heating at the laser spot, so that the bonding of atoms is cut off at the interface between the semiconductor layer and the substrate, thereby forming a thermal decomposition layer between the substrate and the semiconductor layer. Subsequently, the substrate is heated at a given temperature, so that the adhesive layer foams to lose its adhesive power. As a result, the polymer film is easily peeled off from the semiconductor layer.

Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: The present invention relates particularly to a method of and an apparatus for forming a fine interconnection in a highly integrated circuit formed on a semiconductor substrate. The method has the steps of preparing a substrate having fine recesses formed in a surface thereof, dispersing ultrafine particles made at least partly of a metal in a predetermined solvent, producing an ultrafine particle dispersed liquid, supplying the ultrafine particle dispersed liquid to the fine recesses of the substrate, heating the substrate to melt and bond the metal, and chemical mechanical polishing the surface of the substrate to remove an excessively attached metal therefrom. According to the present invention, it is possible to stably deposit an interconnection metal of good quality using an inexpensive material.

Abstract: Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.

Abstract: A low resistance path extends from a first region of a semiconductor substrate to a second region thereof. The low resistance path is produced by depositing a metal such as aluminum on the surface of the substrate and then directing a laser beam onto the metal causing the metal and a portion of the substrate beneath the metal to melt forming an alloy of the metal and the substrate material.

Abstract: A laser annealing mask is provided with cross-hatched sub-resolution aperture patterns. The mask comprises a first section with aperture patterns for transmitting approximately 100% of incident light, and at least one section with cross-hatched sub-resolution aperture patterns for diffracting incident light. In one aspect, a second mask section with cross-hatched sub-resolution aperture patterns has an area adjacent a vertical edge and a third mask section with cross-hatched sub-resolution aperture patterns adjacent the opposite vertical edge, with the first mask section being located between the second and third mask sections. The section with cross-hatched sub-resolution aperture patterns transmits approximately 40% to 70%,, and preferably 50% to 60% of incident light energy density. In some aspects, the section with cross-hatched sub-resolution aperture patterns includes a plurality of different cross-hatched aperture patterns.

Abstract: A method for forming via holes includes placing an insulating layer on a first wiring layer, forming opening portions in the insulating layer, and forming a second wiring layer on the insulating layer. At the time of forming the opening portions, the insulating layer is irradiated with a laser beam with the focus position staggered.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: Semiconductor devices with highly reliable Cu interconnects exhibiting reduced resistance are formed by sequentially depositing a seedlayer by PVD, depositing a conformal seedlayer enhancement film by CVD, and then laser thermal annealing the seedlayer enhancement film in nitrogen to expel impurities, enhance film conductivity, reduce film stress, increase film density, and reduce film roughness. Embodiments include single and dual Cu damascene techniques formed in dielectric layers having a dielectric constant no greater than about 3.9.

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract: A semiconductor device having an array of dummy interconnections in a fuse window are proposed. The each dummy interconnection comprised of a fuse body scheduled to be blown away by laser beam, a fuse wiring extended up to the bottom of the fuse body from one side of the fuse window, and another fuse wiring extended up to the bottom of the fuse body form the another side of the fuse window. Contact plugs are disposed on terminal portions of the fuse wirings respectively, the terminal portions facing to each other having a predetermined gap between them. The bottom surfaces of both terminal portions of the fuse body are electrically connected with the facing terminal portions of the fuse wirings through the contact plugs, respectively. The length of the fuse body is set so as to have a length not shorter than the predetermined gap and not exceeding a diameter of laser beam to blow off the fuse body.

Abstract: A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a connection through the p layer 13 to the underlying n++ layer 12, a column of semi-conductor material is heated, the column passing through the various doped layers and the material in the column being heated or melted to allow migration of dopant between layer of the device in the region of the column.

Abstract: To reduce manufacturing time in a production line for a semiconductor integrated circuit device, plural wafers in a lot are divided into the same number according to the number of manufacturing devices. Each group of the divided wafers is allocated to each of plural manufacturing devices in a state that each group is housed in each of plural division carriers and one sheet processing is applied to the wafer in the plural manufacturing devices in parallel.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: In an MIS field effect transistor having a gate electrode formed on a first semiconductor layer which is a polycrystalline silicon film on an insulating substrate through a gate insulating film, a channel region formed in the semiconductor layer and a source region and a drain region arranged on both sides of the channel region, a thin film semiconductor device has a main orientation of at least the channel region of {110} with respect to the surface of the gate insulating film. Further, a polycrystalline semiconductor film having a main orientation of the surface almost perpendicular to a direction for connecting the source and drain regions of {100} is preferably used in the channel of a semiconductor device.

Abstract: In the S3-type semiconductor laser, when an angle of a first growth profile line to the first principal plane, the first growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the first layer of the first conduction type cladding layer is &thgr;1, an angle of a second growth profile line to the first principal plane, the second growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the second layer of the first conduction type cladding layer is &thgr;2, an angle of a third growth profile line to the first principal plane, the third growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the third layer of the first conduction type cladding layer is &thgr;3, and an angle of a fourth growth profile line to the first principal plane, the fourth growth profile line connecting respective lower side lines of an upper inclined plane and

Abstract: A method of forming a silicide region (80) on a Si substrate (10) in the manufacturing of semiconductor integrated devices, a method of forming a semiconductor device (MISFET), and a device having suicide regions formed by the present method. The method of forming a suicide region involves forming a silicide region (80) in the (crystalline) Si substrate having an upper surface (12) and a lower surface (14). The method comprises the steps of first forming an amorphous doped region (40) in the Si substrate at or near the upper surface, to a predetermined depth (d). This results in the formation of an amorphous-crystalline interface (I) between the amorphous doped region and the crystalline Si substrate. The next step is forming a metal layer (60) atop the Si substrate upper surface, in contact with the amorphous doped region. The next step involves performing backside irradiation with a first radiation beam (66).

Abstract: A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

Abstract: The present invention discloses a method for forming metal silicide on an electronic structure by first depositing a metal layer on top of a silicon layer of polysilicon, single crystal silicon or amorphous silicon capable of forming a metal silicide, and then irradiating the metal layer with laser energy for a sufficient length of time such that a layer of metal silicide is formed at the metal interface with polysilicon, single crystal silicon and amorphous silicon. The unreacted metal layer on the metal silicide is then removed by a wet dipping method by selecting a suitable etchant for the metal. The present invention novel method can be applied to various metallic materials such as Ti, Co, W, Pt, Hf, Ta, Mo, Pd and Cr. The laser source utilized is a pulse Excimer laser of XeCl, ArF or XeF.

Abstract: A method of forming a silicide region (80) on a Si substrate (10) in the manufacturing of semiconductor integrated devices, a method of forming a semiconductor device (MISFET), and a device having suicide regions formed by the present method. The method of forming a silicide region involves forming a silicide region (80) in the (crystalline) Si substrate having an upper surface (12) and a lower surface (14). The method comprises the steps of first forming an amorphous doped region (40) in the Si substrate at or near the upper surface, to a predetermined depth (d). This results in the formation of an amorphous-crystalline interface (I) between the amorphous doped region and the crystalline Si substrate. The next step is forming a metal layer (60) atop the Si substrate upper surface, in contact with the amorphous doped region. The next step involves performing backside irradiation with a first radiation beam (66).

Abstract: A structure includes a metal nitride film of the form MN, where M is selected from the group consisting of Ga, In, AlGa, AlIn, and AlGaIn. The structure has at least one electrically conductive metal region that is formed within and from the metal nitride film by a thermal process driven by absorption of light having a predetermined wavelength. Single films comprised of AlN are also within the scope of this invention, wherein an Al trace or interconnect is formed by laser radiation of wavelength 248 nm so as to contact circuitry that exists under the film. Multilayered stacks of films are also within the scope of the teachings of this invention.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A process for planarization of a silicon wafer is described together with apparatus for implementing it. The process planarizes by directing a high-energy, pulsed laser beam in a direction parallel to the wafer surface while the wafer is rotating. The height of the beam relative to the wafer is carefully controlled thereby enabling the removal of all material above the lower edge of the beam to be removed from the wafer through laser ablation. The method works equally well for removal of metal (as in planarization of damascene wiring) or dielectric (as in planarization of conventional wiring). Once all excess material has been removed (typically requiring about 60 seconds) additional operation of the process does no harm so neither end point detection nor precise control of process time are required.

Abstract: A film containing such an element as germanium or tin is formed on a wiring electrode mainly made of aluminum. A wiring film to take contact to the wiring electrode is further formed thereon. The film containing the above element is rendered flowable by performing a heat treatment. This process allows formation of a reliable contact.

Abstract: A semiconductor device includes a fuse constituted by a lower interconnection, an upper metal interconnection, and a plug. The lower interconnection is formed on a semiconductor substrate. The upper metal interconnection is formed on the lower interconnection through interlevel insulating film to have an overlap region that overlaps at least part of the lower interconnection. The plug is formed in the overlap region to electrically connect the upper metal interconnection and the lower interconnection to each other. A method of manufacturing a semiconductor device is also disclosed.

Abstract: A method of repairing or augmenting a metal line buried beneath at least one cover layer comprising the steps of creating a via through the cover layer to the metal line, repairing or augmenting the metal line, and filling the via. Also provided is apparatus for repairing or augmenting a metal line buried beneath at least one cover layer comprising means for creating a via through the cover layer to the metal line, means for repairing or augmenting the metal line, and means for filling the via. Also provided is a substrate having a metal line buried beneath at least one cover layer wherein the metal line has been repaired or augmented according to the process comprising the steps of creating a via through the cover layer to the metal line, repairing or augmenting the metal line, and filling the via.

Abstract: A method and an apparatus for editing an integrated circuit. In one embodiment, an integrated circuit substrate is placed into a laser chemical vapor deposition (LCVD) tool and a conductive metal film is deposited onto the integrated circuit substrate over an area of interest. The integrated circuit substrate is subsequently placed into a focused ion beam (FIB) tool where an optional FIB cleaning step is performed on the conductive element deposited by the LCVD tool to help ensure that a good electrical contact can be made. The FIB tool is also used to introduce any desired cuts into signal lines of the integrated circuit to complete edits. The FIB is also used to remove passivation over integrated circuit nodes of interest to expose buried metal lines for subsequent coupling to the conductive element deposited with the LCVD tool.

Abstract: A method for forming a metal line of a semiconductor device is suitable for forming a conductive material with strong connection force, by irradiating the region between metals to be connected with each other, with laser beams. It comprises the steps of: forming a plurality of metal lines on a substrate; depositing a first conductive material over the substrate including the metal lines; irradiating the first conductive material between the metal lines to be connected, with laser beams, before forming a second conductive material; and removing the first conductive material excluding the second conductive material.

Abstract: This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate.

Abstract: A first metal film and a second metal film, both of which are made of Ni or the like, are deposited on the upper surface of a substrate made of SiC. In such a state, the interface between the first metal film and the substrate and the interface between the second metal film and the substrate both form a Schottky contact. Next, laser light is irradiated from above the upper surface of the substrate only onto the first metal film on the substrate after the diameter of the top end of the laser light has been reduced. Thus, since the metal-semiconductor interface between the first metal film and the substrate is turned into an alloy owing to the energy of the laser light without heating the entire substrate, an ohmic contact can be formed in the interface between the first metal film and the substrate. As a result, an ohmic electrode can be constituted by the first metal film.

Abstract: A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract: A device for forming a deposited film is provided. It comprises (a) a reaction chamber; (b) a heating means for heating a substrate placed in the reaction chamber; (c) a starting gas introducing means for introducing starting gases into the reaction chamber, the gas introducing means having a means for introducing two or more kinds of gases alternately and intermittently into the reaction chamber; (d) a decomposing means for decomposing the starting gases in the reaction chamber so as to form a deposited film on the substrate heated by said heating means in the reaction chamber, the decomposing means having a light source which irradiates at least one kind of light into the reaction chamber to decompose the starting gases.

Abstract: A method of manufacturing a semiconductor device having the steps of: preparing a semiconductor device structure having an interconnection structure including a pair of electrically separated interconnections disposed near each other in one layer and a conductive pattern disposed near the pair of interconnections in the same layer; and applying light having a high intensity sufficient for melting and scattering conductive material of the conductive pattern to the conductive pattern and shorting the pair of interconnections with material formed by melting, scattering, and depositing the conductive material. This method provides a semiconductor device capable of easily connecting separated interconnections formed in the same layer.

Abstract: Stable suicides are formed utilizing excimer laser crystallization in place of a conventional second high temperature rapid thermal processing annealing step. Specifically, thermally unstable silicide having a metal-rich surface layer is conventionally formed utilizing deposition of refractory metal followed by low temperature annealing. After removal of unreacted refractory metal, an amorphous silicon film is deposited on top of the unstable silicide and exposed to radiation from an excimer laser, such that the amorphous silicon melts, reacts with refractory metal from the underlying unstable silicide, and reforms as thermally stable silicide evidencing low electrical resistance.

Abstract: There are disclosed apparatus and method for well performing a reflow step that reduces malfunctions of TFTs due to defective contacts. The apparatus has at least first and second hermetic reaction chambers whose ambients can be controlled independently. These two chambers are connected together hermetically. In the first chamber, a film consisting only or chiefly of aluminum is formed by sputtering. In the second reaction chamber, a heat treatment is performed to impart fluidity to at least a part of the film consisting only or chiefly of aluminum.

Abstract: To produce a high quality thin film by effectively removing the particles from the emitted substance and the oxygen retained under a high vacuum during the production of the thin film by laser ablation, there is provided a process for producing a thin film on a substrate by laser ablation in a vacuum chamber in which a laser beam is irradiated to a target to cause emission of a substance from the target and allowing the emitted substance to deposit on the substrate to grow a thin film on the substrate by laser ablation, the process including irradiating an ion beam to at least one of the substrate and a plume of the emitted substance formed between the substrate and the target.

Abstract: In a method of manufacturing an electronic component for forming a conductor pattern on an insulating substrate by transfer method employing intaglio printing technique, this manufacturing method comprises a step of fabricating an intaglio 20 made of flexible resin forming an insulating layer 23 on a groove 21, a step of filling the groove 21 with Ag paste 24 and drying, a step of overlaying the intaglio 20 on an insulating substrate 2 having a water-soluble resin 28 formed on the surface by pressing a pressing portion 26, freezing, peeling off the intaglio 20 and insulating substrate 2, and transferring the pattern of the Ag paste 24, and a step of firing it and forming a conductor pattern.

Abstract: A method which protects the region between a component and the substrate onto which the components is bonded using an electrically insulating fillet of photoresist. The fillet protects the regions from subsequent plating with metal and therefore shorting the plated conductors which run down the sides of the component and onto the substrate.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A laser-annealing method includes the steps of a first step of cleaning a non-monocrystal silicon film formed on a substrate, and a second step of laser-annealing the non-monocrystal silicon film in an atmosphere containing oxygen therein, wherein the first and second steps are conducted continuously without being exposed to the air. Also, a laser-annealing device includes a cleaning chamber, and a laser irradiation chamber, wherein a substrate to be processed is transported between the cleaning chamber and the laser irradiation chamber without being exposed to the air.

Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

Abstract: A semiconductor chip mounting method consisting of steps is performed to mount a semiconductor chip on a substrate. Herein, an electrode is formed on a main surface of the semiconductor chip and is covered with an insulating film. A contact hole is formed through the insulating film to be in contact with a part of the electrode. In addition, a Ni layer is formed to cover the contact hole. A wiring layer is formed on a main surface of the substrate and is covered with an insulating film. To achieve laser beam bonding effected between the semiconductor chip and substrate, a solder is provided for either the semiconductor chip or the substrate. For example, it is possible to provide a solder layer which is formed through a part of the insulating film to be in contact with the wiring layer of the substrate; or it is possible to provide a solder bump which projects from a concavity of the Ni layer of the semiconductor chip.

Abstract: A method for providing a lateral conductive link between conductive elements, e.g., metals, placed on a first non-conductive material, wherein a second non-conductive material is placed on said first non-conductive material to form an interface therebetween in a region between the conductive elements. Energy is applied to the conductive elements to produce mechanical strains by thermal expansion in the conductive elements which initiate a rupturing of the interface between the non-conductive materials so as to provide at least one fissure therein extending between the conductive elements. The energy applied causes a portion of at least one of the conductive elements to flow in such fissure to provide a lateral conductive link between the conductive elements.

Abstract: A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: Conductive links are provided between conductive materials, e.g., metals, separated by a non-conductive material, e.g., a silicon-based glass material. In a preferred embodiment, a single pulse of laser energy is applied to at least one of the conductive materials to produce mechanical strain therein which strain initiates a fracturing of the non-conductive material so as to provide at least one fissure therein extending between the conductive materials. The laser energy pulse further causes at least one of the conductive materials to flow in such fissure to provide a conductive link between the conductive materials. Preferably, the non-conductive material is formed in layers such that an interface between the layers controls the fissures.

Abstract: Light emitting diodes with highly reflective contacts and methods for fabricating them are described. In a first preferred embodiment of the present invention, LEDs with reflective contacts are formed using a laser to create small alloyed dots in a highly reflective metal evaporated on the top and bottom surface of the LED chip. Using this technique, most of the bottom surface remains highly reflective, and only those portions of the bottom surface where the laser struck become absorbing. Typically, only 1% of the bottom surface is formed into contacts, leaving 99% of the bottom surface to serve as a reflecting surface. The 1% of the surface, however, provides an adequate low resistance ohmic contact. LEDs fabricated with this technique allow photons to bounce off the rear surface more than 20 times before there is a 50% chance of absorption.

Abstract: A fluxless method for fusing preformed solder balls to contact pads on a semiconductor package substrate wherein a masking plate having one or more vertical holes corresponding to the contact pads is placed over the package substrate, oxide-free solder balls are placed in the holes, the assembly is preheated to a temperature less than the melting point of the solder, and an energetic beam is directed onto the preformed solder balls to melt them and fuse them to the contact pads.

Abstract: The method of this invention produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes the steps of producing an amorphous region on the silicon body using ion implantation, for example, forming or positioning a metal such as titanium, cobalt or nickel in contact with the amorphous region, and irradiating the metal with intense light from a laser source, for example, to cause metal atoms to diffuse into the amorphous region. The amorphous region thus becomes an alloy region with the desired silicide composition. Upon cooling after irradiation, the alloy region becomes partially crystalline. To convert the alloy region into a more crystalline form, the invented method preferably includes a step of treating the alloy region using rapid thermal annealing, for example.