Assembly Of Plural Semiconductor Substrates Patents (Class 438/67)
  • Patent number: 11600741
    Abstract: The present disclosure provides a support device for conveying at least one solar cell element in a transport direction, wherein the support device comprises a support element configured for supporting the at least one solar cell element and an electric arrangement configured for providing an electrostatic force for holding the at least one solar cell element on the support element.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 7, 2023
    Assignee: APPLIED MATERIALS ITALIA S.R.L.
    Inventors: Daniele Gislon, Luigi De Santi, Thomas Micheletti, Andrea Baccini, Mirko Galassi, Roberto Boscheratto
  • Patent number: 11139403
    Abstract: A high efficiency configuration for a solar cell module comprises solar cells arranged in an overlapping shingled manner and conductively bonded to each other in their overlapping regions to form super cells, which may be arranged to efficiently use the area of the solar module.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: October 5, 2021
    Assignee: SunPower Corporation
    Inventors: Yafu Lin, Benjamin Francois
  • Patent number: 11049799
    Abstract: A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 29, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Fong Lin, Shin-Cheng Lin, Cheng-Wei Chou, Yu-Chieh Chou
  • Patent number: 11043608
    Abstract: The present disclosure relates to a method and apparatus for manufacturing a semiconductor sheet assembly. The method for manufacturing a semiconductor sheet assembly includes positioning a semiconductor sheet, and determining a first region to be grooved and a defect position in the first region; cutting and grooving the semiconductor sheet along the defect position in the first region; and splitting the semiconductor sheet that is cut and grooved.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 22, 2021
    Assignees: ZHEJIANG JINKO SOLAR CO., LTD., JINKO SOLAR CO., LTD.
    Inventors: Luchuang Wang, Wusong Tao, Zhiqiu Guo, Yang Bai, Xueming Zhang
  • Patent number: 10923611
    Abstract: A radio frequency transparent photovoltaic cell includes a back contact layer formed of an electrically conductive material, at least one aperture formed in the back contact layer, and at least one photovoltaic cell section disposed on the back contact layer. An airship includes one or more radio frequency antennas disposed in an interior of the airship. One or more radio frequency transparent photovoltaic cells are disposed on an outer surface of the airship.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 16, 2021
    Assignee: Raytheon Company
    Inventors: Daniel F. Sievenpiper, Michael Wechsberg, Fangchou Yang
  • Patent number: 10886394
    Abstract: A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed on the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and on the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 5, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shin-Cheng Lin, Wen-Hsin Lin, Marojahan Tampubolon
  • Patent number: 10861899
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Patent number: 10818500
    Abstract: The invention aims for a wafer edge trimming method 1 adhered on a support wafer 2 by way of an interface layer 3. A zone at the perimeter 12 of the wafer 1 is trimmed by grinding. The stopping of the grinding is advantageously done at the level of the interface layer 3. To do this, an interface layer 3 comprising a transition layer 4 having a resistance to grinding greater than that of the wafer 1 is used. According to a possibility, detecting an increase of the resistance to grinding during the grinding is done, so as to stop the grinding.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 27, 2020
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Franck Fournel, Christophe Morales, Marc Zussy
  • Patent number: 10672938
    Abstract: A cleaving system and method are described. The system can include a holding apparatus to retain a photovoltaic structure at a center section of a cleaving platform. The system can further include a contact apparatus to make contact with the photovoltaic structure and separate it into a plurality of strips. During operation, the system can activate an actuator to move the contact apparatus against the photovoltaic structure, thereby separating the photovoltaic structure into strips.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 2, 2020
    Assignee: SolarCity Corporation
    Inventors: Pablo Gonzalez, Bobby Yang
  • Patent number: 10581004
    Abstract: A structure of photovoltaic cell is provided. The structure of photovoltaic cell includes a substrate, a lower conductive layer, a photovoltaic layer, and an upper conductive layer, the lower conductive layer is disposed at one side of the substrate, the photovoltaic layer is disposed at the other surface of the lower conductive layer, and the upper conductive layer is disposed on the other surface of the photovoltaic layer. An electron transporting layer, a hole transporting layer, and an active layer sandwiched between the electron transporting layer and the hole transporting layer collectively constitute the photovoltaic layer. The electron transporting layer convers a portion of the active layer and the hole transporting layer for blocking the upper conductive layer from electrically connecting to the active layer and the hole transporting layer.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 3, 2020
    Assignee: NANOBIT TECH. CO., LTD.
    Inventors: Ding-Kuo Ding, Yu-Yang Chang, Shiou-Ming Liu, Sung-Chien Huang
  • Patent number: 10535706
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Patent number: 10157959
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING, COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Patent number: 9966401
    Abstract: A semiconductor package according to the inventive concepts includes an image sensor chip mounted on a substrate, a first holder disposed on an edge area of the image sensor chip, a second holder disposed laterally spaced apart from the image sensor chip on an edge area of the substrate, a molding part provided in a gap region between the first holder and the second holder on the substrate, and a transparent cover disposed on the first holder and the molding part.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyunsu Jun
  • Patent number: 9887222
    Abstract: A method of manufacturing an optical apparatus is provided. The method includes arranging a photo device above a substrate with an adhesive located between the photo device and the substrate, forming a bonding member that bonds the substrate and the photo device by curing the adhesive, and arranging, above the photo device, a transparent plate and a sealing member. The sealing member covers the photo device and is located between the transparent plate and the substrate. An elastic modulus of the bonding member is 1 GPa or less.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 6, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takashi Miyake
  • Patent number: 9564544
    Abstract: A solar cell production method, whereby: a plurality of solar cell strings connecting a prescribed number of solar cells in series are formed; a plurality of solar cell strings are lined up along a second direction intersecting a first direction in which the solar cell strings extend, and the same are arranged such that the interval at one end of the first direction between adjacent solar cell strings is smaller than the interval at the other end; the arranged plurality of solar cell strings are connected to each other and a solar cell connection body is formed; a first filling material sheet, the solar cell connection body, a second filling material sheet, and a second protective member are laminated upon a first protective member having a curved surface; pressure is applied from above the second protective member; and a solar cell module having a curved surface shape is formed.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 7, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yosuke Ishii, Yuki Oikawa, Satoshi Suzuki
  • Patent number: 9368656
    Abstract: The invention relates to a photovoltaic cell, comprising a plate shaped substrate of a semiconductor material with a solar face and a connection face, a first volume of the substrate adjacent to the solar face is doped with a first polarity, the second volume is doped with a second polarity and the volumes are separated by a pn-junction, a number of apertures in the substrate extending between both faces and in which a plug has been positioned of which a part is conducting, contact tracks at the solar face of the substrate connected with the first volume and the conducting part of the plug, first contacts at the connection face of the substrate connected with the conducting part of the plug and second contacts located at the connection face of the substrate connected with the second volume, wherein the specific electrical conductivity of the plug decreases from its centre to the contact face with the substrate.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: June 14, 2016
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventors: Menno Nicolaas Van Den Donker, Peter Andreas Maria Wijnen
  • Patent number: 9349894
    Abstract: A solar cell includes an integrated structure. The integrated structure includes a first electrode layer, a P-type silicon layer, an N-type silicon layer, and a second electrode layer arranged in the above sequence. At least one curved surface is defined on the integrated structure. The integrated structure includes a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer; and a photoreceptive surface exposing the P-N junction. The photoreceptive surface is one the at least one curved surface of the integrated structure and is configured to receive incident light beams.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: May 24, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 9349890
    Abstract: A solar cell includes an integrated structure and a reflector. The integrated structure includes a first electrode layer, a P-type silicon layer, an N-type silicon layer, and a second electrode layer arranged in the above sequence; a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer; a photoreceptive surface exposing the P-N junction. The photoreceptive surface is on a curved surface of the integrated structure and is configured to receive incident light beams. The reflector is on another side of the integrated structure, opposite to the photoreceptive surface.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 24, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 9048161
    Abstract: A method for fabricating a sensor includes: forming, on a base substrate, a pattern of a source electrode and a drain electrode, a pattern of a data line, a pattern of a receiving electrode, a pattern of a photodiode, and a pattern of a transparent electrode disposed by using a first patterning process; forming a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer by using a third patterning process; forming a pattern of a gate insulating layer by using a fourth patterning process, wherein the gate insulating layer has a via hole above the transparent electrode; and forming a pattern of a gate electrode, a pattern of a gate line, and a pattern of a bias line connected to the transparent electrode via the via hole above the transparent electrode by using a fifth patterning process.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 2, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shaoying Xu, Zhenyu Xie, Xu Chen
  • Publication number: 20150144175
    Abstract: A photovoltaic module has cells each having at least one collecting finger (2) oriented in a first elongation direction (D1) and at least one bus (3) oriented in a second elongation direction (D2) making at an angle to the first. At a zone (4) of electrical connection between the bus (3) and the collecting finger (2), the bus has at least one local enlargement (Le) of its width (Lb) along the first direction (D1). The ratio of the length (We) in the second direction (D2) of the local enlargement (Le) of the width (Lb) of the bus (3) to the width (Wd) of the corresponding collecting finger (2) in the second direction (D2) is strictly higher than one. The total width (Lt) of the bus at a local enlargement (Le) is strictly larger than the width (Lr) along the first direction of a metal strip (5) that electrically connects the cells.
    Type: Application
    Filed: May 17, 2013
    Publication date: May 28, 2015
    Inventor: Armand Bettinelli
  • Publication number: 20150118784
    Abstract: A method for bonding a first semiconductor body having a plurality of electromagnetic radiation detectors to a second semiconductor body having read out integrated circuits for the detectors. The method includes: aligning electrical contacts for the plurality of electromagnetic radiation detectors with electrical contacts of the read out integrated circuits; tacking the aligned electrical contacts for the plurality of electromagnetic radiation detectors with electrical contacts of the read out integrated circuits to form an intermediate stage structure; packaging the intermediate stage structure into a vacuum sealed electrostatic shielding container having flexible walls; inserting the package with the intermediate stage structure therein into an isostatic pressure chamber; and applying the isostatic pressure to the intermediate stage structure through walls of the container. The container includes a stand-off to space walls of the container from edges of the first semiconductor body.
    Type: Application
    Filed: December 2, 2013
    Publication date: April 30, 2015
    Applicant: Raytheon Company
    Inventors: Kenneth Allen Gerber, Jonathan Getty, Aaron M. Ramirez, Scott S. Miller
  • Patent number: 9018726
    Abstract: The photodiode has a p-type doped region (2) and an n-type doped region (3) in a semiconductor body (1), and a pn junction (4) between the p-type doped region and the n-type doped region. The semiconductor body has a cavity (5) such that the pn junction (4) has a distance (d) of at most 30 ?m from the bottom of the cavity (7).
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: April 28, 2015
    Assignee: ams AG
    Inventors: Jochen Kraft, Ingrid Jonak-Auer, Rainer Minixhofer, Jordi Teva, Herbert Truppe
  • Publication number: 20150107653
    Abstract: An article of manufacture (400) includes a number of photovoltaic cells (102) forming a photovoltaic (PV) module circuit, with a first bus bar (106) electrically coupled to one extremity of the PV module circuit and a second bus (206) bar electrically coupled to a second extremity of the PV module. The bus bars (106, 206) are positioned on an opposing side of the PV cells (104, 204) from a light incident side of the PV cells.
    Type: Application
    Filed: May 29, 2013
    Publication date: April 23, 2015
    Inventors: Abhijit Namjoshi, Marty Degroot, Leonardo Lopez, Rebekah Feist, Lindsey Clark
  • Publication number: 20150102447
    Abstract: A method for producing at least one photosensitive infrared detector by assembling a first electronic component including plural photodiodes sensitive to infrared radiation and a second electronic component including at least one electronic circuit for reading the plurality of photodiodes, an infrared detector, and an assembly for producing such a detector, the method including: production, on each one of the first and second components, of a connection face formed at least partially by a silicon oxide (SiO2)-based layer; bonding the first component and the second component by the connection faces thereof, thus performing the direct bonding of the two components. The method can simplify hybridization of heterogeneous components for producing an infrared detector.
    Type: Application
    Filed: May 6, 2013
    Publication date: April 16, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Stephanie Huet, Abdenacer Ait-Mani, Lea Di Cioccio
  • Publication number: 20150091113
    Abstract: This invention relates to a direct conversion X-ray sensor and to a method of manufacturing the same. This X-ray sensor includes an array substrate including a pixel electrode formed so as to protrude from a surface thereof at a pixel region; a photoconductive substrate including an upper electrode, and a photoconductive layer formed on a surface of the upper electrode so as to be in contact with the pixel electrode and having a PIN diode structure; and a bonding material filling a space around a contact region of the pixel electrode and the photoconductive layer so as to bond the array substrate and the photoconductive substrate.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 2, 2015
    Inventors: Sung Kyn HEO, Ho Seok LEE
  • Patent number: 8993366
    Abstract: The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 31, 2015
    Assignee: MicroLink Devices, Inc.
    Inventors: Raymond Chan, Haruki Miyamoto
  • Patent number: 8987036
    Abstract: A solar battery module (40) includes a stack of: a plurality of solar battery strings (30) and bus sections (32) connected to both ends of each of the plurality of solar battery strings (30); flexible resin layers (33a through 33c); and a flexible resin film (34). The flexible resin layers (33a through 33c) and the flexible resin film (34) have, on a light receiving surface side of solar battery cells (20), holes through which the bus sections (32) are each partially exposed. The exposed parts of the bus sections (32) serve as a respective plurality of electrically-connecting means (32a). A solar battery array (41) includes a plurality of solar battery modules (40). The plurality of solar battery modules (40) are electrically connected with each other via the plurality of electrically-connecting means (32a). This makes it possible to achieve a large-scale solar battery array (41) with high mechanical strength.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Naoki Takahashi
  • Patent number: 8980673
    Abstract: Provided are a solar cell and a method of manufacturing the same. The method of manufacturing the solar cell includes stacking a solar cell device layer containing GaN on a sacrificial substrate, etching the solar cell device layer to expose the sacrificial substrate, thereby forming one or more solar cell devices comprising the solar cell device layer, anisotropically etching the exposed sacrificial substrate, contacting the solar cell devices to a stamping processor to remove the solar cell devices from the sacrificial substrate, and transferring the solar cell devices onto a receiving substrate. A high temperature semiconductor process may be performed on a substrate such as a silicon substrate to transfer the solar cell devices onto the substrate, thereby manufacturing flexible solar cells. Also, a large number of solar cells may be excellently aligned on a large area. In addition, economical solar cells may be manufactured.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 17, 2015
    Assignees: LG Siltron Incorporated, Korea Advanced Institute of Science
    Inventors: Keon Jae Lee, Sang Yong Lee, Seung Jun Kim
  • Patent number: 8975105
    Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 10, 2015
    Assignee: Raytheon Company
    Inventor: Cody B. Moody
  • Publication number: 20150059830
    Abstract: A photovoltaic device and method of manufacture of a photovoltaic device including an assembly of at least two photovoltaic cells; and a lamination material inserted between each photovoltaic cell, each photovoltaic cell including: two current output terminals; at least one photovoltaic junction; current collection buses; and connection strips extending from the current collection buses to the current output terminals, all the current output terminals being placed on a single surface of the photovoltaic device is provided.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 5, 2015
    Inventors: Marc VERMEERSCH, Loic FRANCKE
  • Publication number: 20150054110
    Abstract: Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventor: Keiichiro KASHIHARA
  • Publication number: 20150054107
    Abstract: A method of manufacturing an optical apparatus is provided. The method includes arranging a photo device above a substrate with an adhesive located between the photo device and the substrate, forming a bonding member that bonds the substrate and the photo device by curing the adhesive, and arranging, above the photo device, a transparent plate and a sealing member. The sealing member covers the photo device and is located between the transparent plate and the substrate. An elastic modulus of the bonding member is 1 GPa or less.
    Type: Application
    Filed: July 28, 2014
    Publication date: February 26, 2015
    Inventor: Takashi Miyake
  • Publication number: 20150053248
    Abstract: A solar cell module includes serially connected solar cells. A solar cell includes a carrier that is attached to the backside of the solar cell. Solar cells are attached to a top cover, and vias are formed through the carriers of the solar cells. A solar cell is electrically connected to an adjacent solar cell in the solar cell module with metal connections in the vias.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: SunPower Corporation
    Inventors: Seung RIM, Sung Dug KIM
  • Patent number: 8951824
    Abstract: Provided are novel methods of fabricating photovoltaic modules using pressure sensitive adhesives (PSA) to secure wire networks of interconnect assemblies to one or both surfaces of photovoltaic cells. A PSA having suitable characteristics is provided near the interface between the wire network and the cell's surface. It may be provided together as part of the interconnect assembly or as a separate component. The interconnect assembly may also include a liner, which may remain as a part of the module or may be removed later. The PSA may be distributed in a void-free manner by applying some heat and/or pressure. The PSA may then be cured by, for example, exposing it to UV radiation to increase its mechanical stability at high temperatures, in particular at a, for example the maximum, operating temperature of the photovoltaic module. For example, the modulus of the PSA may be substantially increased during this curing operation.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: February 10, 2015
    Assignee: Apollo Precision (Fujian) Limited
    Inventor: Todd Krajewski
  • Publication number: 20150027513
    Abstract: A semiconductor substrate and a photovoltaic power module incorporating the semiconductor substrate. The substrate includes one or more bypass diodes formed integrally in the semiconductor substrate, each bypass diode corresponding to a respective one or more photovoltaic cells, and metallised zones being electrically and thermally coupled to the bypass diodes. The substrate enables photovoltaic cells to be placed close together, and has low thermal resistance. Methods of manufacturing the substrate and module are provided.
    Type: Application
    Filed: November 21, 2012
    Publication date: January 29, 2015
    Applicant: Solar Systems Pty Ltd
    Inventors: William Ring, Joel Goodrich, Zhen Mu, Robert Musk
  • Publication number: 20150031162
    Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Mineo Shimotsusa, Takeshi Ichikawa, Yasuhiro Sekine
  • Patent number: 8940616
    Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Huamao Lin, Pradeep Yelehanka
  • Publication number: 20150011039
    Abstract: A solar cell module is manufactured by forming silicone coating films (2, 2) on panels (1a, 1b), placing a solar cell matrix (3) on the silicone coating film on panel (1a), providing a seal member (4) consisting of a base seal member (4a) of butyl rubber and protrusive seal segments (4b) of butyl rubber on a peripheral region of panel (1a), mating the two panels together such that the seal member (4) may abut against a peripheral region of panel (1b), and the solar cell matrix (3) may be sandwiched between the silicone coating films (2), and compressing and heating the mated panels (1a, 1b) in vacuum for establishing a seal around the solar cell matrix (3).
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tomoyoshi Furihata, Hiroto Ohwada, Naoki Yamakawa, Masahiro Hinata
  • Publication number: 20150004741
    Abstract: A wafer separation apparatus improves wafer separation performance in separation and transfer and suppresses the occurrence of wafer breakage in separation and transfer, while remaining inexpensive and small. The apparatus includes: a cassette that vertically accommodates a large number of single wafers in intimate contact with each other, the cassette being at least vertically opened; a cassette support that removably supports the cassette, the cassette support being at least vertically opened; a hoisting unit that hoists and lowers the cassette support integrally with the cassette; a liquid bath that accommodates a liquid into which the cassette support is immersed integrally with the cassette when the hoisting unit descends; a nozzle in the inside of the liquid bath to issue micro bubbles from the underside of the cassette support toward a large number of the wafers; and a micro bubble generator that generates micro bubbles to be issued from the nozzle.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Ichiki KUSUHARA, Kyouhei TSUNASHIMA
  • Publication number: 20150000724
    Abstract: An adhesive may be applied to a surface of a reusable carrier. Metal foil may be attached to the adhesive to couple the metal foil to the surface of the reusable carrier. The metal foil may be patterned without damaging the reusable carrier. A semiconductor structure (e.g., a solar cell) may be attached to the patterned metal foil. The reusable carrier may then be removed. In some embodiments, the semiconductor structure may be encapsulated using an encapsulant, with the adhesive being compatible with the encapsulant.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Thomas PASS, Richard SEWELL, Taeseok KIM, Gabriel HARLEY, David F.J. KAVULAK, Xiuwen TU
  • Publication number: 20140373905
    Abstract: A multijunction solar cell including an upper first solar subcell; a second solar subcell adjacent to the first solar subcell; a first graded interlayer adjacent to the second solar subcell; a third solar subcell adjacent to the first graded interlayer such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell, and a lower fourth solar subcell is provided adjacent to the second graded interlayer, such that the fourth subcell is lattice mismatched with respect to the third subcell. An encapsulating layer composed of silicon nitride or titanium oxide disposed on the top surface of the solar cell, and an antireflection coating layer disposed over the encapsulating layer.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Applicant: Emcore Solar Power, Inc.
    Inventor: Arthur Cornfeld
  • Publication number: 20140373897
    Abstract: This solar cell module is provided with: a plurality of solar cells; and a tab, which electrically connects the solar cells, and which has recesses and projections on the surface thereof. The tab has height of the recesses and the projections smaller in the peripheral region of each of the solar cells, compared with that in other regions of each of the solar cells.
    Type: Application
    Filed: September 12, 2014
    Publication date: December 25, 2014
    Inventors: Yukihiro YOSHIMINE, Tasuku ISHIGURO, Naoto IMADA
  • Publication number: 20140360563
    Abstract: An improved method for interconnecting thin film solar cells to form solar cell modules is provided, the method comprising using a flat metallic mesh formed from a thin metallic strip to provide a current collection grid over a thin film solar cell. The method is particularly useful for forming interconnections between thin film solar cells deposited on flexible substrates. The rectangular cross sectional shape of the mesh elements provides an increased area of electrical contact to the solar cell compared to the small tangential area provided by elements of circular cross section. Mesh elements can be made higher rather than wider to improve conductivity without proportionally increasing shading loss. Various coatings can be applied to the mesh to improve its performance, provide corrosion resistance, and improve its cosmetic appearance.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 11, 2014
    Inventors: David B. Pearce, Bruce D. Hachtmann, Liguang Gong, Thomas M. Valeri, Dennis R. Hollars
  • Publication number: 20140360554
    Abstract: The present invention is premised upon a method of producing two or more thin-film-based interconnected photovoltaic cells comprising the steps of: a) providing a photovoltaic article comprising: a flexible conductive substrate, at least on photo-electrically active layer, a top transparent conducting layer, and a carrier structure disposed above the tap transparent layer; b) forming one or more first channels through the layers of the photovoltaic article; c) applying an insulating layer to the conductive substrate and spanning the one or more first channel; d) removing the carrier structure; e) forming an addition to the one or more first channels through the insulating layer; f) forming one or more second channels off set from the one or mom first channels through the insulating layer to expose a conductive surface of the flexible conductive substrate; g) applying a first electrically conductive material to the conductive surface of the flexible conductive substrate via the one or more; second channels; h)
    Type: Application
    Filed: December 11, 2012
    Publication date: December 11, 2014
    Inventors: Rebekah K. Feist, Michael E. Mills
  • Publication number: 20140312450
    Abstract: A method and structure of an image sensor device including a read out integrated circuit (ROIC) and a photodiode array (PDA). An embodiment may include a package substrate having a recess and a raised pedestal within the recess; a read out integrated circuit (ROIC) physically attached to the raised pedestal; a photodiode array (PDA) physically attached to the ROIC and electrically coupled therewith; and a printed circuit board (PCB) within the recess in the package substrate, wherein the PCB has an opening therein and the raised pedestal at least partially extends through the opening in the PCB.
    Type: Application
    Filed: March 6, 2014
    Publication date: October 23, 2014
    Applicant: Sensors Unlimited, Inc.
    Inventors: John Tagle, Dmitry Zhilinsky, Michael Liland, JR.
  • Patent number: 8865506
    Abstract: A method for fabricating a solar cell commences by bonding a first metal-coated substrate to a second metal-coated substrate to provide a bonded substrate. The bonded substrate is then coated with a first precursor solution to provide a coated bonded substrate. Finally, the procedure de-bonds the coated bonded substrate to provide a first solar cell device and a second solar cell device. A system for fabricating the solar cell comprises a first precursor solution deposition system containing a first precursor solution for deposition on a substrate, a first heating element for heating the substrate after deposition of the first precursor solution, a second precursor solution deposition system containing a second precursor solution for deposition on the substrate, and a second heating element for heating the substrate after deposition of the second precursor solution.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: October 21, 2014
    Assignee: Magnolia Solar, Inc.
    Inventors: Gopal G. Pethuraja, Roger E. Welser, Ashok K. Sood
  • Patent number: 8866199
    Abstract: An object of the present invention is to provide a group III-V compound semiconductor photo detector comprising an absorption layer having a group III-V compound semiconductor layer containing Sb as a group V constituent element, and an n-type InP window layer, resulting in reduced dark current. The InP layer 23 grown on the absorption layer 23 contains antimony as impurity, due to the memory effect with antimony which is supplied during the growth of a GaAsSb layer of the absorption layer 21. In the group III-V compound semiconductor photo detector 11, the InP layer 23 contains antimony as impurity and is doped with silicon as n-type dopant. Although antimony impurities in the InP layer 23 generate holes, the silicon contained in the InP layer 23 compensates for the generated carriers. As a result, the second portion 23d of the InP layer 23 has sufficient n-type conductivity.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Youichi Nagai
  • Patent number: 8865507
    Abstract: Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 21, 2014
    Assignee: SiOnyx, Inc.
    Inventors: Homayoon Haddad, Leonard Forbes
  • Publication number: 20140305492
    Abstract: A solar module is described. The solar module has a laminated composite of two substrates bonded to one another by at least one bonding layer, between which substrates there are solar cells which are connected in series and which each have an absorber zone made of a semiconducting material between a front electrode arranged on a light entrance side of the absorber zone and a rear electrode. A diffusion barrier differing from the front electrode is located between each absorber zone and the bonding layer and is designed to inhibit the diffusion of water molecules from the bonding layer into the absorber zone and/or the diffusion of dopant ions from the absorber zone into the bonding layer. A process for producing such a solar module is also described.
    Type: Application
    Filed: August 1, 2012
    Publication date: October 16, 2014
    Inventors: Arnaud Verger, Fabien Lienhart, Paul Mogensen, Walter Stetter, Alejandro Avellan
  • Publication number: 20140301534
    Abstract: Improved imaging systems are disclosed. More particularly, the present disclosure provides for an improved image sensor assembly for an imaging system, the image sensor assembly having an integrated photodetector array and its associated data acquisition electronics fabricated on the same substrate. By integrating the electronics on the same substrate as the photodetector array, this thereby reduces fabrications costs, and reduces interconnect complexity. Since both the photodiode contacts and the associated electronics are on the same substrate/plane, this thereby substantially eliminates certain expensive/time-consuming processing techniques. Moreover, the co-location of the electronics next to or proximal to the photodetector array provides for a much finer resolution detector assembly since the interconnect bottleneck between the electronics and the photodetector array is substantially eliminated/reduced.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 9, 2014
    Applicant: General Electric Company
    Inventors: Naresh Kesavan Rao, James Wilson Rose, Christopher David Unger, Abdelaziz Ikhlef, Jonathan David Short