Assembly Of Plural Semiconductor Substrates Patents (Class 438/67)
-
Publication number: 20090000114Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: ApplicationFiled: December 7, 2007Publication date: January 1, 2009Applicant: RF MICRO DEVICES, INC.Inventors: Jayanti Jaganatha Rao, Thomas Scott Morris, Milind Shah
-
Patent number: 7452745Abstract: A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding the first and second wafers to form a structure comprising successively the circuit layer, the field isolation layer and the photosensitive layer; and forming electrically conductive vias to electrically connect the photosensitive layer to at least some of the electronic components of the circuit layer. Also, photodetecting devices prepared by these methods.Type: GrantFiled: August 24, 2006Date of Patent: November 18, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Frédéric Dupont, Ian Cayrefourcq
-
Publication number: 20080245409Abstract: A method of manufacturing a solar cell on a flexible film by providing a substrate; depositing on the substrate a sequence of layers of semiconductor material forming a solar cell; mounting the semiconductor substrate on a flexible film; and thinning the semiconductor substrate to a predetermined thickness. The sequence of layers forms an inverted metamorphic solar cell structure.Type: ApplicationFiled: December 27, 2006Publication date: October 9, 2008Applicant: EMCORE CorporationInventors: Tansen Varghese, Arthur Cornfeld, Michelle Xie
-
Publication number: 20080179700Abstract: A lateral photodiode, with improved response speed, includes a semiconductor substrate having active regions, and a p-type region and an n-type region arranged parallel to the surface of the substrate. The active regions are an n-layer and a p-layer respectively, and stacked in the thickness direction of the substrate to form a p-n junction. In addition, a barrier layer, for preventing movement of carriers from the substrate toward the active region, is provided on the side of the active regions toward the substrate.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicants: FUJIFILM Corporation, Massachusetts Institute of TechnologyInventors: Yukiya Miyachi, Wojciech P. Giziewicz, Jurgen Michel, Lionel C. Kimerling
-
Patent number: 7405487Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a microelectronic substrate by directing a source of laser radiation toward the encapsulating material. The method can further include exposing a surface of the microelectronic substrate, for example, to enhance a rate at which heat is transferred away from the microelectronic substrate. Alternatively, the encapsulating material can be removed to form heat transfer structures, such as pins or ribs, also to enhance a rate at which heat is transferred away from the microelectronic substrate. In still another embodiment, a portion of the encapsulating material or a support member to which the substrate is attached can be removed to define interlocking features that allow one microelectronic substrate package to be stacked on another and to resist relative movement between the two packages.Type: GrantFiled: August 12, 2002Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventor: Joseph M. Brand
-
Patent number: 7374962Abstract: The contrast offered by a spatial light modulator device may be enhanced by positioning nonreflective elements such as supporting posts and moveable hinges, behind the reflecting surface of the pixel. In accordance with one embodiment, the reflecting surface is suspended over and underlying hinge-containing layer by integral ribs of the reflecting material defined by gaps in a sacrificial layer. In accordance with an alternative embodiment, the reflecting surface is separated from the underlying hinge by a gap formed in an intervening layer, such as oxide. In either embodiment, walls separating adjacent pixel regions may be recessed beneath the reflecting surface to further reduce unwanted scattering of incident light and thereby enhance contrast.Type: GrantFiled: September 29, 2005Date of Patent: May 20, 2008Assignee: Miradia Inc.Inventors: Kegang Huang, Xiao Yang, Dongmin Chen
-
Patent number: 7358109Abstract: A package for a surface-emitting laser encloses the die between a sub-mount and a cap. The sub-mount and the cap can be formed using wafer processing techniques that permit a wafer level packaging process which attaches multiple die to a sub-mount wafer, attaches caps either separated or as part of a cap wafer to the sub-mount wafer, and cuts the structure to separate individual packages. The cap includes a transparent plate that can be processed to incorporate an optical element such as a lens. An alignment post attached to the cap indicates the position of an optical signal from the laser and fits snugly into one end of a sleeve while an optical fiber connector fits into the other end.Type: GrantFiled: November 18, 2004Date of Patent: April 15, 2008Inventors: Kendra Gallup, Brenton A. Baugh, Robert E. Wilson, James A. Matthews, James H. Williams, Tak Kui Wang
-
Patent number: 7338884Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.Type: GrantFiled: November 29, 2004Date of Patent: March 4, 2008Assignee: NEC CorporationInventors: Tadanori Shimoto, Katsumi Kikuchi, Koji Matsui, Kazuhiro Baba
-
Patent number: 7326590Abstract: A method for manufacturing a ball grid array package includes the steps of providing a substrate strip having a plurality of sub-substrate strips wherein each has an upper surface and a lower surface, disposing a plurality of chips on the upper surfaces of the sub-substrate strips, forming a plurality of encapsulation bodies for encapsulating the chips on the upper surfaces respectively, and forming a plurality of ribs between the encapsulation bodies.Type: GrantFiled: October 28, 2004Date of Patent: February 5, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Sheng-Tsung Liu
-
Patent number: 7303976Abstract: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.Type: GrantFiled: May 10, 2005Date of Patent: December 4, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Kirby Sand
-
Patent number: 7285439Abstract: A shielding case bank has shielding cases that arranged at a pitch twice as large as a pitch of molded articles in a molded article bank. Two shielding case banks are stacked one on the other with displacement from each other by half the pitch so that the shielding cases are as a whole arranged as the same pitch as the molded articles. The stacked shielding case banks are mounted on the molded article bank so that each shielding case covers a front face, both side faces, and a top face of the corresponding molded article. Each molded article and the corresponding shielding case are fixed to each other, and a back face of each molded article is covered. After that, guide frames of the shielding case banks are sequentially separated from the shielding cases, and the molded article bank is divided into discrete molded articles.Type: GrantFiled: October 28, 2004Date of Patent: October 23, 2007Assignee: Sharp Kabushiki KaishaInventor: Hiroshi Yoshida
-
Patent number: 7285434Abstract: A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.Type: GrantFiled: March 9, 2005Date of Patent: October 23, 2007Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kuo Chung Yee, Chun Chi Lee
-
Publication number: 20070164386Abstract: A semiconductor device and the fabrication method thereof are provided.Type: ApplicationFiled: December 28, 2006Publication date: July 19, 2007Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Yi Chang, Chien-Ping Huang, Yu-Po Wang, Chih-Ming Huang, Cheng-Hsu Hsiao
-
Patent number: 7238878Abstract: A photovoltaic module comprises electrically interconnected and mutually spaced photovoltaic cells that are encapsulated by a light-transmitting encapsulant between a light-transparent front cover and a back cover, with the back cover sheet being an ionomer/nylon alloy embossed with V-shaped grooves running in at least two directions and coated with a light reflecting medium so as to provide light-reflecting facets that are aligned with the spaces between adjacent cells and oriented so as to reflect light falling in those spaces back toward said transparent front cover for further internal reflection onto the solar cells, whereby substantially all of the reflected light will be internally reflected from said cover sheet back to the photovoltaic cells, thereby increasing the current output of the module. The internal reflector improves power output by as much as 67%.Type: GrantFiled: June 10, 2003Date of Patent: July 3, 2007Inventor: Ronald C. Gonsiorawski
-
Patent number: 7235885Abstract: A semiconductor device includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second surface of the wiring board and has inside thereof an electronic component that is electrically connected with the wiring pattern and an external terminal that is disposed on the second surface and electrically connected with the wiring pattern.Type: GrantFiled: October 19, 2004Date of Patent: June 26, 2007Assignee: Sieko Epson CorporationInventor: Shingo Horii
-
Patent number: 7214116Abstract: A light-emitting diode with no fluctuations in optical properties and good sealing properties, and a simple production method for producing this light-emitting diode. The light-emitting diode has a base comprising a cup part on which the light-emitting diode is placed, a resin material introduced into cup part, and a lens member placed on top of a cup for focusing light emitted by a light-emitting diode chip. A layer of fluorescent material, which converts the wavelength of at least some of the light from the light-emitting diode chip, is applied to the inner convex face of the lens member. When the lens member is attached to the base, the inner convex face deforms the resin material and air and excess resin material can be pushed to the outside.Type: GrantFiled: December 29, 2003Date of Patent: May 8, 2007Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.Inventor: Akira Takekuma
-
Patent number: 7195948Abstract: A method for fabricating a semiconductor device, comprising the steps of: forming an element on a silicon substrate; packaging the element; and annealing the packaged element before its transportation or long-term storage.Type: GrantFiled: December 10, 2002Date of Patent: March 27, 2007Assignee: Sharp Kabushiki KaishaInventor: Tsutomu Ashida
-
Patent number: 7138289Abstract: A multilayer color-sensing photodetector is fabricated in a semiconductor wafer having a single crystal structure to form a first, second and third layer of single crystal semiconductor material. A dielectric layer is formed that completely surrounds each single crystal region. A blocking layer is applied to prevent ion implantation where not desired. Ions are implanted into a predefined implant area. The semiconductor wafer is heated to create a dielectric layer part way through the single crystal semiconductor region. The second layer of single crystal semiconductor materials is formed by depositing a single crystal or polycrystalline material and annealing it to form a single crystal semiconductor. The deposited semiconductor layer is masked and etched to obtain single crystal regions directly above the previous layer. A blocking layer is applied and an ion implant is performed. After heating, there is left a region of single crystal silicon that has its sides and bottom surrounding by a dielectric border.Type: GrantFiled: July 7, 2004Date of Patent: November 21, 2006Assignee: JBCR Innovations, LLPInventors: Richard A. Blanchard, Richard K. Robinson
-
Patent number: 7098395Abstract: A thin-film solar cell module of a see-through structure has a plurality of integrated thin-film solar cell segments, each having a rectangular surface, provided on at least a portion of a surface region of a light-transmitting substrate having a rectangular surface and are spaced apart from each other. Adjacent solar cell segments are spaced apart at substantially regular intervals, with their long sides extending parallel to each other. Those portions of the substrate, which lie between the solar cell segments, are exposed, defining light-transmitting windows. A transparent sealing resin fills the gaps between the adjacent solar cell segments.Type: GrantFiled: March 26, 2002Date of Patent: August 29, 2006Assignee: Kaneka CorporationInventors: Masafumi Hiraishi, Naoaki Nakanishi
-
Patent number: 7074696Abstract: The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward the patterned connection layer, connection of the circuit devices to one another by means of a filler at least between the circuit devices, removal of the transfer substrate, and application of electrical connection devices for selective contact connection of the contact area of the circuit devices to one another.Type: GrantFiled: July 29, 2003Date of Patent: July 11, 2006Assignee: Infineon Technologies AGInventors: Gerd Frankowsky, Harry Hedler, Barbara Vasquez
-
Patent number: 7071505Abstract: An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided between a floating diffusion region and a gate of a source follower output transistor, with the contact also electrically connected to a storage capacitor. The storage capacitor provides additional charge storage capacity to the floating diffusion region. In addition, an associated reset transistor has different dopant characteristics in the source and drain regions. The floating diffusion region may be used in the pixels of a CMOS imager or in the output stage of a CCD imager.Type: GrantFiled: January 8, 2004Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
-
Patent number: 7060592Abstract: An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.Type: GrantFiled: September 15, 2004Date of Patent: June 13, 2006Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Cheng-Kuang Sun, Kuang-Chih Cheng, Kuang-Shin Lee
-
Patent number: 7037747Abstract: A method of manufacturing an optical device including: on at least one of a light transmitting first substrate and a second substrate which includes a first optical element having a first optical portion and a second optical element having a second optical portion, forming a first spacer in a form to surround the first optical portion, and then forming a second spacer in a form to surround the second optical portion; sealing the first and second optical portions with the first substrate and the first and second spacers by connecting the first substrate to the second substrate with the first and second spacers interposed; and cutting the second substrate to separate the first and second optical elements respectively having the first and second sealed optical portions.Type: GrantFiled: January 30, 2004Date of Patent: May 2, 2006Assignee: Seiko Epson CorporationInventor: Osamu Omori
-
Patent number: 7019401Abstract: The present invention provides a multi-layer substrate structure for reducing layout area, including a first core layer, a second core layer, and a set of coupled transmission line. The first core layer includes a first surface connected to a power supply layer and a second surface corresponding to the first surface. The second core layer includes a third surface connected to a first grounding layer and a fourth surface corresponding to the third surface. The set of coupled transmission lines includes a plurality of first differential signal lines formed on the second surface with a certain line width and a plurality of second differential signal lines formed on the fourth surface with a line width corresponding to the first differential signal lines. The second surface and the fourth surface are connected to a first dielectric layer making the second surface separated from the fourth surface with an appropriated distance.Type: GrantFiled: April 2, 2004Date of Patent: March 28, 2006Assignee: Micro-Star Int'l Co., Ltd.Inventors: Hsieh-Chen Chang, An-Ling Chi
-
Patent number: 6995034Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.Type: GrantFiled: August 30, 2004Date of Patent: February 7, 2006Assignee: Reflectivity, INCInventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
-
Patent number: 6963024Abstract: A solar cell module 60 has a plurality of solar cells 14 having a plurality of parallel grooves 8 on the individual light-receiving surfaces thereof, each of the grooves having an electrode 5 for extracting output on the inner side face (electrode-forming inner side face) on one side in the width-wise direction thereof; and a support 10, 50 for supporting the solar cells 14 in an integrated manner so as to direct the light-receiving surfaces upward. The annual power output can be increased by adjusting the direction of arrangement of the electrode-forming inner side faces of the grooves 8 while taking the angle of inclination ? of the light-receiving surface of the individual as-installed solar cells 14 relative to the horizontal plane and the latitude ? of the installation site of the solar cell module into consideration.Type: GrantFiled: January 30, 2002Date of Patent: November 8, 2005Assignees: Shin-Etsu Handotai Co., Ltd., Shin-Etsu Chemical Co., Ltd.Inventors: Satoyuki Ojima, Hiroyuki Ohtsuka, Masatoshi Takahashi, Takenori Watabe, Takao Abe
-
Patent number: 6949400Abstract: An ultrasonic slitting device cuts and seals the edges of photovoltaic cells and modules to encapsulate the photoactive components in an environment substantially impervious to the atmosphere.Type: GrantFiled: January 24, 2003Date of Patent: September 27, 2005Assignee: Konarka Technologies, Inc.Inventor: James Ryan
-
Patent number: 6914182Abstract: Two types of solar cell modules having an equal output voltage and different sizes are used, and a plurality of solar cell modules of these two types are installed so that they are connected in parallel. The size of a solar cell module having two solar cell sub-modules is two times larger than the size of a solar cell module including one solar cell sub-module. By connecting two power generating regions of each of the solar cell sub-modules of the former solar cell module in parallel, connecting adjacent two solar cell sub-modules in series and connecting two power generating regions of the solar cell sub-module of the latter solar cell module in series, an equal output voltage is obtained from both of the solar cell modules.Type: GrantFiled: July 10, 2001Date of Patent: July 5, 2005Assignee: Sanyo Electric Co., LtdInventors: Katsutoshi Takeda, Toshihiro Kinoshita
-
Patent number: 6906253Abstract: The present invention provides a solar tile and method for fabricating the same. The solar tile includes a flexible circuit having at least one electrically conductive path laminated between two insulating sheets. The flexible circuit includes a plurality of openings that are completely through the flexible circuit and define contact locations with the electrically conductive path. The solar tile also includes a plurality of coplanar photovoltaic solar cells that are secured to the flexible circuit so that the contacts are aligned with the openings in the flexible circuit. Further, the solar tile includes a plurality of electrically conductive solder connections located within the openings in the flexible circuit to electrically connect the solar cell contacts and the electrically conductive path. Additionally, in a preferred embodiment, the solar tile includes a single coverslide situated adjacent and covering the plurality of solar cells opposite the flexible circuit.Type: GrantFiled: June 26, 2002Date of Patent: June 14, 2005Assignee: The Boeing CompanyInventors: John Scott Bauman, Craig S. Flora
-
Patent number: 6893941Abstract: A semiconductor device formed by cutting a first substrate and a second substrate bonded together by a spacer, wherein: the spacer is disposed at an end of the first substrate after cutting; the second substrate is a semiconductor wafer formed with a light reception element or elements; and the first substrate has an optical element or an optical element set for converging light on the light reception element or elements. A method of manufacturing such a semiconductor device. A semiconductor device manufacture method includes: a step of detecting a warp of a semiconductor substrate; a step of holding the semiconductor substrate on a base under a condition that the warp is removed; a step of bonding an opposing substrate to the semiconductor substrate; and a step of cutting the opposing substrate, wherein the opposing substrate bonded to the semiconductor substrate is set with a size corresponding to the warp of the semiconductor substrate or with a gap to an adjacent opposing substrate.Type: GrantFiled: July 31, 2003Date of Patent: May 17, 2005Assignee: Canon Kabushiki KaishaInventor: Yasuo Suda
-
Patent number: 6841411Abstract: A method of forming an image sensor array uses a transparent top conductive layer first as an etch mask in forming inter-pixel trenches and then as an etch stop in a planarization step, whereafter the top conductive layer is integral to operation of the completed image sensor array. During fabrication, a stack of layers is formed to collectively define a continuous photosensitive structure over an array area. The operationally dependent transparent top conductive layer is then used in the patterning of the photosensitive structure to form trenches between adjacent pixels. An insulating material is deposited within the trenches and the top conductive layer is then used as the etch stop in planarizing the insulating material. The method includes providing a connectivity layer that provides electrical continuity along the patterned top conductive layer.Type: GrantFiled: June 30, 2003Date of Patent: January 11, 2005Assignee: Agilent Technologies, Inc.Inventor: Ronnie P. Varghese
-
Patent number: 6809250Abstract: In a method of repairing a solar panel having a defective solar cell or cells, a replacement cell (or cells) is glued onto a defective solar cell or cells of the solar panel, and is electrically integrated in the solar panel.Type: GrantFiled: December 23, 2002Date of Patent: October 26, 2004Assignee: Astrium GmbHInventor: Reiner Gerson
-
Patent number: 6803514Abstract: A mounting structure for mounting a photovoltaic element onto a metal body, which outputs a power generated by the photovoltaic element to the outside surface, and a method for mounting the photovoltaic element. In the mounting structure, the metal body has a first surface and a second surface opposite the first surface, in which the photovoltaic element is joined to the first surface and an electrically insulative material is joined to the second surface. A semiconductor element-mounting substrate for mounting a semiconductor element thereon comprising a retaining substrate having a circuit pattern, which has an electrode-joining portion for joining the semiconductor element electrode portion, an external terminal-fixing portion, and a groove between the electrode-joining portion and external-fixing portion, and a method for mounting the semiconductor element. In the mounting substrate, the electrode-joining portion is larger than the semiconductor element electrode portion.Type: GrantFiled: March 25, 2002Date of Patent: October 12, 2004Assignee: Canon Kabushiki KaishaInventor: Yoshifumi Takeyama
-
Patent number: 6803513Abstract: A photovoltaic module includes at least a first and a second photovoltaic cell each having a substrate electrode, a top electrode and a photovoltaic semiconductor body disposed therebetween in electrical communication with the substrate electrode and the top electrode. Each cell includes a plurality of current collecting grid wires disposed atop the top electrode in electrical contact therewith. The grid wires of the first cell are in electrical communication with a current collecting bus bar and the grid wires of the second cell extend onto the first cell so as to establish an unbroken current path therebetween. The grid wires of the second cell may establish electrical communication with the substrate electrode of the first cell, in which case a series connection therebetween is established. Alternatively, the grid wires of the second cell may establish electrical communication with the top electrode of the first cell so as to create a parallel electrical connection therebetween.Type: GrantFiled: August 20, 2002Date of Patent: October 12, 2004Assignee: United Solar Systems CorporationInventors: Kevin Beernink, Eric Akkashian
-
Patent number: 6770503Abstract: A micromechanical sensor is fabricated on a semiconductor wafer, and a control circuit is fabricated on another semiconductor wafer. A cavity is etched on the back side of the control circuit wafer, the cavity being formed such that the sensor on the other wafer fits within the cavity when the wafers are brought together in an adjoining relationship. Through-holes are etched through the back side of the control circuit wafer to allow access to electrical contact points, and a patterned layer of metal is deposited to form electrical interconnections between the electrical contact points and termination points on the back side of the wafer via the through-holes. The termination points are arranged such that electrical contacts of the sensor contact the termination points when the wafers are placed in the adjoining relationship. The wafers are then cleaned and bonded together in the adjoining relationship.Type: GrantFiled: October 21, 1999Date of Patent: August 3, 2004Assignee: The Charles Stark Draper Laboratory, Inc.Inventors: Thomas F. Marinis, Jerome B. Sohn, Richard P. Tumminelli
-
Patent number: 6737338Abstract: A pattern forming method of the present invention for forming a predetermined pattern on a photosensitive resin film by (i) layering the photosensitive resin film on an inorganic thin film with which a plastic substrate is coated and (ii) exposing the photosensitive resin film via a photomask having the predetermined pattern in an exposing step is characterized by including the step of heating the plastic substrate having the inorganic thin film before the exposing step, a time from an end of the heating step to a start of the exposing step being managed to be not less than a predetermined time, in accordance with an asymptotic contracting behavior after the end of the heating step of the plastic substrate having the inorganic thin film. With this, it is possible to provide a pattern forming method capable of forming a plurality of patterns on a plastic substrate with high accuracy of superposition, and a display device manufactured using the same.Type: GrantFiled: February 13, 2003Date of Patent: May 18, 2004Assignee: Sharp Kabushiki KaishaInventor: Hitoshi Takeda
-
Patent number: 6738538Abstract: This invention discloses a novel method of manufacturing optical communications infrastructures that are implemented on a flat semiconductor wafer. This invention has the following characteristics which enable the efficient manufacturing of a combination of elements onto such a wafer: the inherent surface flatness, crystal purity and uniformity over a relatively large dimension for semiconductor wafers; the low cost and wide availability of such wafers; and the ability to combine several types of elements onto the wafer, on a very dense scale, and in a highly repeatable and mechanically aligned manner.Type: GrantFiled: October 25, 2001Date of Patent: May 18, 2004Inventors: Patrick R. Antaki, Mark N. Shepard
-
Patent number: 6727110Abstract: A method and apparatus for fabricating silica-based waveguide devices on a substrate using a low temperature PECVD process using a TEOS source material for depositing waveguide layers containing silica, the apparatus being arranged, in use, in a manner such that a liquid source material containing silicon is used during the PECVD.Type: GrantFiled: November 8, 2001Date of Patent: April 27, 2004Assignee: Redfern Integrated Optics PTY LTDInventor: Michael Bazylenko
-
Patent number: 6723579Abstract: A semiconductor wafer having a matrix array of micro-mirrors comprises a component substrate carried on a base substrate. The component substrate comprises a membrane layer in which the micro-mirrors are formed and a supporting handle layer. The base substrate comprises a base layer from which a plurality of pedestals extend upwardly therefrom into cavities in the handle layer corresponding to the micro-mirrors. Each pedestal carries electrodes for co-operating with the micro-mirrors for tilting thereof. Conductors through vias in the pedestals connect the electrodes to electrically conductive tracks on a bottom surface, and in turn through conductors through vias to addressing terminals for addressing the electrodes.Type: GrantFiled: July 12, 2002Date of Patent: April 20, 2004Assignee: Analog Devices, Inc.Inventors: Colin Stephen Gormley, Stephen Alan Brown, Scott Carlton Blackstone
-
Patent number: 6723576Abstract: An active-matrix type organic EL display which uses transistors with less variation of characteristics (transistors in which active layer is a single crystal semiconductor) is made on a large area of a transparent base board at low cost. Plural unit of fine construction are formed on a silicon wafer in rows. This unit includes a driving element (switching transistor 34, driving transistor 37, capacity 36) of organic EL element (pixel) 35. Unit block 39 is produced by dividing this silicon wafer. This unit block 39 is disposed at a predetermined position of glass base board 52 (display base board). The driving element of each pixel 35 is connected by signal line 31, power supply line 32, scanning line 33, and capacity line 38.Type: GrantFiled: June 29, 2001Date of Patent: April 20, 2004Assignee: Seiko Epson CorporationInventors: Ryoichi Nozawa, Mutsumi Kimura, Satoshi Inoue
-
Patent number: 6709795Abstract: A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.Type: GrantFiled: August 29, 2002Date of Patent: March 23, 2004Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Kevin G. Duesman
-
Patent number: 6686291Abstract: A method (30) of fabricating a micromechanical device (10) by performing spacer layer undercutting (46) and passivation at the package level. A back-end assembly process utilizes a full-cut saw process to separate the partially fabricated micromechanical devices. The individual die are then attached by pick and place equipment to a lead frame and are wire bonded, before the die are undercut. This technique avoids the generation of any particles from becoming lodged under movable structure during the cut process, and further, reduces the susceptibility of the die to damage or particles generated during the pick and place process.Type: GrantFiled: May 20, 1997Date of Patent: February 3, 2004Assignee: Texas Instruments IncorporatedInventor: Edgardo R. Hortaleza
-
Patent number: 6682990Abstract: The separation method of a semiconductor layer according to the present invention comprises separating a semiconductor layer and a semiconductor substrate at a separation layer formed therebetween, wherein a face of the semiconductor layer at the side opposite to the separation layer and/or a face of the semiconductor substrate at the side opposite to the separation layer are held by utilizing an ice layer, whereby it is unnecessary to use an adhesive as holding means and at the same time it is possible to easily and uniformly separate them.Type: GrantFiled: September 7, 2000Date of Patent: January 27, 2004Assignee: Canon Kabushiki KaishaInventors: Masaaki Iwane, Katsumi Nakagawa, Makoto Iwakami, Shoji Nishida, Noritaka Ukiyo, Yukiko Iwasaki, Masaki Mizutani
-
Patent number: 6660564Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.Type: GrantFiled: January 25, 2002Date of Patent: December 9, 2003Assignees: Sony Corporation, Sony Electronics, Inc.Inventor: Frederick T. Brady
-
Patent number: 6660930Abstract: A laminated solar cell module comprises a front light transmitting support, a plurality of interconnected solar cells encapsulated by a light-transmitting encapsulant material, and an improved backskin formed of an ionomer/nylon alloy. The improved backskin has a toughness and melting point temperature sufficiently great to avoid any likelihood of it being pierced by any of the components that interconnect the solar cells.Type: GrantFiled: June 12, 2002Date of Patent: December 9, 2003Assignee: RWE Schott Solar, Inc.Inventor: Ronald C. Gonsiorawski
-
Publication number: 20030219922Abstract: A method of preventing seal damage in LCD panel manufacturing. A photo spacer pattern made of photoresist is used instead of extra seal pattern, such that tact time of sealing process is reduced, air blockage is enhanced, the number of TFT-array areas able to be formed on a glass substrate is increased, and chipping or unevenness of the panel resulting during panel cutting owing to extra seal patterns are all avoided.Type: ApplicationFiled: December 30, 2002Publication date: November 27, 2003Inventors: Hsiang Lung Liu, Hsu-Ho Wu
-
Patent number: 6652904Abstract: The present invention relates to manufacturing of regenerative photovolatic photoelectrochemical (RPEC) devices. The invention describes a method for manufacturing RPEC devices in a production line. The method comprises the steps of: dispensing a protective film in a substantially continuous sheet; attaching at least one substrate to the protective film in such a way that predetermined areas of the substrate are protected from being coated during at least one subsequent manufacturing process; using the protective films as a means to transport the substrate, along the production line through the at least one subsequent manufacturing process.Type: GrantFiled: November 30, 2001Date of Patent: November 25, 2003Assignee: Sustainable Technologies International Pty. LimitedInventors: George Phani, Jason Andrew Hopkins, David Vittorio
-
Patent number: 6645790Abstract: The present invention is generally drawn to a system and method for creating RF integrated microwave circuits that can support multiple applications where many RF functions can be derived from a generic integrated circuit after the RF integrated microwave circuit is manufactured. More specifically, the present invention can provide active and passive device building blocks of respective monolithic microwave integrated circuit (MMIC) arrays and substrates that can be coupled together in various ways after manufacture of the integrated circuits to achieve multiple applications. This can accomplished by manufacturing chips with multiple active device blocks that can support various and multiple applications and that can be coupled together in various ways, adjusted, or tuned after manufacture.Type: GrantFiled: December 21, 2001Date of Patent: November 11, 2003Assignee: Anadigics, Inc.Inventors: Sanjay B. Moghe, Carl S. Chun, Pranav N. Patel, Seung-yup Yoo
-
Patent number: 6642077Abstract: The invention concerns a method for manufacturing and assembling individual photovoltaic silicon cells on a metal substrate, including the operations of: making a metal plate (25) provided with cut out portions (26, 29) separated from each other by points of attachment (27) and delimiting the bases of a plurality of cells; depositing a stack of silicon layers then a metallization on said plate in order to form a group of individual cells (28a-b-c-d); transferring said group onto an interconnection support (30); and perforating the points of attachment in order to separate the cells from the rest of the plate.Type: GrantFiled: September 22, 2000Date of Patent: November 4, 2003Assignee: Asulab S.A.Inventor: Jean-Claude Berney
-
Patent number: 6635505Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.Type: GrantFiled: November 18, 2002Date of Patent: October 21, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yukio Tanaka, Shou Nagao