Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.

Abstract: A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.

Abstract: The present invention is provided to prevent yield reduction of semiconductor device in dry cleaning of semiconductor device manufacturing process. The electric action and chemical action due to plasma of a first gas generated by means of a plasma generating means and the physical action due to viscous friction force of high speed gas flow generated by means of a planar pad that is brought close to the main surface of a wafer are applied together for cleaning the main surface of the wafer. After cleaning, the wafer is exposed to plasma of a second gas in the same vacuum chamber and then transferred to the atmosphere.

Abstract: A plasma processing chamber and method provides the ability to make dissociation of reactive gasses independent from ionization of dilutant gasses. It also provides the ability to control the amount of dissociation of reactive gasses. The distance between the injection points for the reactive gasses and the dilutant gasses is substantially larger than the distance between the wafer pedestal and where the reactive gasses are injected. This distance between injection locations helps makes dissociation of reactive gasses independent from ionization of dilutant gasses. The use of a secondary excitation source that excites substantially only the dilutant gasses further contributes to the ability to control dissociation of reactive gasses independently of ionization of dilutant gasses. The ability to adjust the location of the injection point of the reactive gasses further provides the ability to control dissociation in a novel way.

Abstract: An opening through an insulating layer between a first layer and a second layer of a semiconductor device is formed where the second layer is a polysilicon or amorphous silicon hard mask layer. The polysilicon or amorphous silicon hard mask layer is etched to form at least one opening through the polysilicon or amorphous silicon hard mask layer using a patterning layer as a mask having at least one opening. The insulating layer is etched to form the opening through the insulating layer using the etched polysilicon or amorphous silicon hard mask layer as a mask. The etched polysilicon or amorphous silicon hard mask layer is nitridized prior to subsequent processing.

Abstract: An improved chemical vapor deposition or etching is shown in which cyclotron resonance and photo or plasma CVD cooperate to deposit a layer with high performance at a high deposition speed. The high deposition speed is attributed to the cyclotron resonance while the high performance is attributed to the CVDs.

Abstract: A process of etching openings in a dielectric layer includes supporting a semiconductor substrate in a plasma etch reactor, the substrate having a dielectric layer and a patterned photoresist and/or hardmask layer above the dielectric layer; supplying to the plasma etch reactor an etchant gas comprising (a) a fluorocarbon gas (CxFyHz, where x≧1, y≧1, and z≧0), (b) a silane-containing gas, hydrogen or a hydrocarbon gas (CxHy, where x≧1 and y≧4), (c) an optional oxygen-containing gas, and (d) an optional inert gas, wherein the flow rate ratio of the silane-containing gas to fluorocarbon gas is less than or equal to 0.1, or the flow rate ratio of the hydrogen or hydrocarbon gas to fluorocarbon gas is less than or equal to 0.5; energizing the etchant gas into a plasma; and plasma etching openings in the dielectric layer with enhanced photoresist/hardmask to dielectric layer selectivity and/or minimal photoresist distortion or striation.

Abstract: A plasma photoresist hardening technique is provided to improve the etch resistance of a photoresist mask 26. The technique involves the formation of a thin passivation layer 26b on the photoresist mask 26 which substantially slows down the etching rate of the photoresist material 26a. Advantageously, this technique allows preservation of critical dimension features such as via hole openings and transmission lines. The technique hardens the surface of the photoresist film 26 by both chemically and physically bonding halogenated hydrocarbons with cross linked photoresist polymer. This results in a passivation layer 26b which is highly resistant to harsh plasma etch environments.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: An active matrix substrate includes a line layer formed of an Al-based metal layer and a part of which is exposed through a contact hole formed in an insulating film. In the active matrix substrate, pixel electrodes are formed of an ITO film on the insulating film, and a jumper line for connecting a disconnected portion of a protect ring, a surface layer of a data line connecting pad, and a line protecting film are formed at the same time as the pixel electrodes are formed. This reduces the number of fabrication steps. The ITO film is patterned by dry etching due to reactive ion etching using a mixed gas of a hydrogen halide gas and an inert gas, with the temperatures of the center portion and peripheral portion of the substrate substantially equalized to each other.

Abstract: A method and apparatus for performing in situ measurement of etch uniformity within a semiconductor wafer processing system. Specifically, the apparatus and concomitant method analyzes optical emission spectroscopy (OES) data produced by an OES system. The analysis computes the first derivative of the OES data as the data is acquired. When the data meets a particular trigger criterion, the value of the first derivative is correlated with a particular uniformity value. As such, the system produces a uniformity value for a semiconductor wafer using an in situ measurement technique.

Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.

Abstract: In a processing chamber of an etching apparatus a lower electrode and an upper electrode grounded through a processing container are disposed oppositely to each other. A first high frequency power supply section composed of a first filter, a first matching device, and a first power source, and a second high frequency power supply section composed of a second filter, a second matching device, and a second power source are connected to the lower electrode. A superimposed power of two frequencies composed of a first high frequency power component of at least 10 MHz produced from the first power source and a second high frequency power component of at least 2 MHz produced from the second power source is applied to the lower electrode. Ions in the plasma do not accelerated by changes of electric field in the processing chamber, but are accelerated by a self-bias voltage and collide only against a wafer on the lower electrode.

Abstract: A method for plasma etching substrates having high open area patterns is described. The method is useful in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used to etch strict profile control trenches with 89° +/−1° sidewalls on silicon substrates with high open area patterns such as patterns between about 50% and about 90%. The novel method plasma etches high open area substrates using a plasma formed from a gaseous mixture that includes an oxygen source gas, a fluorine source gas and a fluorocarbon source gas. In an alternative embodiment, the fluorocarbon source gas is a passivation gas. In another alternative embodiment, the fluorocarbon source gas consists essentially of a fluorocarbon having fluorine and carbon in a 2:1 ratio. In another particular embodiment, the oxygen source gas is O2, the fluorine source gas is SF6 and the fluorocarbon source gas is C4F8.

Abstract: An oxygen-free and nitrogen-free plasma ashing process for removing photoresist in the presence of a low k material from a semiconductor substrate. The process includes forming reactive species by exposing a plasma gas composition to an energy source to form plasma. The plasma gas composition is free from oxygen-bearing and nitrogen-bearing gases. The plasma selectively removes the photoresist from the underlying substrate containing low k material by exposing the photoresist to the reactive species. The process can be used with carbon and/or hydrogen based low k dielectric materials.

Abstract: A method of manufacturing a semiconductor device (2) on a substrate (1), the semiconductor device including an active area (5, 6, 16) in the substrate (1) demarcated by spacers (10-13,20-23) and arranged so as to contact an interconnect (29) including TiSi2; the method includes: depositing an oxide layer (26) on the substrate (1); depositing and patterning a resist layer (27) on the oxide (26); reactive ion etching of the oxide (26) to demarcate the active area (5, 6, 16), using the patterned resist layer (27); removing the resist (27) by a dry strip plasma containing at least oxygen; depositing titanium (28) on the oxide (26) and the active area (5, 6, 16); forming the interconnect (29) as self-aligned TiSi2 by a first anneal, a selective wet etch, and a second anneal; the dry strip plasma including, as a second gaseous constituent, at least fluoride.

Abstract: A method for controlling etch bias of carbon doped oxide films comprising performing the etch in a cyclic two step process i.e., a carbon doped oxide (CDO) removal process, said CDO removal process comprises a first gas to etch a trench in the CDO layer. The CDO removal process is followed by a polymer deposition process. The polymer deposition process comprises introducing a second gas in the reactor to deposit a polymer in the trench of the CDO layer. The first gas comprises a first molecule having a first ratio of carbon atoms to fluorine atoms, and the second gas comprises a second molecule having a second ratio of carbon atoms to fluorine atoms, such that the second ratio of carbon atoms to fluorine atoms is greater than the first ratio of carbon atoms to fluorine atoms. The above process may be repeated to etch the final structure.

Abstract: A method for processing substrates, in which a photoresist layer is applied and structured on their surface. By blasting the substrate with particles, recesses are put into the surface of the substrate in those areas not covered by photoresist.

Abstract: Semiconductor wafers are cleaned by placing the semiconductor wafers in a processing vessel, forming a pure water film on the surfaces of the wafers, forming an ozonic water film by dissolving ozone gas in the pure water film, and removing resist films formed on the wafers by the agency of the ozonic water film. The pure water film is formed by condensing steam on the surfaces of the wafers. The resist films formed on the surfaces of the wafers can be removed by also using hydroxyl radicals produced by interaction between steam and ozone gas supplied into the processing vessel. Thus, the resist films can be removed highly effectively.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: An oxide etch process practiced in a plasma etch reactor, such as a magnetically enhanced reactive ion etch (MERIE) reactor. The etching gas includes approximately equal amounts of a hydrogen-free fluorocarbon, most preferably C4F6, and oxygen and a much larger amount of argon diluent gas. The magnetic field is preferably maintained above about 50 gauss and the pressure at 40 milliTorr or above with chamber residence times of less than 70 milliseconds. A two-step process may be used for etching holes with very high aspect ratios. In the second step, the magnetic filed and the oxygen flow are reduced. Other fluorocarbons may be substituted which have F/C ratios of less than 2 and more preferably no more than 1.6 or 1.5.

Abstract: A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.

Abstract: A process of reducing critical dimension (CD) microloading in dense and isolated regions of etched features of silicon-containing material on a substrate uses a plasma of an etchant gas and an additive gas. In one version, the etchant gas comprises halogen species absent fluorine, and the additive gas comprises fluorine species and carbon species, or hydrogen species and carbon species.

Abstract: A method of etching silicon using a plasma generated from a gas comprising fluorine (F), oxygen (O), hydrogen (H) and carbon (C).

Abstract: Chemical generator and method for generating a chemical species at a point of use such as the chamber of a reactor in which a workpiece such as a semiconductor wafer is to be processed. The species is generated by creating free radicals, and combining the free radicals to form the chemical species at the point of use.

Abstract: A method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined.

Abstract: A semiconductor dry etching process that provides deep, smooth (RMS of less than approximately 5 nm), and vertical etching of InP-based materials with ICP RIE using a chlorinated plasma with the addition of hydrogen gas. Inert gases such as nitrogen, argon, or both may also be included. To produce relatively high anisotropy with exceptionally smooth surfaces, the amount of hydrogen gas added preferably exceeds the volumetric measure of chlorinated gas in standard cubic centimeter per minute (sccm); at a ratio of greater than 1:1. The present invention provides an improved dry etching process for InP-based semiconductor materials that yields deep, vertical etch profiles with improved surface smoothness (i.e., morphology) and high manufacturing etch rates.

Abstract: First of all, a semiconductor substrate having a metal contact thereon is provided. Then a protecting layer is formed on the semiconductor substrate and the metal contact. Afterward, an etching process is performed to etch through the protecting layer until exposing a partial surface of the metal contact, so as to form and define a predetermined opening in the protecting layer, wherein an etching-reactive layer is formed on the protecting layer after finishing the plasma etching process. Finally, a stripping process is performed to remove the etching-reactive layer on the protecting layer and form a contact window and a metal contact thereof without fluoride, whereby it is avoided reacting the etching remainder with the metal pad during the follow-up process.

Abstract: An etching gas mixture containing CHF3, SF6 and a non-oxidizing gas such as Ar is used as an etching gas mixture for the anisotropic plasma-chemical dry-etching of a silicon nitride layer differentially or selectively relative to a silicon oxide layer. The gas mixture does not contain oxygen, chlorine, bromine, iodine or halides in addition to the above mentioned constituents, so that the process can be carried out in reactor systems equipped with oxidizable electrodes. By adjusting the gas flow rates or composition ratios of CHF3, SF6, and argon in the etching gas mixture, it is possible to adjust the resulting etching selectivity of silicon nitride relative to silicon oxide, and the particular edge slope angle of the etched edge of the remaining silicon nitride layer. A high etch rate for the silicon nitride is simultaneously achieved.

Abstract: A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen.

Abstract: The present disclosure provides a method for etchback of a conductive layer in a contact via (contact hole). The method described is typically used in the formation of a conductive plug within the contact hole. The method includes a first etchback in which the conductive layer is etched back; a buffer (i.e., transition) step during which the etch rate of the conductive layer is reduced; and a second etchback in which the amount of chemically reactive etchant is reduced from that used in the first etchback and a plasma species is added to provide additional physical bombardment, in an isotropic etch of the substrate surface surrounding the contact hole.

Abstract: Conventional methods of etching TiSix use Cl2 or HBr as the plasma etchant. However, these methods can lead to undesirable residues, due to the presence of silicon nodules in the TiSix The present invention overcomes the residue problem by adding a fluorine containing gas to the plasma etchant, which is then able to effectively etch the Si nodules at an etch rate which is approximately the same as the etch rate of the TiSix, so that the undesirable residue is not formed. A method of etching TiSix is provided, wherein the surface of the TiSix is exposed, typically through a patterned mask, to a plasma etchant. The plasma etchant comprises (i) at least one fluorine containing gas, such as SF6, NF3, CxFy, and compatible mixtures of such gases; and (ii) a gas selected from the group consisting of HBr, Cl2, and combinations thereof.

Abstract: A method for forming a trench for a shallow trench isolation structure wherein the trench has rounded bottom corners. In one embodiment, the present invention performs a breakthrough etch to remove a native oxide layer disposed over a region of a semiconductor substrate. In so doing, a region of the semiconductor substrate is exposed. Next, the present embodiment etches a trench into the semiconductor substrate using a first etching environment. In this embodiment, the first etching environment is comprised of chlorine, hydrogen bromide, helium, and oxygen. The present embodiment then rounds the bottom corners of the trench using a second etching environment. In this embodiment, the second etching environment is comprised sulfur hexafluoride (SF6) and chlorine. In so doing, the present embodiment provides a method for forming a trench for a shallow trench isolation structure wherein the trench does not have sharp bottom corners formed therein.

Abstract: A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.

Abstract: A method for removing sacrificial materials and metal contamination from silicon surfaces during the manufacturing of an integrated micromechanical device and a microelectronic device on a single chip is provided which includes the steps of adjusting the temperature of the chip using a reaction chamber to a temperature appropriate for the selection of a beta-diketone and the design of micromechanical and microelectronic devices, cycle purging the chamber using an inert gas to remove atmospheric gases and trace amounts of water, introducing HF and the beta-diketone as a reactive mixture into the reaction chamber which contains at least one substrate to be etched, flowing the reactive mixture over the substrate until the sacrificial materials and metal contamination have been substantially removed, stopping the flow of the reactive mixture; and cycle purging the chamber to remove residual reactive mixture and any remaining reaction by-products.

Abstract: A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

Abstract: A process for etching a substrate 25 in an etching chamber 105, and simultaneously removing etch residue deposited on the surfaces of the walls 110 and components of the etching chamber 105. In one version, a two-stage method of opening a nitride mask layer on the substrate includes a first stage of providing a highly chemically reactive process gas in the chamber 105 to etch the nitride layer 32 and/or an underlying oxide layer 34, and a second stage of providing a less chemically reactive process gas in the chamber to etch the nitride layer 32 and/or the oxide layer 34 at a slower rate than the first stage. The first and second stage process gases may each comprise a fluorine containing gas, with the fluorine ratio of the first gas higher than the fluorine ratio of the second gas.

Abstract: A method and apparatus for high density nanostructures is provided. The method and apparatus include Nano-compact optical disks, such as nano-compact disks (Nano-CDS). In one embodiment a 400 Gbit/in2 topographical bit density nano-CD with nearly three orders of magnitude higher than commercial CDS has been fabricated using nanoimprint lithography. The reading and wearing of such Nano-CDS have been studied using scanning proximal probe methods. Using a tapping mode, a Nano-CD was read 1000 times without any detectable degradation of the disk or the silicon probe tip. In accelerated wear tests with a contact mode, the damage threshold was found to be 19 &mgr;N. This indicates that in a tapping mode, both the Nano-CD and silicon probe tip should have a lifetime that is at least four orders of magnitude longer than that at the damage threshold.

Abstract: A method for fabricating a NROM is described, in which a bottom anti-reflective coating (BARC) and a photoresist pattern are sequentially formed on a substrate that has a charge trapping layer formed thereon. An etching process is then performed to pattern the BARC and the charge trapping layer with the photoresist pattern as a mask. The etching process is conducted in an etching chamber equipped with a source power supply and a bias power supply, which two have a power ratio of 1.5˜3, while an etchant used therein is a gas plasma containing trifluoromethane (CHF3) and tetrafluoromethane (CF4). Thereafter, a buried drain is formed in the substrate, a buried drain oxide layer is formed on the buried drain, and then plural gates are formed on the substrate.

Abstract: In pre-treating a surface of a substrate in a process of forming a narrowed thin film pattern on the surface of the substrate from a solution such as a plating liquid, a mask with an opening corresponding to the thin film pattern to be formed later is formed on the surface of the substrate. Then, by micronizing a pre-treating liquid such as a water, a plating liquid, an acidic liquid ad an alkaline liquid, an atmosphere containing microparticles having diameters smaller than the minimum distance of the opening of the mask is produced. The substrate is positioned into the atmosphere, and the microparticles of the pre-treating liquid are stuck on the surface of the substrate exposing to the lower part of the opening of the mask. In using a water as the pre-treating liquid, the substrate is positioned into an atmosphere containing moisture vapor and the water particles are stuck on the surface of the substrate through their condensation.

Abstract: Plasma etching processes using a plasma containing fluorine as well as bromine and/or iodine are suited for high aspect ratio etching of trenches, contact holes or other apertures in silicon oxide materials. The plasma is produced using at least one fluorine-containing source gas and at least one bromine- or iodine-containing source gas. Bromine/iodine components of the plasma protect the aperture sidewalls from lateral attack by free fluorine, thus advantageously reducing a tendency for bowing of the sidewalls. Ion bombardment suppresses absorption of bromine/iodine components on the etch front, thus facilitating advancement of the etch front without significantly impacting taper.

Abstract: A post-cleaning method of a via etching process for cleaning a wafer, the wafer having a tungsten (W) layer, an oxide layer covered on the tungsten layer, a photoresist layer patterned on the oxide layer, and a via passing through the photoresist layer and the oxide layer until a predetermined area of the tungsten layer is exposed, the cleaning method has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; (b) performing a dry cleaning process which uses CF4 and N2H2 as the main reactive gas; and (c) performing a water-rinsing process.

Abstract: A microelectronic component is made by providing a starting structure having a dielectric layer and leads on a surface of the dielectric layer. Ends of the leads are connected to contacts on a microelectronic element, such as the contacts on a semiconductor chip or wafer. The dielectric layer is then etched to partially detach the leads from the dielectric layer, leaving at least one end of each lead permanently connected to the dielectric layer. The remainder of the lead may be fully or partially detached from the dielectric layer. If the remainder of the lead is only partially detached, the connecting elements that connects the leads to the polymeric layer can be broken or peeled away from the leads during the step of moving the microelectronic element and dielectric layer away from one another.

Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.

Abstract: A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n+ amorphous-silicon layer and a metal layer. The metal layer defines a source electrode and a drain electrode. The structure simplifies the photolithography process by using a less number of masks to manufacture thin film transistors. It also reduces the occurrence of open circuits in the first metal (MI) layer or short circuits between the MI layer and the second metal (MII) layer caused by the photoresist residue or particle contamination. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology uses two photoresist pattern masks. One is a pattern mask for complete exposure with higher light intensity and the other is a pattern mask for incomplete exposure with lower light intensity.

Abstract: To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.

Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.

Abstract: An oxide etch process practiced in magnetically enhanced reactive ion etch (MERIE) plasma reactor. The etching gas includes approximately equal amounts of a hydrogen-free fluorocarbon, most preferably C4F6, and oxygen and a much larger amount of argon diluent gas. The magnetic field is preferably maintained above about 50 gauss and the pressure at 40 milliTorr or above with chamber residence times of less than 70 milliseconds. A two-step process may be used for etching holes with very high aspect ratios. In the second step, the magnetic filed and the oxygen flow are reduced. Other fluorocarbons may be substituted which have F/C ratios of less than 2 and more preferably no more than 1.6 or 1.5.

Abstract: A method for forming a patterned oxygen containing plasma etchable layer. There is first provided a substrate. There is then formed upon the substrate a blanket oxygen containing plasma etchable layer. There is then formed upon the blanket oxygen containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer the blanket hard mask layer to form a patterned hard mask layer. There is then etched while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer the blanket oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etchable layer.

Abstract: A gas distribution system for uniformly or non-uniformly distributing gas across the surface of a semiconductor substrate. The gas distribution system includes a support plate and a showerhead which are secured together to define a gas distribution chamber therebetween. A baffle assembly including one or more baffle plates is located within the gas distribution chamber. The baffle arrangement includes a first gas supply supplying process gas to a central portion of the baffle chamber and a second gas supply supplying a second process gas to a peripheral region of the baffle chamber. Because the pressure of the gas is greater at locations closer to the outlets of the first and second gas supplies, the gas pressure at the backside of the showerhead can be made more uniform than in the case with a single gas supply.