Including Change In Etch Influencing Parameter (e.g., Energizing Power, Etchant Composition, Temperature, Etc.) Patents (Class 438/714)
  • Patent number: 9437450
    Abstract: In a plasma etching method, with respect to a substrate to be processed, which has a base layer, a silicon oxide film, and an etching mask formed in this order, the etching mask having an etching pattern formed thereon and being formed of polysilicon, a silicon-containing deposit is deposited on a surface of the etching mask using a plasma generated from a processing gas, while applying a negative direct current voltage to an upper electrode formed of silicon. Furthermore, in the plasma etching method, the silicon oxide film is etched using plasma generated from a first CF-based gas using, as a mask, the etching mask having the silicon-containing deposit deposited thereon.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 6, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tetsuro Kikuchi
  • Patent number: 9419211
    Abstract: A gas for an etching process and a treatment process of a metal stacked film in which an insulating layer is interposed between two layers of magnetic materials can be optimized. An etching method of etching a multilayered film including a metal stacked film in which an insulating layer is interposed between a first magnetic layer and a second magnetic layer includes etching the metal stacked film with plasma generated by supplying a gas containing at least C, O, and H into a processing chamber; and treating the metal stacked film with plasma generated by supplying a gas containing at least a CF4 gas into the processing chamber.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: August 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Masato Kushibiki, Nao Koizumi, Takashi Sone, Fumiko Yamashita
  • Patent number: 9306019
    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Jing Wan, Guillaume Bouche, Andy Wei, Shao Ming Koh
  • Patent number: 9299579
    Abstract: An etching method of selectively etching a first region formed of silicon oxide with respect to a second region formed of silicon nitride includes: a process (a) and a process (b). In the process (a), a target object is exposed to plasma of a fluorocarbon gas and a thickness of a protective film on the second region is larger than a thickness of a protective film formed on the first region. In the process (b), the first region is etched by plasma of a fluorocarbon gas. In the process (a), a temperature of the target object is set to 60° C. or more to 250° C. or less.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: March 29, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Maju Tomura, Hikaru Watanabe, Takahiko Kato, Masanobu Honda
  • Patent number: 9275869
    Abstract: A method for etching a layer in a plasma chamber with an inner injection zone gas feed and an outer injection zone gas feed is provided. The layer is placed in the plasma chamber. A pulsed etch gas is provided from the inner injection zone gas feed at a first frequency, wherein flow of pulsed etch gas from the inner injection zone gas feed is ramped down to zero. The pulsed etch gas is provided from the outer injection zone gas feed at the first frequency and simultaneous with and out of phase with the pulsed etch gas from the inner injection zone gas feed. The etch gas is formed into a plasma to etch the layer, simultaneous with the providing the pulsed etch gas from the inner injection zone gas feed and providing the pulsed gas from the outer interjection zone gas feed.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 1, 2016
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Alexander Paterson
  • Patent number: 9246071
    Abstract: The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a photoresist film is formed on a surface of the substrate. Third, a nano-pattern is formed on the photoresist film by nano-imprint lithography. Fourth, the photoresist film is etched to form a patterned photoresist layer. Fifth, a mask layer is covered on the patterned photoresist layer and the surface of the substrate exposed to the patterned photoresist layer. Sixth, the patterned photoresist layer and the mask layer thereon are removed to form a patterned mask layer. Seventh, the substrate is etched through the patterned mask layer by reactive ion etching, wherein etching gases includes carbon tetrafluoride, sulfur hexafluoride, and argon. Finally, the patterned mask layer is removed.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: January 26, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen
  • Patent number: 9238870
    Abstract: A reactive ion etching (RIE) process comprising a chlorine source gas and an oxygen source gas with an atomic ratio of chlorine to oxygen in the plasma of at least 6 to 1 is used to etch chromium alloy films such as SiCr, SiCrC, SiCrO, SiCrCO, SiCrCN, SiCrON, SiCrCON, CrO, CrN, CrON, and NiCr for example. Additionally, a fluorine source may be added to the etch chemistry.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abbas Ali
  • Patent number: 9214355
    Abstract: As device feature size shrinks, plasma induced damage is a major concern affecting micro-electronic and nano-electronic device fabrication. Pulsed plasmas are a means of mitigating the damages. However, in conventional standard etch chemistry, the etch rate for pulsed plasmas is reduced significantly resulting in a substantially decreased throughput of tech processes. A new etch chemistry is disclosed in the present invention to increase throughput in pulsed plasma applications driven mainly by the molecular radicals.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sebastian U. Engelmann, Nathan P. Marchack, Masahiro Nakamura
  • Patent number: 9208997
    Abstract: A method of etching a copper layer of a target object including, on the copper layer, a mask having a pattern to be transferred onto the copper layer is provided. The method includes etching the copper layer by using plasma of a first gas containing a hydrogen gas; and processing the target object by using plasma of a second gas containing a hydrogen gas and a gas (hereinafter, referred to as “deposition gas”) that is deposited on the target object. Further, the etching of the copper layer by using plasma of the first gas and the processing of the target object by using plasma of the second gas are repeated alternately.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 8, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Masato Kushibiki, Takashi Sone, Akitaka Shimizu, Fumiko Yamashita
  • Patent number: 9202894
    Abstract: One method includes forming trenches that define a fin structure including a first layer of a first semiconductor material and a second layer of a second semiconductor material positioned above a substrate, performing at least one etching process that exposes opposing end surfaces of the first and second layers, performing at least one recess etching process that removes end portions of the first layer and defines a cavity on opposite ends of the first layer, performing an epitaxial deposition process that fills each of the cavities with a support structure including a third semiconductor material, and performing an etching process to selectively remove remaining portions of the recessed first layer relative to the second layer and the support structures, the end portions of the second layer and the support structures defining pillars on opposite ends of the fin structure.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Hui Zang
  • Patent number: 9159612
    Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 13, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 9147692
    Abstract: A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: September 29, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 9139909
    Abstract: New and improved microwave plasma assisted reactors, for example chemical vapor deposition (MPCVD) reactors, are disclosed. The disclosed microwave plasma assisted reactors operate at pressures ranging from about 10 Torr to about 760 Torr. The disclosed microwave plasma assisted reactors include a movable lower sliding short and/or a reduced diameter conductive stage in a coaxial cavity of a plasma chamber. For a particular application, the lower sliding short position and/or the conductive stage diameter can be variably selected such that, relative to conventional reactors, the reactors can be tuned to operate over larger substrate areas, operate at higher pressures, and discharge absorbed power densities with increased diamond synthesis rates (carats per hour) and increased deposition uniformity.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: September 22, 2015
    Assignees: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITY, Fraunhofer USA
    Inventors: Jes Asmussen, Timothy Grotjohn, Donnie K. Reinhard, Thomas Schuelke, M. Kagan Yaran, Kadek W. Hemawan, Michael Becker, David King, Yajun Gu, Jing Lu
  • Patent number: 9129911
    Abstract: Boron-doped carbon-based hardmask etch processing is described. In an example, a method of patterning a film includes etching a boron-doped amorphous carbon layer with a plasma based on a combination of CH4/N2/O2 and a flourine-rich source such as, but not limited to, CF4, SF6 or C2F6.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: September 8, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kenny Linh Doan, Jong Mun Kim, Daisuke Shimizu
  • Patent number: 9105585
    Abstract: An etching method can selectively etch a second region formed of silicon oxide in a target object with respect to a first region formed of silicon in the target object. The etching method includes (a) processing the target object with plasma of a first processing gas containing fluorocarbon and fluorohydrocarbon by generating the plasma of the first processing gas with a microwave, and (b) after the processing of the target object with the plasma of the first processing gas, processing the target object with plasma of a second processing gas containing fluorocarbon by generating the plasma of the second processing gas with the microwave.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: August 11, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hironori Matsuoka, Hiroto Ohtake, Kosuke Kariu
  • Patent number: 9087788
    Abstract: Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: July 21, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Dongjiang Wang
  • Patent number: 9068265
    Abstract: Embodiments of the present invention provide a gas distribution plate assembly having protective elements for plasma processing. The gas distribution plate assembly includes a base plate having a front side and a backside, and a plurality of protective elements in direct contact with the base plate. The protective elements cover the front side of the base plate to protect the base plate from a plasma processing environment during use.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 30, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Dmitry Lubomirsky, Kartik Ramaswamy, Kallol Bera, Jennifer Sun
  • Patent number: 9064812
    Abstract: Embodiments of methods for etching a substrate include exposing the substrate to a first plasma formed from an inert gas; exposing the substrate to a second plasma formed from an oxygen-containing gas to form an oxide layer on a bottom and sides of a low aspect ratio feature and a high aspect ratio feature, wherein the oxide layer on the bottom of the low aspect ratio feature is thicker than on the bottom of the high aspect ratio feature; etching the oxide layer from the bottom of the low and high aspect ratio features with a third plasma to expose the bottom of the high aspect ratio feature while the bottom of the low aspect ratio feature remains covered; and exposing the substrate to a fourth plasma formed from a halogen-containing gas to etch the bottom of the low aspect ratio feature and the high aspect ratio feature.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: June 23, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jinsu Kim, Xiaosong Ji, Jinhan Choi, Ho Jeong Kim, Byungkook Kong, Hoon Sang Lee
  • Patent number: 9039909
    Abstract: There is provided a plasma etching method for forming a hole in a silicon oxide film formed on an etching stopper layer. The plasma etching method includes a main etching process for etching the silicon oxide film; and an etching process that is performed when at least a part of the etching stopper layer is exposed after the main etching process. The etching process includes a first etching process using a gaseous mixture of a C4F6 gas, an Ar gas and an O2 gas as the processing gas; and a second etching process using a gaseous mixture of a C4F8 gas, an Ar gas and an O2 gas or a gaseous mixture of a C3F8 gas, an Ar gas and an O2 gas as the processing gas. The first etching process and the second etching process are alternately performed plural times.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 26, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Nakagawa, Yuji Otsuka
  • Patent number: 9040427
    Abstract: A method of plasma etching a silicon carbide workpiece includes forming a mask on a surface of the silicon carbide workpiece, performing an initial plasma etch on the masked surface using a first set of process conditions, wherein the plasma is produced using an etchant gas mixture which includes i) oxygen and ii) at least one fluorine rich gas which is present in the etchant gas mixture at a volume ratio of less than 50%, and subsequently performing a bulk plasma etch process using a second set of process conditions which differ from the first set of process conditions.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: SPTS Technologies Limited
    Inventors: Huma Ashraf, Anthony Barker
  • Publication number: 20150140828
    Abstract: A method of etching an etching target layer containing polycrystalline silicon includes preparing a target object including the etching target layer and a mask formed on the etching target layer; and etching the etching target layer with the mask. Further, the mask includes a first mask portion formed of polycrystalline silicon and a second mask portion interposed between the first mask portion and the etching target layer and formed of silicon oxide. Furthermore, in the etching of the etching target layer, a first gas for etching the etching target layer, a second gas for removing a deposit adhering to the mask, and a third gas for protecting the first mask portion are supplied into a processing vessel in which the target object is accommodated, and plasma of these gases is generated within the processing vessel.
    Type: Application
    Filed: May 27, 2013
    Publication date: May 21, 2015
    Inventor: Masafumi Urakawa
  • Publication number: 20150132968
    Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 14, 2015
    Inventors: He Ren, Jang-Gyoo Yang, Jonghoon Baek, Anchuan Wang, Soonam Park, Saurabh Garg, Xinglong Chen, Nitin K. Ingle
  • Publication number: 20150132967
    Abstract: A method of processing a substrate using a substrate processing apparatus that has an electrostatic chuck including an insulating member inside which an electrode is included and provides a plasma process to a substrate mounted on the electrostatic chuck includes a first process of supplying a heat transfer gas having a second gas pressure to a back surface of the substrate while eliminating electric charges in the substrate using plasma of a process gas having a first gas pressure.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 14, 2015
    Inventors: Masafumi URAKAWA, Rui TAKAHASHI, Masahiro OGASAWARA
  • Patent number: 9029267
    Abstract: A method for controlling thermal cycling of a faraday shield in a plasma process chamber is provided. The method includes: performing a first plasma processing operation on a first wafer in the plasma process chamber; terminating the first plasma processing operation; performing a first wafer transfer operation to transfer the first wafer out of the chamber; and, during the first wafer transfer operation, applying power to a TCP coil under a plasma limiting condition.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: May 12, 2015
    Assignee: Lam Research Corporation
    Inventors: Sanket Sant, Raphael Casaes
  • Patent number: 9023733
    Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 5, 2015
    Assignees: IMEC, Tokyo Electron Limited
    Inventors: Boon Teik Chan, Shigeru Tahara
  • Publication number: 20150118854
    Abstract: As device feature size shrinks, plasma induced damage is a major concern affecting micro-electronic and nano-electronic device fabrication. Pulsed plasmas are a means of mitigating the damages. However, in conventional standard etch chemistry, the etch rate for pulsed plasmas is reduced significantly resulting in a substantially decreased throughput of tech processes. A new etch chemistry is disclosed in the present invention to increase throughput in pulsed plasma applications driven mainly by the molecular radicals.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 30, 2015
    Inventors: Sebastian U. Engelmann, Nathan P. Marchack, Masahiro Nakamura
  • Publication number: 20150118848
    Abstract: Higher overall etch rate and throughput for atomic layer removal (ALR) is achieved. The reaction is a self-limiting process, thus limiting the total amount of material that may be etched per cycle. By pumping down the process station between reacting operations, the reaction is partially “reset.” A higher overall etch rate is achieved by a multiple exposure with pump down ALR process.
    Type: Application
    Filed: November 3, 2014
    Publication date: April 30, 2015
    Inventors: Nerissa Draeger, Harald te Nijenhuis, Henner Meinhold, Bart van Schravendijk, Lakshmi Nittala
  • Patent number: 9017564
    Abstract: A plasma etching method performs plasma etching on a sample, which has laminated films containing a variable layer of a magnetic film, a barrier layer of an insulating material, and a fixed layer of a magnetic film, using a hard mask, which includes at least one of a Ta film and a TiN film. The plasma etching method includes a first step of etching the laminated films using N2 gas; and a second step of etching the laminated films after the first step using mixed gas of N2 gas and gas containing carbon elements.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 28, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Atsushi Yoshida, Naohiro Yamamoto, Makoto Suyama, Kentaro Yamada, Daisuke Fujita
  • Patent number: 9018102
    Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohammed Radwan, Matthias Zinke
  • Patent number: 9011707
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Publication number: 20150104950
    Abstract: A plasma processing method for processing a silicon containing film formed on a substrate including a step of removing a reaction product with a first plasma formed from a first gas containing halogen, hydrogen, and carbon in a case where the reaction product is formed when performing an etching process on the silicon containing film by using an etching mask having an etching pattern.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 16, 2015
    Inventor: Shunichi MIKAMI
  • Patent number: 8987143
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 24, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ratsamee Limdulpaiboon, Chi-I Lang, Sandip Niyogi, J. Watanabe
  • Publication number: 20150079798
    Abstract: Methods for etching an etching stop layer disposed on the substrate using a cyclical etching process are provided. In one embodiment, a method for etching an etching stop layer includes performing a treatment process on the substrate having a silicon nitride layer disposed thereon by supplying a treatment gas mixture into the processing chamber to treat the silicon nitride layer, and performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process etches the treated silicon nitride layer.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Inventors: Mang-Mang LING, Sean S. KANG, Jeremiah T. P. PENDER, Srinivas D. NEMANI, Bradley HOWARD
  • Publication number: 20150079800
    Abstract: According to one exemplary embodiment, a method of manufacturing a semiconductor device is provided, the method including: dry-etching an aluminum film containing silicon with a first etching gas containing halogen to decrease the thickness of the aluminum film; and dry-etching the aluminum film with a second etching gas containing inert gas.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tomoyuki Iguchi
  • Publication number: 20150079799
    Abstract: Methods for etching a dielectric barrier layer disposed on the substrate using a low temperature etching process along with a subsequent interface protection layer deposition process are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes transferring a substrate having a dielectric barrier layer disposed thereon into an etching processing chamber, performing a treatment process on the dielectric barrier layer, remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the treated dielectric barrier layer disposed on the substrate, plasma annealing the dielectric barrier layer to remove the dielectric barrier layer from the substrate, and forming an interface protection layer after the dielectric barrier is removed from the substrate.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Inventors: Srinivas D. NEMANI, Praburam GOPALRAJA, Takehito KOSHIZAWA
  • Patent number: 8980761
    Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH4F), and annealing the substrate to a first temperature to sublimate one or more volatile byproducts.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: David T. Or, Joshua Collins, Mei Chang
  • Patent number: 8980760
    Abstract: Methods and apparatus for controlling a plasma are provided herein. In some embodiments, a method may include supplying a first RF signal having a first frequency and a first period from an RF power source to a first electrode, wherein the first period is a first integer number of first cycles at the first frequency; supplying a second RF signal having a second frequency and a second period from the RF power source to the first electrode, wherein the second period is a second integer number of second cycles at the second frequency and wherein a first multiplicative product of the first frequency and the first integer number is equal to a second multiplicative product of the second frequency and the second integer number; and controlling the phase between the first and second periods to control an ion energy distribution of the plasma formed in a process chamber.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Ankur Agarwal, Ajit Balakrishna, Shahid Rauf
  • Patent number: 8980758
    Abstract: Methods for etching an etching stop layer disposed on the substrate using a cyclical etching process are provided. In one embodiment, a method for etching an etching stop layer includes performing a treatment process on the substrate having a silicon nitride layer disposed thereon by supplying a treatment gas mixture into the processing chamber to treat the silicon nitride layer, and performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process etches the treated silicon nitride layer.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Mang-Mang Ling, Sean S. Kang, Jeremiah T. P. Pender, Srinivas D. Nemani, Bradley Howard
  • Patent number: 8974684
    Abstract: Methods for etching a substrate are provided herein. In some embodiments, a method of etching a substrate may include generating a plasma by providing only a first RF signal having a first frequency and a first duty cycle; applying only a second RF signal to bias the plasma towards the substrate, wherein the second RF signal has the first frequency and a second duty cycle different than the first duty cycle; adjusting a phase variance between the first and second RF signals to control an ion energy distribution in the plasma; and etching the substrate with the plasma.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Samer Banna, Ankur Agarwal
  • Patent number: 8975190
    Abstract: A plasma processing method includes a surface improving step of improving a surface of the photoresist film by performing plasma processing using a hydrogen-containing gas as a processing gas and an etching step of etching the SiON film by performing plasma processing using a processing gas including a gas containing a CHF-based gas and a chlorine-containing gas while using as a mask the photoresist film having the improved surface.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 8975188
    Abstract: A plasma etching method is provided for forming a hole using a first processing gas to etch a silicon layer of a substrate to be processed including a silicon oxide film that is formed into a predetermined pattern. The method includes a first depositing step (S11) of depositing a protective film on a surface of the silicon oxide film using a second processing gas containing carbon monoxide gas, a first etching step (S12) of etching the silicon layer using the first processing gas, a second depositing step (S13) of depositing the protective film on a side wall of a hole etched by the first etching step using the second processing gas, and a second etching step (S14) of further etching the silicon layer using the first processing gas. The second depositing step (S13) and the second etching step (S14) are alternately repeated at least two times each.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Yusuke Hirayama, Kazuhito Tohnoe
  • Publication number: 20150064920
    Abstract: A plasma processing system and method includes a processing chamber, and a plasma processing volume included therein. The plasma processing volume having a volume less than the processing chamber. The plasma processing volume being defined by a top electrode, a substrate support surface opposing the surface of the top electrode and a plasma confinement structure including at least one outlet port. A conductance control structure is movably disposed proximate to the at least one outlet port and capable of restricting an outlet flow through the at least one outlet port to a first flow rate and capable of increasing the outlet flow through the at least one outlet port to a second flow rate, wherein the conductance control structure restricts the outlet flow rate moves between the first flow rate and the second flow rate corresponding to a selected processing state set by the controller during a plasma process.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Harmeet Singh, Sang Ki Nam
  • Patent number: 8969211
    Abstract: The present invention provides a plasma processing method that uses a plasma processing apparatus including a plasma processing chamber in which a sample is plasma processed, a first radio-frequency power supply that supplies a first radio-frequency power for generating plasma, and a second radio-frequency power supply that supplies a second radio-frequency power to a sample stage on which the sample is mounted, wherein the plasma processing method includes the steps of modulating the first radio-frequency power by a first pulse; and controlling a plasma dissociation state to create a desired dissociation state by gradually controlling a duty ratio of the first pulse as a plasma processing time elapses.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Satoru Muto, Tetsuo Ono, Yasuo Ohgoshi, Hirofumi Eitoku
  • Patent number: 8968588
    Abstract: A surface wave plasma (SWP) source couples pulsed microwave (MW) energy into a processing chamber through, for example, a radial line slot antenna, to result in a low mean electron energy (Te). To prevent impingement of the microwave energy onto the surface of a substrate when plasma density is low between pulses, an ICP source, such as a helical inductive source, a planar RF coil, or other inductively coupled source, is provided between the SWP source and the substrate to produce plasma that is opaque to microwave energy. The ICP source can also be pulsed in synchronism with the pulsing of the MW plasma in phase with the ramping up of the MW pulses. The ICP also adds an edge dense distribution of plasma to a generally chamber centric MW plasma to improve plasma uniformity.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 3, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Jianping Zhao, Lee Chen, Vincent M. Donnelly, Demetre J. Economou, Merritt Funk, Radha Sundararajan
  • Patent number: 8962488
    Abstract: Methods for processing a substrate are provided herein. In some embodiments, a method of etching a dielectric layer includes generating a plasma by pulsing a first RF source signal having a first duty cycle; applying a second RF bias signal having a second duty cycle to the plasma; applying a third RF bias signal having a third duty cycle to the plasma, wherein the first, second, and third signals are synchronized; adjusting a phase variance between the first RF source signal and at least one of the second or third RF bias signals to control at least one of plasma ion density non-uniformity in the plasma or charge build-up on the dielectric layer; and etching the dielectric layer with the plasma.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Bryan Liao, Katsumasa Kawasaki, Yashaswini Pattar, Sergio Fukuda Shoji, Duy D. Nguyen, Kartik Ramaswamy, Ankur Agarwal, Phillip Stout, Shahid Rauf
  • Patent number: 8961804
    Abstract: The present invention provides a method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss. In one embodiment, the method includes etching a first substrate through a patterned mask layer in a plasma etch chamber, the first substrate having a backside disposed on a substrate support and a front side facing away from the substrate support, directing a first radiation source from the backside of the first substrate to a first area covered by the patterned mask layer, directing a second radiation source from the backside of the first substrate to a second area uncovered by the patterned mask layer, collecting a first signal reflected from the first area covered by the patterned mask layer, collecting a second signal reflected from the second area uncovered by the patterned mask layer, and analyzing the combined first and the second signal.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 24, 2015
    Assignee: Applied Materials, Inc.
    Inventor: Michael N. Grimbergen
  • Patent number: 8962489
    Abstract: Disclosed is a method for etching a film contains cobalt and palladium is provided. A hard mask is provided on the film. The method film includes a process “a” of etching the film by ion sputter etching, a process “b” of exposing a workpiece to plasma of a first gas containing halogen elements after the process “a” of etching of the film, a process “c” of exposing the workpiece to plasma of a second gas containing carbons after the process “b” of exposing the workpiece to the plasma of the first gas, and a process “d” of exposing the workpiece to plasma of a third gas containing a noble gas after the process “c” of exposing the workpiece to the plasma of the second gas. In the method, a temperature of a placement table on which the workpiece is placed is set to a first temperature of 10° C. or less in the process “a”, process “b” and process “c”.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Masato Kushibiki
  • Publication number: 20150044877
    Abstract: An etching method can improve etching accuracy as well as secure selectivity when forming a dummy gate of a fin-type field effect transistor. In the etching method, the dummy gate of a fin-type field effect transistor is formed with a target object. In the etching method, a gate material deposited between multiple fins is etched by using surface wave plasma. A pressure in the etching method is 50 mTorr (6.67 Pa) or more, a frequency of a power to be applied to a mounting table configured to mount thereon the target object is in a range of 10 Hz or more to 200 Hz or less, and the power is pulse-modulated such that a duty ratio as a ratio of an ON-time to a pulse cycle is 50% or less.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 12, 2015
    Inventors: Hiroto Ohtake, Akinori Kitamura, Hironori Matsuoka, Yoko Noto
  • Publication number: 20150044878
    Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Inventors: John Patrick Holland, Peter L.G. Ventzek, Harmeet Singh, Richard Gottscho
  • Patent number: 8952765
    Abstract: A radio frequency generator includes a power control module, a frequency control module and a pulse generating module. The power control module is configured to generate a power signal indicating power levels for target states of a power amplifier. The frequency control module is configured to generate a frequency signal indicating frequencies for the target states of the power amplifier. The pulse generating module is configured to (i) supply an output signal to the power amplifier, (ii) recall at least one of a latest power level or a latest frequency for one of the target states of the power amplifier, and (iii) adjust a current power level and a current frequency of the output signal from a first state to a second state based on the power signal, the frequency signal, and at least one of the latest power level and the latest frequency of the power amplifier.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 10, 2015
    Assignee: MKS Instruments, Inc.
    Inventors: Larry J. Fisk, II, Amish Rughoonundon