Including Change In Etch Influencing Parameter (e.g., Energizing Power, Etchant Composition, Temperature, Etc.) Patents (Class 438/714)
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Patent number: 8951428Abstract: This invention presents a method for the fabrication of periodic nanostructures on polymeric surfaces by means of plasma processing, which method comprises the following steps: (i) provision of a homogeneous organic polymer (such as PMMA, or PET, or PEEK, or PS, or PE, or COC) or inorganic polymer (such as PDMS or ORMOCER); (ii) exposure of the polymer to an etching plasma such as oxygen (O2) or sulphur hexafluoride (SF6) or a mixture of oxygen (O2) and sulphur hexafluoride (SF6), or mixtures of etching gases with inert gases such as any Noble gas (Ar, He, Ne, Xe).Type: GrantFiled: June 15, 2009Date of Patent: February 10, 2015Inventors: Evangelos Gogolides, Angeliki Tserepi, Vassilios Constantoudis, Nikolaos Vourdas, Georgios Boulousis, Maria-Elena Vlachopoulou, Aikaterini Tsougeni, Dimitrios Kontziampasis
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Publication number: 20150037981Abstract: A method for etching a layer in a plasma chamber with an inner injection zone gas feed and an outer injection zone gas feed is provided. The layer is placed in the plasma chamber. A pulsed etch gas is provided from the inner injection zone gas feed at a first frequency, wherein flow of pulsed etch gas from the inner injection zone gas feed is ramped down to zero. The pulsed etch gas is provided from the outer injection zone gas feed at the first frequency and simultaneous with and out of phase with the pulsed etch gas from the inner injection zone gas feed. The etch gas is formed into a plasma to etch the layer, simultaneous with the providing the pulsed etch gas from the inner injection zone gas feed and providing the pulsed gas from the outer interjection zone gas feed.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Inventors: Saravanapriyan SRIRAMAN, Alexander PATERSON
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Patent number: 8946030Abstract: Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.Type: GrantFiled: December 17, 2013Date of Patent: February 3, 2015Assignee: Tokyo Electron LimitedInventors: Motoki Noro, Tai-Chuan Lin, Shinji Kawada
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Patent number: 8940643Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.Type: GrantFiled: August 20, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chi Ko, Chih-Hao Chen, Keng-Chu Lin
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Publication number: 20150017810Abstract: The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber.Type: ApplicationFiled: July 11, 2013Publication date: January 15, 2015Inventor: Joydeep Guha
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Patent number: 8932947Abstract: Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.Type: GrantFiled: July 23, 2013Date of Patent: January 13, 2015Assignee: Applied Materials, Inc.Inventors: Joo Won Han, Kee Young Cho, Han Soo Cho, Sang Wook Kim, Anisul H. Khan
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Publication number: 20150004794Abstract: A method of controlling a temperature is provided. In the method, a plasma process is performed in a processing chamber on an object to be processed placed on an electrostatic chuck configured to have its temperature adjustable. The electrostatic chuck is controlled to have a first temperature. The temperature of the electrostatic chuck is controlled in a step-by-step manner so as to change from the first temperature to a second temperature that is lower than the first temperature after performing the plasma process. An inside of the processing chamber is purged with an inactive gas after performing the plasma process.Type: ApplicationFiled: June 19, 2014Publication date: January 1, 2015Inventor: Akitoshi HARADA
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Patent number: 8921232Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.Type: GrantFiled: February 25, 2014Date of Patent: December 30, 2014Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura
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Publication number: 20140370715Abstract: Provided are a plasma processing method and a substrate processing apparatus. The plasma processing method includes mounting at least one first plasma source and at least one second plasma source on a chamber, supplying a first gas to the first plasma source, supplying a second gas different from the first gas to the second plasma source, applying power to the first plasma source to generate first plasma, applying power to the second plasma source to generate second plasma, and processing a substrate disposed inside the chamber using the first and second plasma.Type: ApplicationFiled: August 29, 2014Publication date: December 18, 2014Inventors: Seng-Hyun CHUNG, Hyang-Joo LEE
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Patent number: 8912633Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.Type: GrantFiled: September 7, 2012Date of Patent: December 16, 2014Assignee: Lam Research CorporationInventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
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Patent number: 8912835Abstract: A method for controlling pulsed power that includes measuring a first pulse of power from a power amplifier to obtain data. The method also includes generating a first signal to adjust a second pulse of delivered power, the first signal correlated to the data to minimize a power difference between a power set point and a substantially stable portion of the second pulse. The method also includes generating a second signal to adjust the second pulse of delivered power, the second signal correlated to the data to minimize an amplitude difference between a peak of the second pulse and the substantially stable portion of the second pulse.Type: GrantFiled: January 9, 2014Date of Patent: December 16, 2014Assignee: MKS Instruments Inc.Inventors: Siddarth Nagarkatti, Feng Tian, David Lam, Abdul Rashid, Souheil Benzerrouk, Ilya Bystryak, David Menzer, Jack J. Schuss, Jesse E. Ambrosina
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Publication number: 20140363979Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH4F), and annealing the substrate to a first temperature to sublimate one or more volatile byproducts.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Inventors: David T. OR, Joshua COLLINS, Mei CHANG
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Patent number: 8906810Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.Type: GrantFiled: May 7, 2013Date of Patent: December 9, 2014Assignee: Lam Research CorporationInventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
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Patent number: 8900402Abstract: A semiconductor substrate processing system includes a substrate support defined to support a substrate in exposure to a processing region. The system also includes a first plasma chamber defined to generate a first plasma and supply reactive constituents of the first plasma to the processing region. The system also includes a second plasma chamber defined to generate a second plasma and supply reactive constituents of the second plasma to the processing region. The first and second plasma chambers are defined to be independently controlled.Type: GrantFiled: May 10, 2011Date of Patent: December 2, 2014Assignee: Lam Research CorporationInventors: John Patrick Holland, Peter L. G. Ventzek, Harmeet Singh, Richard Gottscho
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Publication number: 20140342571Abstract: A wafer etching apparatus and a wafer etching method using the wafer etching apparatus, which are capable of etching Si wafer in a dry etching method, are disclosed. According to the wafer etching apparatus and the wafer etching method, the capacitively coupled plasma unit or the inductively coupled plasma unit and the remote plasma unit are included together to etch wafer in a high speed and to reduce etching operation time. Additionally, the chuck has an upper surface with roughness so that the wafer can be cooled down through a helium gas provided to the wafer through a minute space between the upper surface and the wafer. Therefore, unwanted plasma which is generated in the groove in the conventional wafer etching apparatus is prevented to prevent damage of the wafer.Type: ApplicationFiled: October 23, 2012Publication date: November 20, 2014Applicant: RORZE SYSTEMS CORPORATIONInventors: Saeng-Man Park, Seung-Bae Oh
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Publication number: 20140342570Abstract: The disclosure concerns a plasma-enhanced etch process in which chamber pressure and/or RF power level is ramped throughout the etch process.Type: ApplicationFiled: June 7, 2013Publication date: November 20, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Kenny Linh Doan, Daisuke Shimizu, Jong Mun Kim, Sergio Fukuda Shoji, Justin Phi, Katsumasa Kawasaki, Kartik Ramaswamy, James P. Cruse
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Patent number: 8888948Abstract: An apparatus for controlling a plasma etching process includes plasma control structure that can vary a size of a plasma flow passage, vary a speed of plasma flowing through the plasma flow passage, vary plasma concentration flowing through the plasma flow passage, or a combination thereof.Type: GrantFiled: September 21, 2012Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Chi-Lun Lu
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Publication number: 20140335697Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.Type: ApplicationFiled: May 7, 2013Publication date: November 13, 2014Applicant: Lam Research CorporationInventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
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Publication number: 20140335679Abstract: In some embodiments, a method for etching features into a substrate may include exposing a substrate having a photoresist layer disposed atop the substrate to a first process gas to form a polymer containing layer atop sidewalls and a bottom of a feature formed in the photoresist layer, wherein the first process gas is selectively provided to a first area of the substrate via a first set of gas nozzles disposed within a process chamber and; exposing the substrate to a second process gas having substantially no oxygen to etch the feature into the substrate, wherein the second process gas is selectively provided to a second area of the substrate via a second set of gas nozzles disposed in the process chamber.Type: ApplicationFiled: July 9, 2013Publication date: November 13, 2014Inventors: TONG LIU, DAVID REYLAND, ROHIT MISHRA, KHALID MOHIUDDIN SIRAJUDDIN, MADHAVA RAO YALAMANCHILI, AJAY KUMAR
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Patent number: 8883650Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.Type: GrantFiled: January 24, 2008Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
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Publication number: 20140329391Abstract: A method for etching features with a continuous plasma is provided. A first plasma process is provided, comprising providing a flow of a first process gas into a process chamber, maintaining the continuous plasma, and stopping the flow of the first process gas into the process chamber. A transition process is provided, comprising providing a flow of a transition gas into the process chamber, maintaining the continuous plasma, and stopping the flow of the transition gas into the process chamber. A second plasma process is provided, comprising providing a flow of a second process gas into the process chamber, maintaining the continuous plasma, and stopping the second process gas into the process chamber.Type: ApplicationFiled: May 1, 2013Publication date: November 6, 2014Applicant: Lam Research CorporationInventor: Lam Research Corporation
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Patent number: 8871107Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan
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Patent number: 8871105Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.Type: GrantFiled: March 9, 2012Date of Patent: October 28, 2014Assignee: Lam Research CorporationInventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
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Patent number: 8865501Abstract: The object of the present invention is to provide a method of fabricating a thermoelectric material and a thermoelectric material fabricated thereby. According to the present invention, since carbon nanotubes with no surface treatment are dispersed in the alloy, electrical resistivity decreases and electrical conductivity increases in comparison to surface-treated carbon nanotubes and an amount of thermal conductivity decreased is the same as that in the case of using surface-treated carbon nanotubes, and thus, a ZT value, a thermoelectric figure of merit, is improved. A separate reducing agent is not used and an organic solvent having reducing powder is used to improve economic factors related to material costs and process steps, and carbon nanotubes may be dispersed in the thermoelectric material without mechanical milling.Type: GrantFiled: June 25, 2013Date of Patent: October 21, 2014Assignee: Korea Institute of Machinery and MaterialsInventor: Kyung Tae Kim
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Publication number: 20140308815Abstract: The etching method of the present invention comprises first and second etching steps (S1, S3) having different types of films to be etched and different types of process gases. During a transition from the first etching step (S1) to the second etching step (S3), a first switching process step (S2) is performed in which the process container is filled with a cleaning gas and the cleaning gas is turned into a plasma to remove the reaction product deposited in the process container in the first etching step. During a transition from the second etching step (S3) to the first etching step (S1), a second switching process step (S4) is performed in which the process container is filled with a cleaning gas and the cleaning gas is turned into a plasma to remove the reaction product deposited in the process container in the second etching step.Type: ApplicationFiled: July 12, 2012Publication date: October 16, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Takashi Dokan, Masaru Sasaki, Hikaru Kamata
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Publication number: 20140302678Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.Type: ApplicationFiled: February 19, 2014Publication date: October 9, 2014Inventors: Alex Paterson, Do Young Kim, Gowri Kamarthy, Helene Del Puppo, Jen-Kan Yu, Monica Titus, Radhika Mani, Noel Yui Sun, Nicolas Gani, Yoshie Kimura, Ting-Ying Chung
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Patent number: 8853096Abstract: The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a photoresist film is formed on a surface of the substrate. Third, a nano-pattern is formed on the photoresist film by nano-imprint lithography. Fourth, the photoresist film is etched to form a patterned photoresist layer. Fifth, a mask layer is covered on the patterned photoresist layer and the surface of the substrate exposed to the patterned photoresist layer. Sixth, the patterned photoresist layer and the mask layer thereon are removed to form a patterned mask layer. Seventh, the substrate is etched through the patterned mask layer by reactive ion etching, wherein etching gases includes carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) and argon (Ar2). Finally, the patterned mask layer is removed.Type: GrantFiled: October 23, 2012Date of Patent: October 7, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen
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Patent number: 8845916Abstract: A method for manufacturing a glass plate using laser etching includes a dipping step for dipping a glass plate, which will be etched, into an etching solution, a patterning step for irradiating laser to the glass plate dipped in the etching solution to form a pattern therein, and a washing step for washing the patterned glass plate. This method allows making a plate with a high aspect ratio and fine line widths in comparison to a conventional plate manufacturing method using photoresist for etching, and also ensures more efficient energy consumption and higher etching efficiency rather than an etching method using laser only.Type: GrantFiled: September 26, 2008Date of Patent: September 30, 2014Assignee: LG Chem, Ltd.Inventor: Bu-Gon Shin
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Publication number: 20140287591Abstract: Disclosed is a method for etching a film contains cobalt and palladium is provided. A hard mask is provided on the film. The method film includes a process “a” of etching the film by ion sputter etching, a process “b” of exposing a workpiece to plasma of a first gas containing halogen elements after the process “a” of etching of the film, a process “c” of exposing the workpiece to plasma of a second gas containing carbons after the process “b” of exposing the workpiece to the plasma of the first gas, and a process “d” of exposing the workpiece to plasma of a third gas containing a noble gas after the process “c” of exposing the workpiece to the plasma of the second gas. In the method, a temperature of a placement table on which the workpiece is placed is set to a first temperature of 10° C. or less in the process “a”, process “b” and process “c”.Type: ApplicationFiled: March 18, 2014Publication date: September 25, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi NISHIMURA, Masato KUSHIBIKI
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Publication number: 20140273487Abstract: In one aspect, a plasma etching apparatus is disclosed. The plasma etching apparatus includes a chamber body having a process chamber adapted to receive a substrate, an RF source coupled to an RF electrode, a pedestal located in the processing chamber and adapted to support a substrate, a plurality of conductive pins adapted to contact and support the substrate during processing, and a DC bias source electrically coupled to the plurality of conductive pins. Etching methods are provided, as are numerous other aspects.Type: ApplicationFiled: March 7, 2014Publication date: September 18, 2014Inventors: Subhash Deshmukh, He Ren, Jingjing Liu
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Publication number: 20140256149Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Alok Ranjan, Akiteru Ko
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Patent number: 8828883Abstract: Apparatuses and methods for processing substrates are disclosed. A processing apparatus includes a chamber for generating a plasma therein, an electrode associated with the chamber, and a signal generator coupled to the electrode. The signal generator applies a DC pulse to the electrode with sufficient amplitude and sufficient duty cycle of an on-time and an off-time to cause events within the chamber. A plasma is generated from a gas in the chamber responsive to the amplitude of the DC pulse. Energetic ions are generated by accelerating ions of the plasma toward a substrate in the chamber in response to the amplitude of the DC pulse during the on-time. Some of the energetic ions are neutralized to energetic neutrals in response to the DC pulse during the off-time. Some of the energetic neutrals impact the substrate with sufficient energy to cause a chemical reaction on the substrate.Type: GrantFiled: August 24, 2010Date of Patent: September 9, 2014Assignee: Micron Technology, Inc.Inventor: Neal R. Rueger
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Patent number: 8828259Abstract: A method for automatically performing power matching using a mechanical RF match during substrate processing is provided. The method includes providing a plurality of parameters for the substrate processing wherein the plurality of parameters including at least a predefined number of learning cycles. The method also includes setting the mechanical RF match to operate in a mechanical tuning mode. The method further includes providing a first set of instructions to the substrate processing to ignore a predefined number of cycles of Rapid Alternating Process RAP steps. The method yet also includes operating the mechanical RF match in the mechanical tuning mode for the predefined number of learning cycles. The method yet further includes determining a set of optimal capacitor values. The method moreover includes providing a second set of instructions to a power generator to operate in a frequency tuning mode.Type: GrantFiled: July 7, 2011Date of Patent: September 9, 2014Assignee: Lam Research CorporationInventor: Arthur H. Sato
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Patent number: 8828248Abstract: Write heads may be formed by reactive ion etching (RIE) a dielectric mask and then reactive ion etching a polymeric underlayer. The first RIE affects the second RIE. The first portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 1.3 to 2, a gas flow ratio of CF4 to He between 2.2 and about 3, and a ratio of RF source power to RF bias power between about 10 and about 16. The second portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 0.3 to 0.8, a gas flow ratio of CF4 to He between about 1.2 and about 1.8, and a ratio of RF source power to RF bias between about 22 to 28. With the above parameters, the dielectric mask can be formed with minimized damage on the underlayer.Type: GrantFiled: February 1, 2013Date of Patent: September 9, 2014Assignee: HGST Netherlands B.VInventors: Guomin Mao, Satyanarayana Myneni, Aron Pentek, Xiaoye Zhao
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Patent number: 8822345Abstract: A plasma processing apparatus includes a gas distribution member which supplies a process gas and radio frequency (RF) power to a showerhead electrode. The gas distribution member can include multiple gas passages which supply the same process gas or different process gases at the same or different flow rates to one or more plenums at the backside of the showerhead electrode. The gas distribution member provides a desired process gas distribution to be achieved across a semiconductor substrate processed in a gap between the showerhead electrode and a bottom electrode on which the substrate is supported.Type: GrantFiled: November 7, 2012Date of Patent: September 2, 2014Assignee: Lam Research CorporationInventors: Rajinder Dhindsa, Eric Lenz
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Patent number: 8822341Abstract: A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.Type: GrantFiled: June 20, 2011Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Ho Jeon, Dong-Hyun Kim, Je-Woo Han, Kyoung-Sub Shin
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Patent number: 8821743Abstract: The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a patterned mask layer is formed on a surface of the substrate. Third, the substrate with the patterned mask layer is placed in a microwave plasma system. Fourth, a plurality of etching gases are guided into the microwave plasma system simultaneously to etch the substrate through three stages. The etching gas includes carbon tetrafluoride (CF4), argon (Ar2), and sulfur hexafluoride (SF6). Finally, the patterned mask layer is removed.Type: GrantFiled: October 23, 2012Date of Patent: September 2, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen, Shou-Shan Fan
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Patent number: 8815712Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.Type: GrantFiled: March 7, 2012Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Tien Wan, You-Ru Lin, Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Publication number: 20140235062Abstract: Disclosed is a plasma processing method which includes a gas supplying process, a power supplying process, and an etching process. In the gas supplying process, a processing gas is supplied into a processing container in which an object to be processed is disposed. In the power supplying process, a plasma generating power of a frequency ranging from about 100 MHz to about 150 MHz as a power for generating plasma of the processing gas supplied into the processing container, and a biasing power which is a power having a frequency lower than that of the plasma generating power are supplied. In the etching process, the object to be processed is etched by the plasma of the processing gas while the biasing power is pulse-modulated so that the duty ratio ranges from about 10% to about 70% and the frequency ranges from about 5 kHz to about 20 kHz.Type: ApplicationFiled: February 18, 2014Publication date: August 21, 2014Applicant: TOKYO ELECTRON LIMITEDInventor: Masafumi URAKAWA
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Patent number: 8809199Abstract: A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern. The method includes preparing a film stack on a substrate, the film stack containing a SiN film on the substrate and a mask pattern on the SiN film, forming a plasma from a process gas containing HBr gas, O2 gas, and a carbon-fluorine-containing gas, applying pulsed RF bias power to the substrate, and transferring the mask pattern to the SiN film by exposing the film stack to the plasma.Type: GrantFiled: February 12, 2011Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventor: Tetsuya Nishizuka
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Patent number: 8809196Abstract: A method for transferring a feature pattern to a thin film on a substrate is described. The method comprises disposing a substrate comprising one or more mask layers overlying a thin film in a plasma processing system, and forming a feature pattern in the one or more mask layers. The method further comprises transferring the feature pattern in the one or more mask layers to the thin film by: performing a first plasma etching process at a first pressure less than about 80 mtorr, and performing a second plasma etching process at a second pressure greater than about 80 mtorr.Type: GrantFiled: January 14, 2009Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventor: Kelvin Kyaw Zin
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Patent number: 8809198Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.Type: GrantFiled: December 30, 2009Date of Patent: August 19, 2014Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Paul Morgan, Max Hineman
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Patent number: 8809197Abstract: In a control method, a first processing is performed on an object to be processed by controlling a temperature of a base to a first temperature and controlling a temperature of an electrostatic chuck that is disposed on a mounting surface of the base so as to mount thereon the object to be processed and has a heater installed therein to a second temperature. A second processing is performed on the object by controlling a temperature of the base to a third temperature and controlling a temperature of the electrostatic chuck to a fourth temperature by a heater. In the control method, a difference between the first temperature and the second temperature and a difference between the third temperature and the fourth temperature are within a tolerable temperature of the junction layer for bonding the base and the electrostatic chuck.Type: GrantFiled: August 29, 2013Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventor: Atsuhiko Tabuchi
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Patent number: 8802545Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.Type: GrantFiled: March 5, 2012Date of Patent: August 12, 2014Assignee: Plasma-Therm LLCInventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
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Patent number: 8796155Abstract: A method of fabricating a substrate includes forming spaced first features over a substrate. An alterable material is deposited over the spaced first features and the alterable material is altered with material from the spaced first features to form altered material on sidewalls of the spaced first features. A first material is deposited over the altered material, and is of some different composition from that of the altered material. The first material is etched to expose the altered material and spaced second features comprising the first material are formed on sidewalls of the altered material. Then, the altered material is etched from between the spaced second features and the spaced first features. The substrate is processed through a mask pattern comprising the spaced first features and the spaced second features. Other embodiments are disclosed.Type: GrantFiled: December 4, 2008Date of Patent: August 5, 2014Assignee: Micron Technology, Inc.Inventors: Scott Sills, Gurtej S. Sandhu, Anton deVilliers
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Patent number: 8796148Abstract: A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.Type: GrantFiled: August 30, 2012Date of Patent: August 5, 2014Assignee: STMicroelectronics (Crolles 2) SASInventors: François Leverd, Laurent Favennec, Arnaud Tournier
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Patent number: 8791028Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer.Type: GrantFiled: August 10, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Kimitoshi Okano
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Patent number: 8791027Abstract: A problem of a resist mask collapse due to a plasma process is solved. In a method of manufacturing a semiconductor device including steps of a plasma process to a sample having a mask made of an organic material, the plasma process includes a first step of a plasma process under a gas containing any of fluorine, oxygen, or nitrogen, or containing all of them, and a second step of the plasma process under a gas containing a rare gas without containing any of fluorine, oxygen, and nitrogen, and the first step and the second step are repeated.Type: GrantFiled: June 4, 2010Date of Patent: July 29, 2014Assignee: Hitachi, Ltd.Inventors: Naoyuki Kofuji, Hideo Miura
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Patent number: 8785331Abstract: The present invention discloses a method for replacing chlorine atoms on a film layer. More particularly, sufficient replacement ions for replacing the chlorine atoms are formed in a plasma process by reducing a volume ratio of a gas in a gas mixture (i.e. the film layer may be etched with the ions formed by dissociation of the gas) and dissociation of the gas mixture further decreases the etching reaction to the film layer in a process for replacing the chlorine atoms. In comparison to a conventional process by pure oxygen, the present invention can improve the prior art re-etching problem to avoid affecting an electric property of a thin film transistor, also has an advantage of manufacturing time reduction for an increased production yield.Type: GrantFiled: June 8, 2012Date of Patent: July 22, 2014Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventor: Yang-Ling Cheng
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Patent number: 8778205Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.Type: GrantFiled: October 14, 2009Date of Patent: July 15, 2014Assignee: Tokyo Electron LimitedInventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita