Abstract: A tungsten silicide (WSi) film is formed of tungsten hexafluoride (WF6) and dichlorosilane (SiCl2) as main raw material on a polysilicon film by the CVD method. At the final stage of this film forming process, supply of tungsten hexafluoride is terminated to relax internal stresses. As a result, on the tungsten silicide film, an Si-rich tungsten silicide film containing chlorine ions in a high concentration is formed. Then, before coating a chemical amplification photoresist, these films along with a silicon substrate are soaked in an etching liquid containing hydrogen peroxide to remove the Si-rich tungsten silicide film so that generation of ammonia chloride, which suppresses an alkali developing action, can be controlled. Thus the tungsten silicide film can be patterned by photolithography without pattern defects.

Abstract: According to the disclosed method, there is provided a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer. Said refractory metal and doped polysilicon layers will form a polycide layer under subsequent thermal treatments. First, a sacrificial layer of a dielectric material such as oxynitride is deposited onto the structure. Oxynitride is impervious to UV radiation and has excellent conformal properties. Then, a layer of a photoresist material is deposited onto the structure and patterned to form a mask. Now the dielectric and top Si3N4 layers are anisotropically etched using the photoresist mask. The mask is stripped and the refractory metal and doped polysilicon layers are anisotropically dry etched down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: A method for forming a semiconductor device having a capacitor, a resistor and a MOS transistor with characteristics conforming to design. To this end, a polysilicon film (4), a capacitor-dielectric/insulating film (5), a polysilicon film (6) are deposited, and an upper electrode (7) of the capacitor is formed from the polysilicon film (6), and edge portions (7a) of the upper electrode (7) are oxidized. On top of this, an inorganic anti-reflection coating film (9) and a CAP oxide film (10) are deposited and etched to form a mask pattern (12) for forming the capacitor and the resistor. On the other hand, a tungsten silicide film (13), an inorganic anti-reflection coating film (14) and a CAP oxide film (15) are deposited and etched to form a mask pattern (17) for forming a gate electrode. The polysilicon film (4) is etched by using the mask patterns (12) and (17), leaving behind the tungsten silicide film (13) beneath the mask pattern 17.

Abstract: A method of fabricating a semiconductor device in which the bitlines and the bitline contacts are fabricated utilizing a single masking step in which line-space resist patterns are employed in defining the regions for the bitlines and the bitline contacts. The method utilizes a first line-space resist pattern and a second line-space resist pattern which is perpendicularly aligned to the first line-space resist pattern to form bitlines that are self-aligned to the bitline contacts.

Abstract: A method of forming a cobalt silicide layer on a silicon region comprises the steps of: forming a TEOS oxide film on a surface of the silicon region; carrying out an ion-implantation process for implanting ions through the TEOS oxide film into the silicon region; carrying out a heat treatment to activate the ions implanted in the silicon region, whereby a silicidation reaction inhibitor layer concurrently formed on an interface between the TEOS oxide film and the surface of the silicon region; carrying out a dry etching to remove laminations of the TEOS oxide film and the silicidation reaction inhibitor layer from the surface of the silicon region; carrying out a cleaning process for cleaning the surface of the silicon region by subjecting the surface of the silicon region to an acidic solution and subsequently to a diluted hydrofluoric acid solution; and forming a cobalt silicide layer on the surface of the silicon region.

Abstract: There is described a method of forming a semiconductor device in which a contact plug penetrates through an interlayer insulating film. The method is capable of formation of a multilayer wiring structure of small resistance. Contact holes are formed in an interlayer oxide film laid on a silicon substrate by etching, through use of a CF-based gas plasma. An organic layer deposited at the bottom of the contact holes is removed through cleaning etching through use of a plasma of a mixed gas consisting of CF4 and O2. After removal of the organic layer, a conductive contact plug is formed in each of the contact holes.

Abstract: A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).

Abstract: A method of forming a gate electrode with a titanium polycide structure capable of preventing abnormal oxidation of the gate electrode when performing gate re-oxidation process, is disclosed. In the present invention, after forming a gate electrode having a stacked structure of a polysilicon layer and a titanium silicide layer, thermal-treating is performed under nitrogen atmosphere to form a TiN layer on the side wall of the titanium silicide layer, considering as silicon content of the titanium silicide layer is high, abnormal oxidation decreases. At this time, a titanium silicide layer having deficient Ti is formed on the side wall of the titanium silicide layer adjacent to the TiN layer. Therefore, after removing the TiN layer, the side wall of the titanium silicide layer having excessive Si (or deficient Ti) is exposed. Thereafter, gate re-oxidation process is performed. At this time, abnormal oxidation of the titanium silicide layer is prevented by the titanium silicide layer having excessive silicon.

Abstract: Sidewall spacers, adjacent a gate electrode and source/drain regions of a MOS transistor are formed of a dielectric material that can be completely or partially removed to “lift-off” silicide stringers if formed. After silicide stringer removal, a dielectric layer, having a first portion and second portion that are selectively etchable with respect to one another, is deposited. A gate contact opening is formed in the dielectric layer where the opening is essentially the same dimension as the gate length. Alignment of the opening to the gate electrode is buffered by the thickness of the first portion of the dielectric layer, adjacent sidewalls of the gate electrode.

Abstract: The present invention provides a method of fabricating a vertical hard mask/conductive pattern profile. The process begins by forming a polysilicon or more preferably a polysilicon and silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern using Cl2/He—O2/N2 etch chemistry, thereby forming a hard mask/conductive pattern profile that is vertical.

Abstract: The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate. Provided on the semiconductor substrate is a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines, and comprising gate regions formed by a first conducting layer, a dielectric interpoly layer and a second conducting layer with said regions being insulated from each other by dielectric insulation films to form said architecture with said word lines being defined photolithographically by protective strips.

Abstract: In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

Abstract: A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted.

Abstract: Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (48, 148) over an oxidizable section (18, 118) of the semiconductor device. The protective cover (48, 148) is operable to at least inhibit oxidation of the oxidizable section (18, 118). While the oxidizable section (18, 118) is covered, an oxide structure (52, 152) is formed. The oxide structure (52, 152) is operable to at least ameliorate etch damage to the semiconductor device.

Abstract: A method of fabricating a self-aligned storage node is described. A storage node plug is formed after formations of the bit line contact and the storage node contact. A spacer is formed on a sidewall of an opening, which is used for forming a bit line. The bit line is formed in the opening. Because the spacer provides good isolation, the tolerance window for forming the bit line is increased. Some follow-up steps are performed to form a storage node.

Abstract: A method of plasma etching a Si3N4 masked tungsten silicide layer down to an underlying doped polysilicon layer in the gate conductor stack formation process is disclosed. The method is performed in a plasma etcher and the etching mixture contains C12, HCl and O2 wherein the C12/HCl ratio is approximately equal to 4.7 and the oxygen flow varies between 20 and 30 sccm, 25 sccm being the optimal value. A slight overetching of the underlying doped polysilicon layer with this mixture is recommended. The etching method of the present invention preserves the thickness and integrity of the top Si3N4 masking layer that are essential elements for the successful completion of the remaining steps of the gate conductor stack formation process.

Abstract: The present invention relates to a method of forming a contact hole of a DRAM on the semiconductor wafer. The semiconductor wafer comprises a substrate, a first dielectric layer, two bit lines on the first dielectric layer, a second dielectric layer, and a photo-resist layer comprising an opening to define the pattern of the contact hole. The method comprises performing a first anisotropic etching process to vertically remove a portion of the two dielectric layers and two bit lines to grossly form the contact hole, removing the photo-resist layer in its entirety, performing a thermal oxidation to form a silicon oxide layer on the side walls of the two bit lines, then forming a silicon nitride layer on the surface of the contact hole, and performing a dry etching to remove the silicon nitride layer. There is a silicon oxide layer and a silicon nitride layer between the bit line and the contact hole, and the contact area of the contact hole will not be reduced.

Abstract: A method of fabricating a narrow bit line structure is disclosed. The fabrication includes the steps as follows. At first, the interpoly dielectric layer is formed over the MOSFET. Then the landing pad is formed in the interpoly dielectric layer. Afterwards, the first polysilicon layer, the tungsten silicide layer, the silicon-oxy-nitride layer, and the second polysilicon layer is continuously formed over the interpoly dielectric layer. The defined photoresist layer is formed on the second polysilicon layer. A portion of the second polysilicon layer is etched, using the defined photoresist layer as a mask. Afterwards, the defined photoresist layer is removed. The polysilicon spacer is formed in the second polysilicon layer sidewall. The silicon oxide layer is deposited over the second polysilicon layer. Next, the silicon oxide layer is etched back to expose the second polysilicon layer.

Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.

Abstract: A method for forming a metal layer using an atomic layer deposition process. A sacrificial metal atomic layer is formed on a semiconductor substrate by reacting a precursor containing a metal with a reducing gas, and a metal atomic layer is formed of metal atoms separated from a metal halide gas on a semiconductor substrate by reacting the sacrificial metal atomic layer with a metal halide gas. Also, a silicon atomic layer may be additionally formed on the metal atomic layer using a silicon source gas, to thereby alternately stack metal atomic layers and silicon layers. Thus, a metal layer or a metal silicide layer having excellent step coverage can be formed on the semiconductor substrate.

Abstract: In a charge coupled device, a plurality of charge transfer electrodes are formed on a first insulating layer formed on a semiconductor substrate. Each of the charge transfer electrodes is formed by a first conductive layer and a second conductive layer narrower than the first conductive layer. A second insulating layer having the same area as the second conductive layer and is formed on the second conductive layer. A sidewall insulating layer is formed on sidewalls of the second insulating layer and the second conductive layer.

Abstract: Polysilicon and oxide layers on a semiconductor wafer are etched in a single etching chamber configured for selectively providing a first etching environment in the chamber for etching of the polysilicon layer, and a second etching environment in the chamber for etching the oxide layer. The decoupled plasma source polysilicon etch chamber enables etching of both oxide-based layers and silicon-based layers, without removing the semiconductor wafer from the etching chamber.

Abstract: A method for forming a gate structure on a semiconductor substrate includes the following steps. A layer of a gate material is formed on the semiconductor substrate, and a patterned mask layer is formed on the layer of the gate material opposite the substrate. The layer of the gate material is then etched with an etching gas including a mixture of chlorine gas (Cl.sub.2), oxygen gas (O.sub.2), and a gas including fluorine (F) using the patterned mask layer as an etching mask. In particular, the step of forming the layer of the gate material can include the steps of forming a polysilicon layer on a surface of the semiconductor substrate, and forming a silicide layer on the polysilicon layer opposite the substrate.

Abstract: A dry etching method of a multilayer film for a semiconductor device includes a first step for etching a metallic layer or a metallic silicide layer by use of a compound gas plasma mixed by a first gas including at least two of O.sub.2, N.sub.2, CO, a second gas including fluorine, a third gas including chlorine, and a fourth gas including bromine, a second step for processing an entire structure formed on the semiconductor substrate by use of a fluorine gas plasma including carbon, and a third step for etching the polysilicon layer by use of a gas plasma including chlorine. The dry etching method prevents an undercut generation along the sidewalls as etching targets, as well as residues remaining in the substrate, thereby improving a reliability of the semiconductor device. The method omits an additional refining process, thereby decreasing a fabrication time of the semiconductor device, improving productivity and realizing cost reduction of the semiconductor device.

Abstract: A method for manufacturing a self-aligned stacked storage node DRAM cell on a substrate for a capacitor over bit line (COB) process is disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.

Abstract: A layered trace configuration comprising a conductive trace capped with a silicide material which allows for removal of oxide polymer residues forming in vias used for interlayer contacts in a multilayer semiconductor device and eliminates or greatly reduces the formation of metal polymer residues in the vias. The formation of an interlayer contact according to one embodiment of the present invention comprises providing a trace formed on a semiconductor substrate and a silicide layer capping the conductive layer. An interlayer dielectric is deposited over the silicide capped trace and the substrate. A via is etched through the interlayer dielectric, wherein the etch is selectively stopped on the silicide layer. Any residue forming in the via is removed and a conductive material is deposited in the via to form the interlayer contact.

Abstract: The invention discloses a split polycilicon process for forming poly gate and polycide gate with an almost equal height in a CMOS image integrated circuit fabricated on a substrate to reduce the sheet resistance of the poly gate electrode. First, a gate oxide layer is formed on a substrate, and then a polysilicon layer and a capped dielectric layer are sequentially deposited. Next, a poly gate is patterned by using a first photoresist layer, and then the capped dielectric layer and a portion of the polycilison layer are etched. Next, the first photoresist layer is removed. Thereafter, a silicide layer is deposited. Then, a polycide gate is patterned by using a second photoresist layer, and the silicide layer and the polysilicon layer is etched. Finally, the second photoresist layer is removed.

Abstract: A method of etching closely spaced trenches in a silicon body wherein a masked silicon body is introduced into a plasma etching apparatus. An object having an exposed silicon surface that is consumable by a plasma environment is provided in the apparatus. A reactive plasma environment is established in the apparatus which removes silicon from the body and the silicon object. The additional silicon from the object in the plasma influences the silicon removal from the body to thereby provide tapered trench side walls.

Abstract: The present invention is embodied in a method and apparatus for etching dielectric layers and inorganic ARC's without the need for removing the substrate being processed from the processing chamber and without the need for intervening processing steps such as chamber cleaning operations (in situ process). A layer and/or a multi-layer film deposited on a substrate, such as silicon, is located within a processing chamber. The substrate has a base, an underlying layer above the base, an overlying layer above the underlying layer, and a top dielectric anti-reflective coating (DARC) layer formed on the overlying layer. In the preferred method, first, the DARC layer and the overlying layer is etched by a first process gas. Next, the underlying layer is etched by a second process gas.

Abstract: In a semiconductor device manufacturing method, HBr gas (etching gas) is made plasma while the gas pressure thereof is kept to 2 mTorr or less, and ion elements of the plasma are accelerated under bias power of 150 W or more to etch a titanium silicide film 11. Thereafter, HBr gas is further made plasma while the gas pressure thereof is kept to 5 to 10 mTorr, and ion elements of the plasma are accelerated under bias power of 10 to 100 W to etch a polysilicon film 10 with the ion elements in the plasma.

Abstract: A dry etching method for a multilayer film is disclosed, which is capable of dry-etching a multilayer film such as a titanium polyside (a polysilicon layer and a titanium silicide layer) and includes the steps of a first step for anisotropically etching the titanium silicide layer using a plasma containing Cl.sub.2 /N.sub.2 gas, and a second step for anisotropically etching the polysilicon layer using a plasma containing Cl.sub.2 /O.sub.2.

Abstract: For the contact opening in advanced IC processing, it becomes critical to monitor the degree of overetching of the thin silicide layer and also to obtain the etching rate of the silicide layer. A method is disclosed which will allow the electrical measurements of the sheet resistance of the exposed (by the contact etch) silicide layer, thus allowing electrical measurements to the integrity as well as the thickness of the remaining silicide layer. A main feature of the disclosed test method is a modification of the conventional van der Pauw test structure, or of the cross-bridge structure (which will allow electrical measurement of the line width, in addition to the sheet resistance information).

Abstract: An etching process is provided for etching through a tungsten silicide layer and an underlying polysilicon layer during the formation of a control gate in a semiconductor device. The etching process prevents the formation of a tungsten silicide residue while etching a layer of tungsten silicide, by employing a plasma that exhibits strong physical sputtering capabilities. The plasma effectively etches away exposed portions of the silicide layer, especially in narrow patterned regions. The plasma exhibits an etching selectivity (ratio of tungsten silicide etch rate to polysilicon etch rate) that is less than about 1.0.

Abstract: A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.

Abstract: A method for producing a semiconductor device from a silicon substrate supporting a patterned hardmask layer, a tungsten silicide layer, a polysilicon layer, and a gate oxide layer. The method comprises etching the tungsten silicide layer and the polysilicon layer with an etchant gas comprising carbon monoxide (CO) and chlorine (Cl.sub.2). The etchant gas may also include hydrogen bromide (HBr) or a nitrogen-containing gas (e.g., N.sub.2).

Abstract: A method for plasma assisted CVD deposition of tungsten and of tungsten compounds is described wherein a plasma containing a high density of active hydrogen species is maintained to scavenge fluorine and fluoride species formed by the decomposition of the tungsten precursor WF.sub.6. The activated hydrogen species also assist in the breaking of W--F bonds, thereby facilitating the decompoition process and forming high density, high conductivity, fluoride free conductive films of tungsten and of tungsten compounds. The ability to form such fluoride free tungsten films with the assistance of activated hydrogen species, permits the deposition of tungsten directly onto gate oxides thereby enabling the formation of tungsten gate electrodes without underlying polysilicon. Low conductivity tungsten contacts including in-situ formed tungsten compound barrier layers may also be formed by this process.

Abstract: A method fabricating salicide. A substrate having a polysilicon gate and a source/drain region is provided. A silicon oxide layer is formed on the polysilicon gate and the substrate. Using dry etch, a part of the silicon oxide layer is removed to leave a spacer with a waistline on a side wall of the polysilicon gate. A metal layer is formed on the polysilicon gate and the source/drain region.

Abstract: A process for etching single crystal silicon, polysilicon, silicide and polycide using iodinate or brominate gas chemistry, is disclosed. The iodinate/brominate gas chemistry etches narrow deep trenches with very high aspect ratios and good profile control and without black silicon formation or other undesirable phenomena.

Abstract: In a method of manufacturing a semiconductor device, a first film essentially consisting of silicon is deposited on the surface of a semiconductor substrate. A second film essentially consisting of material having a proper etching selection ratio relative to tungsten is deposited on the first film. A third film essentially consisting of tungsten is deposited on the second film. A resist pattern is formed on the third film. The third film is etched and patterned to the surface of the second film, by using the resist pattern as a mask. The second film is etched to have the same shape as the third film. The first film is etched to have the same shape as the third film. After the step of patterning the third film and before the step of patterning the first film, the resist pattern is heated to a temperature of 80.degree. C. or higher, the semiconductor substrate is exposed in atmospheric air, and the resist pattern is removed.

Abstract: A method for etching metal silicide layers 22a, 22b and polysilicon layers 24a, 24b on a substrate 20 with high etching selectivity, and anisotropic etching properties, is described. In the method, the substrate 20 is placed in a plasma zone 55, and process gas comprising chlorine, oxygen and optionally helium gas, is introduced into the plasma zone. A plasma is formed from the process gas to etch the metal silicide layer 22 at high etching selectivity relative to etching of the polysilicon layer 24, while providing substantially anisotropic etching of the metal silicide and polysilicon layers. Preferably, the plasma is formed using combined inductive and capacitive plasma sources.

Abstract: Sidewall spacers, adjacent a gate electrode and source/drain regions of a MOS transistor are formed of a dielectric material that can be etched selectively to the material selected as the isolation dielectric. A layer of silicide forming metal is deposited overlying the MOS transistor and heated, wherein silicide regions are formed where the metal makes contact with silicon, for example, in the gate electrode and source/drain regions. At least a portion of the sidewall spacers are etched-away and silicide stringers, if formed on the spacers, are removed.

Abstract: A method for dry-etching a polycide film composed of a double layer film of a polysilicon film provided on a semiconductor substrate and a metal silicide film provided on said polysilicon film according to the present invention comprises the steps of: a first etching step for etching said silicide film with a first etching gas containing no fluorine-based gasses using a photoresist film as a mask, and a second etching step for etching said polysilicon film with a second etching gas not containing chloride gas and fluorine gas using said patterned metal silicide film and said photoresist film remaining on said metal silicide film after said first etching step as a mask.

Abstract: A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

Abstract: A method of reducing the loss of metal silicide in pre-metal etching which includes the following steps. A polysilicon gate electrode and implanted source/drain electrodes are formed on a silicon substrate. A metal silicide layer is formed on the polysilicon gate electrode and the source/drain electrodes. On the surface of the substrate, the polysilicon gate electrode, the source-drain electrodes region and the metal silicide layer, a protecting glass for insulation is formed and then dry etched to form a contact window. The metal silicide layer will form a damaged metal silicide layer in the contact window. Thereafter, a thermal process is conducted to repair the damaged metal silicide layer and finally, pre-metal etching is conducted completing the process. Pursuant to this method, the extremely low resistance of the metal silicide remains.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.

Abstract: A method of filling contact holes in a dielectric layer on an integrated circuit wafer. The method reduces processing steps and results in a reliable metal plug filling the contact hole. In one embodiment the contact hole is filled using blanket deposition of titanium silicide using chemical vapor deposition followed by etchback. In a second embodiment the contact hole is filled with titanium silicide using selective chemical vapor deposition of titanium silicide. In a third embodiment an adhesion layer of titanium silicide is formed on the sidewalls and bottoms of the contact holes. A conductor metal of titanium silicide, aluminum, tungsten, or copper is used to fill the contact hole using selective chemical vapor deposition.

Abstract: Methods of forming electrically conductive lines include the steps of forming a first electrically insulating layer (e.g., SiO.sub.2) on a face of a semiconductor substrate and then forming a layer of polycrystalline silicon (polysilicon) as a blanket layer on the first electrically insulating layer. A metal silicide layer (e.g., TiSix) is then formed on the polysilicon layer by reacting the polysilicon layer with an appropriate metal such as titanium (Ti) using a thermal treatment step. Thereafter, a second electrically insulating layer (e.g., SiO.sub.2, Si.sub.3 N.sub.4) is formed on the metal silicide layer using conventional techniques. A layer of photoresist is then deposited onto the second electrically insulating layer and patterned as an etching mask using conventional photolithographic processing steps.

Abstract: A method of forming a polycide gate of a semiconductor device, including the steps of etching all the metal silicide layer by using a plasma, and etching the polysilicon layer by relatively decreasing power for increasing the energy of a particles constituting the plasma, as compared with that in the step of etching the metal silicide layer. A physically and functionally stable polycide gate can be simply and rapidly formed.