Abstract: A method for forming a fine pattern of a semiconductor device comprises: forming a first hard mask film and an etch barrier film over a semiconductor substrate; forming a sacrificial pattern over the etch barrier film; forming a spacer on sidewalls of the sacrificial pattern; removing the sacrificial pattern; etching the etch barrier film and the hard mask film with the spacer as an etch mask to form an etch barrier pattern and a hard mask pattern; and removing the spacer and the etch barrier pattern, thereby improving yield and reliability of the device.

Abstract: A method of fabricating a semiconductor device, includes providing a substrate having at least one first portion and at least one second portion. The first portion includes a semiconductor material and the second portion includes an electrically isolating material. An etching step is performed using an etchant in order to at least partially remove the first and the second portions. The etchant includes a NF3/CH4/N2 plasma.

Abstract: Disclosed are methods and systems of etching copper containing materials so that they have smooth and/or planar surface. In this connection, the systems and methods employ two different solutions to accomplish the etching. The first solution oxidizes the surface of the copper containing material and forms a passivating film. The second solution removes the passivating film in a controlable manner.

Abstract: The present invention is a method of use of a novel cleaning solution in a single wafer cleaning process. According to the present invention the method involves using a cleaning solution in a single wafer mode and the cleaning solution comprises at least ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), water (H2O) and a chelating agent. In an embodiment of the present invention the cleaning solution also contains a surfactant. Moreover, the present invention also teaches a method of combining an ammonia hydroxide, hydrogen peroxide, and chelating agent step with a short HF step in a fashion that minimizes process time in a way that the entire method removes aluminum and iron contamination efficiently without etching too much oxide. The single wafer cleaning processes may also be used to increase the yield of high-grade reclaimed wafers.

Abstract: A method for removing contamination on a semiconductor substrate is disclosed. The contamination contains at least one element belonging to one of 3A group, 3B group and 4A group of long-period form of periodic system of elements. The method comprises first and second process steps. The first process is wet processing the semiconductor substrate by first remover liquid that contains one of acid and alkali. The second process is wet processing the semiconductor substrate by second remover liquid that contains oxidizing reagent and one of hydrofluoric acid and salt of hydrofluoric acid.

Abstract: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

Abstract: An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. An adjacent layer of the heterostructure is selectively etched to expose at least a portion of the etch stop layer. The etch stop layer also can be selectively etched. In one embodiment, the adjacent layer can be etched using reactive ion etching (RIE) and the etch stop layer is selectively etched using a wet chemical etch. In any event, the selectively etched area can be used to generate a contact or the like for a device.

Abstract: A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer is accreted to the first oxide layer to narrow the first set of voids to become a second set of voids on the substrate. A polysilicon layer is deposited over the second oxide layer, the first oxide layer and the substrate. A third set of voids is etched into the polysilicon layer. Further etching widens the third set of voids to define a fourth set of voids to expose the first oxide layer and the substrate. The first oxide layer and the substrate is deeply etched to define beams and trenches in the substrate.

Abstract: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.

Abstract: A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and formed by epitaxial growth.

Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.

Abstract: A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge section is defined in the overgrowth layer and portions of the sacrificial layer are removed to define a shank section in the overgrowth layer under the ridge section. The ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section.

Abstract: A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.

Abstract: A system and method is disclosed for using a differential wet etch stop technique to provide a uniform oxide layer over a metal layer in a laser trimmed fuse. A layer of boron doped oxide with a slow etch rate is placed over the metal layer. A layer of phosphorus doped oxide with a fast etch rate is placed over the boron doped oxide. The time period required for a wet etch process to etch through the phosphorus doped oxide is calculated. The wet etch process is then applied to the phosphorus doped oxide for the calculated time period. The wet etch process slows significantly when it reaches the boron doped oxide. This method forms a uniform layer of boron doped oxide over the metal layer.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.

Abstract: A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32).

Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

Abstract: The temperature of the sputtering process for forming the Ti film is selected to a temperature within a range of from 200 degree C. to 225 degree C. to provide stable film quality against oxidization (step 11). The irradiation with ultraviolet is conducted before applying the photo resist to reduce positive electric charge (step 12), and nitrogen plasma processing is conducted during the etching of the via hole and after the plasma stripping processing to reduce positive electric charge (steps 13 and 14), and the resistivity of the rinse liquid at the organic stripping is controlled to obtain equal to or lower than 0.3M? cm (step 15). Further, the RF-spattered thickness during the RF sputtering process for the barrier metal film is set to 18 nm to 22 nm to remove TiOn film (step 16).

Abstract: The present invention discloses a method for forming an element isolation film of a semiconductor device, comprising the steps of: sequentially forming a pad oxide film, a pad nitride film and a mask oxide film on a semiconductor substrate on which a first region for forming a high voltage device and a second region for forming a low voltage device or a flash memory cell are defined; etching the mask oxide film, the pad nitride film and the pad oxide film in the first region and the mask oxide film in the second region, and forming an oxide film for the high voltage device in the first region; removing the residual pad nitride film in the second region; removing the nitride film and partially removing the oxide film for the high voltage device in the first region, wherein the oxide film for the high voltage device has a third thickness; removing the residual pad oxide film in the second region; partially removing the oxide film for the high voltage device in the first region according to a cleaning process, w

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal layer; forming a photomask on the anti-reflection layer; performing an initial etching, a main etching and an over-etching for the anti-reflection layer, the metal layer and the lower adhesive layer, respectively, in a region which is not protected by the photomask, using C3F8 as a main etching gas; and removing the photomask residual on the anti-reflection layer.

Abstract: Provided is a method for fabricating a semiconductor optical device that can be used as a reflecting semiconductor mirror or an optical filter, in which two or more types of semiconductor layers having different etch rates are alternately stacked, at least one type of semiconductor layers is selectively etched to form an air-gap structure, and an oxide or a nitride having a good heat transfer property is deposited so that the air gap is buried, whereby it is possible to effectively implement the semiconductor reflector or the optical filter having a high reflectance in a small period because of the large index contrast between the oxide or the nitride buried in the air gap and the semiconductor layer.

Abstract: A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.

Abstract: A resist film and a polymer layer adhered on a semiconductor substrate can be removed by the method according to the present invention. A first processing liquid, typically including a oxidizing agent, such as hydrogen peroxide solution, is fed to the substrate, thereby the condition of the resist film and the polymer layer is changed. Next, a second processing liquid, typically including a dimethyl sulfoxide and an amine solvent, is fed to the substrate, thereby the resist film and the polymer layer is dissolved and lifted off from the substrate. A sputtered copper particles included in the polymer layer can also be removed.

Abstract: A method and apparatus for a semiconductor device having increased electrical carrier mobility is described. That method and apparatus comprises forming two recesses within a substrate, and providing a material within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses. Also described is a semiconductor device that comprises a substrate having two recesses formed therein, and a material disposed within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses.

Abstract: Methods of selectively removing post-etch polymer material and dielectric antireflective coatings (DARC) without substantially etching an underlying carbon-doped low k dielectric layer, and compositions for the selective removal of a DARC layer and post-etch polymer material are provided. A composition comprising trimethylammonium fluoride is used to selectively etch a dielectric antireflective coating layer overlying a low k dielectric layer at an etch rate of the antireflective coating layer to the low k dielectric layer that is greater than the etch rate of the antireflective coating to a TEOS layer. The method and composition are useful, for example, in the formation of high aspect ratio openings in low k (carbon doped) silicon oxide dielectric layers and maintaining the integrity of the dimensions of the formed openings during a cleaning step to remove a post-etch polymer and antireflective coating.

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: Disclosed is a method of manufacturing a semiconductor device. First, a silicidation blocking layer is formed on a semiconductor substrate by a plasma enhanced chemical vapor deposition process. Next, the silicidation blocking layer in a region in which a metal silicide contact is to be formed is removed by a wet etching process. Next, after a metal layer is formed on the resultant, the silicon in the region and the metal of the metal layer are reacted to form the metal silicide. Since the silicidation blocking layer consisting of PE-SiON is formed at a low temperature of less than 400 Celsius Degrees, it is possible to prevent diffusion and redistribution of impurities in gate and source/drain regions of a transistor during the deposition of the silicidation blocking layer.

Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor, which can reduce the junction capacitance without degradation of transistor characteristics including forming a buffer oxide layer on a semiconductor substrate; successively conducting ion implantations for well formation and field stop formation in the substrate through the buffer oxide layer; removing the buffer oxide layer; forming and patterning a sacrificial layer to form a trench successively conducting ion implantations for threshold voltage adjustment and punch stop formation on the semiconductor substrate area exposed by the trench; forming a gate oxide layer on the exposed surface of the substrate; forming a polysilicon layer so as to completely fill the trench; polishing the polysilicon layer to form a gate electrode; removing the sacrificial layer; forming an LDD region in the substrate; forming spacers on side walls of the gate electrode; and forming source/drain regions.

Abstract: A method of spiking a mixed acid liquid in a reactor is performed under three modes of control, a based-on-charge mode control, a based-on-time mode control, and a based-on-time-and-charge mode control. In the based-on-charge mode control, spike timing and spiking amount of an acid liquid are set for each lot of product. In the based-on-time mode control, the spike timing and the spiking amount of the acid liquid are set for each timing point. In the based-on-time-and-charge mode control, the spike timing and the spiking amount of an acid liquid are set for each lot of product and each timing point. Thereby, a concentration of the mixed acid liquid is controlled at a targetlevel.

Abstract: The temperature of the sputtering process for forming the Ti film is selected to a temperature within a range of from 200 degree C. to 225 degree C. to provide stable film quality against oxidization (step 11). The irradiation with ultraviolet is conducted before applying the photo resist to reduce positive electric charge (step 12), and nitrogen plasma processing is conducted during the etching of the via hole and after the plasma stripping processing to reduce positive electric charge (steps 13 and 14), and the resistivity of the rinse liquid at the organic stripping is controlled to obtain equal to or lower than 0.3M&OHgr; cm (step 15). Further, the RF-spattered thickness during the RF sputtering process for the barrier metal film is set to 18 nm to 22 nm to remove TiOn film (step 16).

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A fabrication method of a semiconductor device improved in the polishing rate of an insulation film and less likely to generate a defect during polishing is obtained. In this fabrication of a semiconductor device, impurities are introduced into a first insulation film, and then planarization is effected by polishing the surface of the first insulation film. Thus, the polishing rate of the portion of the first insulation film in which impurities are introduced is improved. Also a defect is not easily generated therein.

Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices. Vias, interconnect metallization and wiring lines are formed using single and dual damascene techniques wherein dielectric layers are treated with a wide electron beam exposure.

Abstract: A method of manufacturing a semiconductor apparatus includes the step (a) to the step (f). In the step (a), an insulation film is formed on a semiconductor substrate. In the step (b), a wiring trench is formed which extends to the insulation film. In the step (c), a first conductive film is formed which covers an inner surface of the wiring trench and covers the insulation film. In the step (d), a second conductive film is formed which fills the wiring trench and covers the first conductive film. In the step (e), the second conductive film is removed by chemical mechanical polishing (CMP) until a surface of the first conductive film is exposed. In the step (f), a surface of the second conductive film is polished by using a first solution such that a first protective film for protecting the second conductive film is formed. In the step (g), the first conductive film and the second conductive film is removed by CMP until a surface of the insulation film is exposed.

Abstract: A method is disclosed for accurately predicting the wet etch end points as a function of the temperature and concentration of the etching solution, as well as of the thickness of the film to be etched. This is accomplished by fitting an etch rate equation to the process of etching a film in terms of two constant parameters that are determined by one set of experiments performed on a given wet etch bench. Thereafter, the constants are used with the rate equation to calculate precisely the etch rate of a film, and then the etch rate is divided into a target film loss or a target film thickness to obtain etching time, or time to etch, which takes into account the variations in temperature and concentration, for example, of the acid in the solution. The resulting film either looses the specified amount of material, or acquires the specified thickness without incurring any damage, which is especially suited for sub-micron semiconductor technology where precise etching is required.

Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a via hole reaching a metal wiring and a concave groove are simultaneously formed in an interlayer film. When the interlayer film and the material of an organic film embedded in the via hole are etched, the etching rate for the material of the organic film with an etching gas is set to be higher than the etching rate for the interlayer film with an etching gas. Thus, plasma etching does not proceed in a state in which the material of the organic film projects from the bottom of the concave groove formed in the interlayer film, and the production of depositions is prevented.

Abstract: A method for forming a metal silicide layer in a self-aligned manner on a source region and a drain region and a gate electrode of a semiconductor device formed on a semiconductor substrate, the method comprising the steps of: depositing a cobalt film over an entire surface of the semiconductor device formed on the semiconductor substrate, forming the metal silicide layer on the source region and drain region and the gate electrode by performing a heat treating thereof, and etching away an unreacted cobalt remaining on the semiconductor substrate using an admixture solution made of hydrochloric acid, hydrogen peroxide, and water, having relative concentration ratio ranging from 1:1:5 to 3:1:5, at a solution temperature of 25 to 45° C., with an etching time of 1 to 20 minutes.

Abstract: A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).

Abstract: A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.

Abstract: A method for plating solder is provided. In accordance with the method, a die having a seed metallization thereon is provided. The seed metallization is microetched (85) with a solution comprising an acid and an oxidizer, thereby forming an etched seed metallization. An under bump metallization (UBM) is then electroplated (87) onto the etched seed metallization, and a lead-free solder composition, such as SnCu, is electroplated (91) onto the UBM. A method for reflowing solder is also provided, which may be used in conjunction with the method for plating solder. In accordance with this later method, the substrate is subjected to a seed metallization etch (137), followed by a microetch (141). A solder flux is then dispensed onto the substrate (147) and the solder is reflowed (149).

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A nonvolatile memory device is formed by forming a first oxide layer on a substrate. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. The second oxide layer is patterned so as to expose the nitride layer. A first polysilicon layer is formed on the second oxide layer and the exposed portion of the nitride layer. The first polysilicon layer and the nitride layer are etched so as to expose the second oxide layer and the first oxide layer and to form polysilicon spacers on the nitride layer. The polysilicon spacers are etched so as to expose portions of the nitride layer. The exposed portions of the nitride layer may function as charge trapping layers. The exposed portion of the first oxide layer is etched to expose a portion of the substrate. A third oxide layer is formed on the exposed portion of the substrate, the exposed portions of the nitride layer, and the second oxide layer. A second polysilicon layer is formed on the third oxide layer.

Abstract: A cleaning gas that is obtained by vaporizing a carboxylic acid is supplied into a treatment chamber having an insulating substance adhering to the inside thereof, and the inside of the treatment chamber is evacuated. When the cleaning gas supplied into the treatment chamber comes in contact with the insulating substance adhering to an inside wall and a susceptor in the treatment chamber, the insulating substance is turned into a complex, so that the complex of the insulating substance is formed. The complex of the insulating substance is easily vaporized due to its high vapor pressure. The vaporized complex of the insulating substance is discharged out of the treatment chamber by the evacuation.