Abstract: A primary layer deposited over a secondary layer is planarized. A chemical mechanical polishing process is performed using a slurry which targets the primary layer. Then, chemical etching is performed using a chemical wet etchant which targets the secondary layer. The method is used, for example, when making connections to a lower layer through an insulating layer. Plug holes are formed through the insulating layer to the lower layer. Then the secondary layer is deposited. The secondary layer acts as a barrier layer or a glue layer.

Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices. Vias, interconnect metallization and wiring lines are formed using single and dual damascene techniques wherein dielectric layers are treated with a wide electron beam exposure.

Abstract: A wafer cleaning process is disclosed for quenching etch reactions while rinsing etch reactants and etch products from the wafer. Holes are etched through an insulating layer by reactive ion etch, for example. The holes might comprise contact openings over a semiconductor substrate, or vias through insulating layers between metal lines. An organic or polymer residue left in the holes is cleaned by a wet process. The cleaning process continues to attack sidewalls of the holes, undesirably widening them. The wafer is therefore rinsed with a rinse agent below 0° C., thermally quenching further etching of the sidewalls and affording greater control over the hole dimensions. At the same time, the rinse agent allows relatively rapid diffusion of etchants and etch products from narrow and deep openings. An exemplary rinse agent for such low temperature rinsing is dilute ethylene glycol (C2H6O2).

Abstract: A microfabrication process for making enclosed, subsurface microfluidic tunnels, cavities, channels, and the like within suspended beams includes etching a single crystal silicon wafer to produce trenches defining a beam. The trench walls are oxidized, and the interior of the beam is etched through a channel via on the top of the beam to form a hollow beam with oxide sidewalls.

Abstract: A method for detaching an epitaxial layer from one substrate and transferring it to another substrate allows an epitaxially grown material layer to be easily detached from a first substrate that has good epitaxial growth properties and transferred to another substrate having better cleaving, electrical or other properties than the first substrate. A mask is applied to a portion of a surface of the first epitaxial layer and a second epitaxial layer is grown over the first epitaxial layer and the mask. A trench is formed in the second epitaxial layer to expose the mask and a second substrate is bonded to the second epitaxial layer. An etchant is introduced through the trench and etches away the mask, thus releasing the second epitaxial layer from the first substrate and the first epitaxial layer. Thus, the second epitaxial layer has been released from the first substrate and transferred to the second substrate without performing operations that would impair the optical properties of the epitaxial material.

Abstract: A process for forming a silicided MOS transistor (100) begins by providing source and drain regions (104) and (106) and a gate electrode (110). Silicon nitride spacers (116) are formed adjacent the gate electrode (110). A cobalt layer (118) and an overlying titanium layer (120) are then deposited in contact with the regions (104), (106), and (110). A rapid thermal process (130) is then used to react the titanium, cobalt, and silicon together to form silicide regions (124), (126), and (128), and intermetallic compound layers (132) and (134). The intermetallic compound layers (132) and (134) are then etched using two sequentially-performed wet etch steps (136) and (138). The resulting structure (100) has a nitride spacer (116) and field oxide regions (107) which are free from cobalt residual contamination (38).

Abstract: A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

Abstract: A method of fabricating a liquid crystal display device includes the step of removing a porous anodic oxide film selectively with respect to a barrier-type anodic oxide film covering a gate electrode pattern of a thin-film transistor, wherein the step of removing the porous anodic oxide film is conducted after the step of disconnecting a bridging conductor pattern used for supplying electric current at the time of anodic oxidation process of the gate electrode.

Abstract: A process for producing a semiconductor device includes the following sequential steps: producing a semiconductor body having an Al.sub.x Ga.sub.1-x As layer with an upper surface, where x.ltoreq.0.40; applying a contact metallization made of a non-noble metallic material to the Al.sub.x Ga.sub.1-x As layer; precleaning a semiconductor surface to produce a hydrophilic semiconductor surface; roughening the upper surface of the Al.sub.x Ga.sub.1-x As layer by etching with an etching mixture of hydrogen peroxide.gtoreq.30% and hydrofluoric acid.gtoreq.40% (1000:6) for a period of from 1 to 2.5 minutes; and re-etching with a dilute mineral acid. According to another embodiment, 0.ltoreq.x.ltoreq.1 and the upper surface of the Al.sub.x Ga.sub.1-x As layer is roughened by etching with nitric acid 65% at temperatures of between 0.degree. C. and 30.degree. C.

Abstract: An array of n-wavelength vertical cavity surface emitting lasers (VCSELs) can be grown with precise and repeatable wavelength control. First, a foundation VCSEL structure is grown on a substrate. Next, n-paired layers of AlGaAs and InGaP are grown, where n is the desired number of different wavelengths. Next, one of the n regions is masked and etched. The steps of masking and etching are repeated until all n regions are etched. Finally, the upper VCSEL structure is grown.

Abstract: A class of epoxy bond and stop etch (EBASE) microelectronic fabrication techniques is disclosed. The essence of such techniques is to grow circuit components on top of a stop etch layer grown on a first substrate. The first substrate and a host substrate are then bonded together so that the circuit components are attached to the host substrate by the bonding agent. The first substrate is then removed, e.g., by a chemical or physical etching process to which the stop etch layer is resistant. EBASE fabrication methods allow access to regions of a device structure which are usually blocked by the presence of a substrate, and are of particular utility in the fabrication of ultrafast electronic and optoelectronic devices and circuits.

Abstract: Semiconductor devices with copper interconnects wherein a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the trenches. A copper layer is placed over the barrier metal layer and fills the trenches. The part of the copper layer that is not inside the trenches is polished away, making sure that the barrier metal layer is not polished away. The copper layer is laser annealed to increase the grain size, remove seams, and provide a better interface bond between the barrier metal layer and the copper layer. The barrier metal layer protects the dielectric layer during the annealing process. The part of the barrier metal layer that is not in the trenches is removed by polishing.

Abstract: An efficient method of interconnecting a solar cell having at least two front surface contacts with a diode mounted on a front surface of the solar cell includes the act of forming at least a first recess on a front surface of the solar cell. A first solar cell contact is formed on the front surface in the first recess. A second solar cell contact is formed on the front surface. At least a first bypass diode is positioned at least partly within the recess. The bypass diode has a first diode contact and a second diode contact. The first solar cell contact is interconnected with the first diode contact. The second solar cell contact is interconnected with the second diode contact.

Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.

Abstract: A process for selective recess etching of GaAs field-effect transistors. A selected etch stop layer (In.sub.x Ga.sub.1-x P) maintains what is commonly referred to as lattice-match with the GaAs substrate material. By using this etch stop, a significant reduction in access resistances is realized with respect to devices containing other etch stop materials while an improvement in the uniformity of device characteristics across the wafer and from wafer to wafer is realized.

Abstract: A process for removing a plurality of layers of different materials from a substrate having a silicon material base, at least one of said layers being a silicon oxide material and at least one other of said layers comprising a metal and the metal layer being located above the silicon oxide layer. The process includes the steps of treating the substrate with a series of chemical formulations adapted to successively remove the materials of the plurality of layers until the silicon material base is exposed, the silicon oxide layer being removed by treatment with HF, wherein the HF treatment to remove said silicon oxide layer comprises exposing the substrate to:initially, a dilute HF solution of no more than 1.0% concentration;subsequently, a concentrated HF solution of from about 2.5% to about 10% concentration; andfinally, a dilute HF solution of no more than 1.0% concentration.

Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.

Abstract: A process for producing an electronic device having a silicon nitride film on a substrate is provided which comprises steps of forming a silicon nitride film and a silicon oxide film on a first face and a second face reverse to the first face of the substrate respectively, removing the silicon oxide film on the first face by wet etching, removing the silicon nitride film on the first face by wet etching, and removing the silicon oxide film on the second face by wet etching.

Abstract: A process of opening, a stack of large diameter via holes, in a multiple levels of insulator layers, to be used for access of a laser repair procedure, applied to underlying integrated circuit shapes, while simultaneously opening small diameter via holes, in the same multiple levels of insulator layers, to be used to accommodate metal plug structures, has been developed. The process features the use of a polysilicon stop layer, used at the bottom of the stack of large diameter via holes, protecting underlying components of the underlying integrated circuit, from the dry and wet etching procedures used for the creation of the stack of large diameter via holes. The process also features the formation of metal spacers, on the sides of the large diameter via holes, created simultaneously during the formation of metal plug structures, and used again to protect the multiple levels of insulator layer, that would have been exposed, if left unprotected, during a wet etching procedure.

Abstract: A room temperature wet chemical digital etching technique for, gallium arsenide or other semiconductor material. Hydrogen peroxide and an acid are used in a two step etching cycle to remove the gallium arsenide in approximately 15 .ANG. limited increments. In the first step of the cycle, gallium arsenide is oxidized by, for example, 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of, for example, 14-17 .ANG. for time periods from 15 seconds to 120 seconds. The second step of the cycle removes this oxide layer with an acid that does not attack unoxidized gallium arsenide. These steps are repeated in succession using new reactant materials and cleaning after each reactant (to prevent reactant contamination) until the desired etch depth is obtained. Experimental results are presented demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Abstract: Polystringers that cause NAND-type memory core cells to malfunction are removed. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. Next, the device is exposed to oxygen gas in a high temperature environment to oxidize the surface of the device, and in particular to remove the polystringers.

Abstract: The evaluating method includes: dipping a mirror-polished silicon wafer in a dilute hydrofluoric acid; washing the surface of the silicon wafer; subjecting the surface-washed silicon wafer to a heat treatment in an oxygen atmosphere to form a thermal oxidation film; forming a predetermined number of polycrystalline silicon electrodes having a predetermined area on the thermal oxidation film; applying a voltage to each electrode between the predetermined number of polycrystalline silicon electrodes and the silicon wafer; and judging the quality of the mirror-polishing process of the silicon wafers in accordance with the breakdown electric field intensity of the leakage current obtained by measuring the oxide film insulation.

Abstract: A metal utilized for forming a silicide film is left even after completion of the reaction to produce silicide. A conductive film made of a material other than the metal is grown on the metal. A local interconnection overlapping the silicide layer is formed by the conductive film and the metal remaining after formation of silicide.

Abstract: A bonded substrate and a process for its production is provided to solve the problem involved in the heat treatment which tends to cause troubles such as break, separation and warpage of the substrates bonded. A single-crystal semiconductor epitaxially grown on a porous semiconductor substrate is bonded to an insulator substrate, and the semiconductor substrate is removed by etching, grinding, or a combination of the both, where no heat treatment is carried out or, even if carried out, only once.

Abstract: An SOI substrate and method for forming is described incorporating the steps of forming strained layers of Si and/or SiGe on a first substrate, forming a layer of Si and/or S.sub.i O.sub.2 over the strained layers, bonding a second substrate having an insulating layer on its upper surface to the top surface above the strained layers, and removing the first substrate. The invention overcomes the problem of forming strained Si and SiGe layers on insulating substrates.

Abstract: An etching material comprising at least phosphoric acid, acetic acid, and nitric acid, with chromic acid added therein. Also claimed is an etching process using the etching material above, provided that the process comprises selectively etching, by using the solution, an aluminum oxide layer formed on the surface of a material containing aluminum as the principal component thereof.

Abstract: A new method of changing the surface property of a nitride film from hydrophobic to hydrophillic and thereby reducing nitride residue after photolithography is described. A pad oxide layer is provided on the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. Thereafter, the surface of the nitride layer is cleaned wherein the surface is changed from hydrophobic to hydrophillic. The nitride layer is coated with a photoresist film which is developed to leave an opening where the field oxidation region is to be formed. The nitride layer and pad oxide layer are etched away where they are not covered by the photoresist film to expose a portion of the semiconductor substrate. The exposed portion of the semiconductor substrate is oxidized to form a field oxidation region in the fabrication of an integrated circuit.

Abstract: The invention relates to a method for cleaning vias in electronic component substrates prior to metallization thereof.

Abstract: This is a method for improving contact openings during the manufacture of an integrated circuit. The process of forming a contact in an integrated circuit is often carried out rapidly, with imperfect control. As a result, incomplete removal of the insulating material may occur within the contact opening. In addition, the substrate material may be damaged to some extent within the contact opening by the contact formation process. In either case, high electrical resistance within the contact may result. Photo-resist may leave residue within the contact opening, low surface dopant concentrations, and insulative layer discontinuities may cause increased electrical resistance within the contact. A sequential application of two types of aqueous etchants will smooth the contact sidewall and remove a thin layer of relatively low dopant concentration at the surface of the substrate and other debris which may remain from the contact formation process and thereby allow lower resistance contacts to be formed.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: A method for forming patterned conductor metallization layers adjoining patterned barrier metallization layers upon semiconductor substrates. A semiconductor substrate is provided which has formed upon its surface a patterned second masking layer upon a blanket first masking layer. The patterned second masking layer is formed from a photoresist material and the blanket first masking layer is formed from a silicon oxide material, a silicon nitride material or a silicon oxynitride material. Beneath the blanket first masking layer resides a blanket multi-layer metallization stack which includes a blanket conductor metallization layer adjoining a blanket barrier metallization layer. The blanket first masking layer and the upper lying blanket metallization layer of the blanket conductor metallization layer and the blanket barrier metallization layer are successively patterned through a Reactive Ion Etch (RIE) process using as the etch mask the patterned second masking layer.

Abstract: In the present invention, a first protective layer formed over a diaphragm is prevented from being etched unnecessarily at the time of etching a second protective layer, and the detection accuracy of the diaphragm is improved.In a process for producing a semiconductor pressure sensor, a first protective layer 4, a metal layer 8 and a second protective layer 6 are successively formed by deposition over a diaphragm 1a, and the second protective layer 6 is removed by etching so that the second protective layer 6 is left on a predetermined portion of an electrode 5. Since the metal layer 8 acts as an etching stopper layer at the time of removing the second protective layer 6 by etching, the first protective layer 4 over the diaphragm 1a is prevented from being etched. The metal layer 8 is removed by etching thereafter so that only the first protective layer 4 is formed over the diaphragm 1a.

Abstract: Reduced undercutting of a titanium-tungsten layer in a ball limiting metallurgy (BLM) is achieved in the preparation of solder ball interconnect structures by removing metal oxide film which forms on the titanium-tungsten layer and etching the titanium-tungsten layer in different steps. Removing the metal oxide with an acid solution prior to etching the titanium-tungsten layer provides for a more uniform etch of the titanium-tungsten layer.