Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

Abstract: A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.

Abstract: An etchant and a method for fabricating a substrate for an electronic device using the etchant where the etchant contains a predetermined additive to control the etch rate of a Cu deposition layer (containing Cu, Cu/Ti, or Cu/Ta) over passage of time. Some examples of the additive may include a chelate having the —COOH group, a chemical compound containing a Cu ion, and a deoxidizer containing sulfur (S). The method includes forming a metal thin film containing copper (Cu) on a substrate, selectively exposing the metal thin film, and etching at least one of the exposed and the unexposed portions on the metal thin film with the additive-containing etchant to control the Cu etch rate over time against the number of sheets of processed substrates. The use of the additive-containing etchant results in improved yield and reduction in production costs because of less frequent etchant replacements.

Abstract: Within a method for forming a dual damascene aperture there is surface treated a first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through the second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Within the present invention, when forming the trench through the second dielectric layer an endpoint is determined by detecting a difference between the second bulk composition and the first surface composition.

Abstract: A method for removing a polysilicon layer from a non-silicon layer comprising the following steps. A structure having a non-silicon layer formed thereover is provided. A first polysilicon layer is formed upon the non-silicon layer. The first polysilicon layer is removed from over the non-silicon layer to expose the non-silicon layer using a NH4OH:DIW dip solution process having a NH4OH:DIW ratio of from about 1:2 to 1:8. Whereby the non-silicon layer is substantially unaffected by the NH4OH:DIW dip solution process.

Abstract: A semiconductor device, which uses a crystalline silicon film having high crystallinity and a flat surface with few ridges and has high characteristics, and a method of manufacturing the semiconductor device are provided. According to the manufacturing method, a first amorphous silicon film is crystallized by using a heat treatment. A second amorphous silicon film is formed on a first crystalline silicon film thus obtained as an under film, and the second amorphous silicon film is crystallized by irradiation of laser light, so that a silicon film having excellent crystallinity and a surface with few ridges is obtained. The first crystalline silicon film and the second crystalline silicon film having different crystal structures are used as an active layer of a thin film transistor.

Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layer and a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Abstract: A method for removing layers or layer systems from a substrate and subsequent application onto an alternative substrate. A porous breakaway layer is formed by anodization in hydrofluoric acid. Optionally, a stabilizing layer with lower porosity is previously produced on top of the breakaway layer. The oxide of the porous breakaway layer or the stabilizing layer is removed by brief contact with HF, and an epitaxial layer is applied on the porous breakaway layer or the stabilizing layer. The epitaxial layer or the layer system is then removed from the substrate, and the epitaxial layer or the layer system is applied onto an alternative substrate. Optionally, the stabilizing layer and/or residues of the breakaway layer are removed from the epitaxial layer.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography. In accordance with one embodiment of the invention, there is provided a method of fabricating a semiconductor structure including providing a relaxed Si1−xGex layer on a substrate; planarizing said relaxed Si1−xGex layer; and depositing a device heterostructure on said planarized relaxed Si1−xGex layer including at least one strained layer.

Abstract: The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In a process for forming metal interconnection contact holes on both a gate electrode including an Si-rich SiON film as a mask insulating film in a peripheral circuit region and on a semiconductor substrate, the metal interconnection contact hole is formed according to a three-step etching process using a photoresist film pattern exposing the intended locations of a metal interconnection contacts as an etching mask. Accordingly, contact properties are improved by preventing damage to the semiconductor substrate, thereby reducing leakage current and improving yield.

Abstract: The method for forming an isolation film in a semiconductor device includes the steps of providing a semiconductor substrate having at least a first insulation film formed thereon, and forming a trench in the first insulation film and the semiconductor substrate. Next, an insulation film pattern is formed. The insulation film pattern fills the trench and extends from the trench over a portion of the first insulation film. Afterwards, the first insulation film is etched. The etching of the first insulation film also results in etching of the insulation film pattern, but the insulation film pattern at the upper side wall edges of the trench is not etched.

Abstract: Methods and apparatus are used for electrochemical planarization of an electrically conductive material surface with varying topography from a partially fabricated integrated circuit, in which protruding regions of the conductive material are removed more quickly than recessed regions to thereby increase the planarity of the conductive material surface. This is accomplished by using dissolution electrochemistry. The partially fabricated integrated circuit is used as the anode in an electrochemical cell, with the anode and cathode active surfaces positioned in very close proximity. By using highly resistive electrolyte and moving the anode and cathode progressively closer during electrochemical dissolution, the electrically conductive material surface is effectively planarized.

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover, the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said silicon nitride layer. Suitable materials for the buffer layer that have been found to be effective include silicon oxide and silicon oxynitride with the latter offering some additional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

Abstract: An efficient method of interconnecting a solar cell having at least two front surface contacts with a diode mounted on a front surface of the solar cell includes the act of forming at least a first recess on a front surface of the solar cell. A first solar cell contact is formed on the front surface in the first recess. A second solar cell contact is formed on the front surface. At least a first bypass diode is positioned at least partly within the recess. The bypass diode has a first diode contact and a second diode contact. The first solar cell contact is interconnected with the first diode contact. The second solar cell contact is interconnected with the second diode contact.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.

Abstract: Methods of selectively removing post-etch polymer material and dielectric antireflective coatings (DARC) without substantially etching an underlying carbon-doped low k dielectric layer, and compositions for the selective removal of a DARC layer and post-etch polymer material are provided. A composition comprising trimethylammonium fluoride is used to selectively etch a dielectric antireflective coating layer overlying a low k dielectric layer at an etch rate of the antireflective coating layer to the low k dielectric layer that is greater than the etch rate of the antireflective coating to a TEOS layer. The method and composition are useful, for example, in the formation of high aspect ratio openings in low k (carbon doped) silicon oxide dielectric layers and maintaining the integrity of the dimensions of the formed openings during a cleaning step to remove a post-etch polymer and antireflective coating.

Abstract: A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer.

Abstract: A method of forming metal contacts in a semiconductor device having an active metal contact region and a bit line contact region is provided. In the method, a contact pad is formed in the active metal contact region and the bit line contact region using a conductive plug. An etch stopper is formed on the upper sides of the conductive plug. A portion of a lower interlayer dielectric layer is etched so that the etch stopper protrudes above the lower interlayer dielectric layer. A bit line stack is formed in the bit line contact region. An etch stopper is formed in the active metal contact region. An upper interlayer dielectric layer is etched to expose the surfaces of the etch stopper and bit line capping layer pattern of the bit line stack. The exposed surfaces of the etch stopper and bit line capping layer pattern are etched to form a contact hole which exposes the conductive plug and a bit line conductive layer of the bit line stack. The contact hole is filled with a conductive layer.

Abstract: A method for preventing or reducing corrosion of copper containing semiconductor features during chemical mechanical polishing (CMP) including providing a semiconductor wafer polishing surface including a copper layer overlying a copper filled anisotropically etched feature; polishing the semiconductor wafer polishing surface according to a first CMP process to remove at least a portion the copper layer to reveal a portion of an underlying barrier/adhesion layer; polishing the semiconductor wafer polishing surface according to a second CMP process including applying a neutralizing solution; polishing the semiconductor wafer polishing surface according to a third CMP process including applying a copper corrosion inhibitor solution; and, polishing the semiconductor wafer polishing surface according to at least a fourth CMP process to remove a remaining portion of the underlying barrier/adhesion layer.

Abstract: In a method for fabricating a silicon-on-insulation wafer having fully processed devices in its upper-most silicon layer, the wafer is reduced in thickness from a surface opposite to the device layer surface by performing a first etching step of etching the semiconductor substrate to the insulation layer, so that the insulation layer functions as an etch stop layer, and a second etching step of etching the insulation layer to the semiconductor device layer, so that the semiconductor device layer functions as an etch stop layer. The semiconductor device layer is then separated into individual chips for fabricating a three-dimensionally integrated circuit thereof.

Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

Abstract: A method for avoiding erosion of a conductor structure during a procedure of removing etching residues is provided. The method provides a semiconductor structure and the conductor structure formed therein. A cap layer is formed on the conductor structure and the semiconductor and a dielectric layer formed thereon. The dielectric layer and the cap layer are then etched to partially expose the conductor structure. The etching residues are removed with an amine-containing solution and the amine-containing solution is removed with an intermediate solvent to avoid erosion of the exposed conductor structure. As a key step of the present invention, the intermediate solvent comprises N-methylpyrrolidone or isopropyl alcohol and can protect the conductor structure from erosion.

Abstract: A method for cutting Group III nitride semiconductor light emitting element comprises the step of discharge-etched on a front face of a chip or cutting channel of a substrate; and breaking on a back surface of the discharge-etching face to be formed with dies. This method is different from the prior art dicing saw and point scribe. Thus, the cutting time is shortened. The consumption of the diamond knife from cutting is reduced. The yield ratio of dies is improved and the outlook is also improved.

Abstract: An improved method of forming a semiconductor device is described. The method comprises forming a dielectric layer on a substrate, forming a photoresist layer on the dielectric layer, then patterning the photoresist layer to define a region to be etched. After forming an etched region within the dielectric layer, the photoresist layer is removed and the etched region is cleaned. The etched region is cleaned by applying a buffered oxide etch dip, followed by an amine based dip.

Abstract: A method of manufacturing a semiconductor device, having a resist-removing step which is improved so as not to etch a peripheral material and damage the peripheral material is provided. A resist pattern is formed on a substrate. Using the resist pattern as a mask, the substrate is etched. A surface-deteriorated layer of the resist pattern is removed by a first chemicals treatment. A bulk portion of the resist pattern is removed by a second chemicals treatment.

Abstract: Methods of controlling environmental conditions within a fluidic system, where such environmental conditions can affect the operation of the system in its desired function, and fluidic channels, devices and systems that are used in practicing these methods. Such environmental conditions are generally directed to the fluids themselves, the movement of such fluids through these systems, and the interaction of these fluids with other components of the system, e.g., other fluids or solid components of the system.

Abstract: A chemical-mechanical polishing apparatus has a surface formed on a solid aggregate comprising a solid suspension of abrasive particles in a light sensitive material. An ultraviolet light source exposes a thin top layer of the surface and a developing fluid develops the exposed surface. The developing fluid dissolves the UV-exposed top portion of the aggregate and a polishing slurry is formed of the developing fluid and the released abrasive particles. The aggregate surface remaining after developing acts as a polishing surface. The polishing slurry is used during chemical-mechanical polishing of a processed semiconductor wafer. After polishing, a rinsing fluid is dispensed to remove used slurry from the polishing aggregate.

Abstract: A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers.

Abstract: A method for forming a protection device with slope laterals is provided. Firstly, providing a semiconductor substrate having a plurality of alternative first sacrificial layers and second sacrificial layers formed thereon. A first etching step is performed to remove one portion of each of the first sacrificial layers and thereby expose one portion of each lateral of each of the second sacrificial layers. Subsequently, performing a second etching step to remove one portion of the lateral of the second sacrificial layer. Then, repeatedly and alternately performing the first etching step and the second etching step until completely removing the first sacrificial layers and then obtaining a plurality of protection devices formed of the second sacrificial layers each of which having slope laterals.

Abstract: A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench.

Abstract: A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation layer to be located between the outer peripheral extremity of the semiconductor layer and that of the support member and hence the semiconductor layer and the insulation layer produce a stepped profile.

Abstract: A process for manufacturing damascene wiring in integrated circuits is described. Trenches in the top most layer are first over-filled with a soft metal (such as copper) and then a relatively thin layer of a hard material such as tantalum, tantalum nitride, titanium, titanium nitride etc is deposited on the copper surface Under a first set of control conditions CMP is then applied for just long enough to selectively remove this hard material layer from peaks in the copper surface while leaving it intact in the valleys. The control conditions for CMP are then adjusted so that CMP can proceed with material at the peaks being removed at a significantly faster rate than in the valleys. Thus, when the point is reached that all copper outside the trenches has been removed, the trenches are found to be just filled with a flat layer that has no dishing.

Abstract: In a device having a structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are layered on a silicon substrate in that order from a bottom position, CMP polishing is performed in order for a top layer of a silicon oxide film to residually exist. An etchant for selectively etching a silicon nitride film only is then used. Only a nitride film in a scratched portion, the depth of which is deeper than the depth of the silicon oxide film, is selectively etched, and only the scratch, the depth of which is deeper than the depth of the residual film of the silicon oxide film, is exposed.

Abstract: By adopting an electrolytic plating method in forming the bump, the drawbacks of the conventional electrolytic plating method should be avoided. For example, the necessity of adopting a lead wiring for each wiring or the like should be eliminated. On the surface of a metal base, a resist film (first resist film) having a negative pattern for forming a wiring film and a resist film (second resist film) having a negative pattern for forming the bump or the pad is formed. By using these films as masks, electrolyic plating of a bump material film is conducted to form the bump. Subsequently, after only the second film is removed. By using the first resist film as a mask, electrolytic plating is then conducted to form a wiring film.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon. The process comprising the steps of aligning said area of said wafer, such as an alignment mark on the wafer, to an etchant dispensing apparatus, placing the surface of the wafer adjacent at least a portion of an annular portion of the etchant dispensing apparatus, dispensing at least one etchant onto said area of said wafer, such as an alignment mark, and removing the at least one etching from the wafer.

Abstract: A top IC die is removed from a bottom IC die in a multichip IC package while substantially preserving interconnect of the bottom IC die for proper fault isolation during testing of the multichip IC package. The top IC die is attached to the bottom IC die with a die attach material within the multichip IC package. The top IC die has a first area that is smaller than a second area of the bottom IC die, and the top IC die is disposed inward from any edge of the bottom IC die such that a perimeter area of the bottom IC die is outside the top IC die. A predetermined area of the top IC die is exposed with the predetermined area being smaller than the first area of the top IC die. The predetermined area is disposed inward from any edge of the top IC die. The first area of the top IC die outside the predetermined area remains covered, and the perimeter area of the bottom IC die remains covered.

Abstract: An efficient method of interconnecting a solar cell having at least two front surface contacts with a diode mounted on a front surface of the solar cell includes the act of forming at least a first recess on a front surface of the solar cell. A first solar cell contact is formed on the front surface in the first recess. A second solar cell contact is formed on the front surface. At least a first bypass diode is positioned at least partly within the recess. The bypass diode has a first diode contact and a second diode contact. The first solar cell contact is interconnected with the first diode contact. The second solar cell contact is interconnected with the second diode contact.

Abstract: A semiconductor substrate is dipped into a contaminating treatment liquid whose pH value is controlled depending on the property of metal impurities, so as to produce a sample contaminated with metal of a desired concentration. Alternatively, a semiconductor substrate is kept in a hermetic container along with desired organic matter so as to produce a sample contaminated with the organic matter in the form of vapor obtained through vapor-liquid or vapor-solid equilibrium.

Abstract: A method of purifying an alkaline solution is capable of extremely efficiently nonionizing metallic impurity ions in an alkaline solution at a low cost. A method of etching semiconductor wafers in turn is capable of etching semiconductor wafers using the purified alkaline solution without deteriorating the quality of the semiconductor wafers. A reducing agent having an oxidation potential lower than a reversible electrode potential of metallic ions existing in the alkaline solution is dissolved in the alkaline solution to thereby nonionize the metallic ions existing in the alkaline solution.

Abstract: A pre-stripping treatment solution for treatment of metal surfaces before stripping photoresist which has been used for patterning a metal layer. Also provided is a method of removing the photoresist, and a method of manufacturing semiconductor devices using the above solution and method. In one aspect of the invention, the photoresist is first ashed. The ashed resultant structure is then treated, prior to stripping of the photoresist, with a pre-stripping treatment solution of an organic acid solution having a carboxyl group is mixed with deionized water at a volume ratio of 1:0 to 1:100.

Abstract: Dents are formed on the silicon oxide film 3 formed on a silicon substrate 1; thereon are formed a barrier metal film 4 and a copper plating film 5 in this order. Then, chemical mechanical polishing is conducted for planarization. Polishing is conducted for a given time and, when the barrier metal film 4 has been exposed, a hydrofluoric acid-containing solution is fed. As the hydrofluoric acid-containing solution, a buffered hydrofluoric acid or the like is used.

Abstract: A fabrication method for a capacitor having high capacitance that increases capacitance of a capacitor and consequently decreases defective semiconductor devices includes: forming a doped first polysilicon layer pattern on a semiconductor substrate; forming a silicide film pattern on the first polysilicon layer pattern; annealing the semiconductor substrate; sequentially forming a first insulating film and a second insulating film over the silicide film pattern; forming a contact hole to expose a portion of the silicide film pattern and then sequentially placing the semiconductor substrate in an etchant solution and a buffered etchant solution to remove a portion of the first insulating film formed on the silicide film pattern; forming a first capacitor electrode on a portion of an upper surface of the second insulating film pattern and the silicide film pattern, and at inner walls of the contact hole; and forming a dielectric layer on an outer surface of the lower electrode and then a second capacitor electr

Abstract: In a method for manufacturing a semiconductor device, a barrier metal disposed on a metallic thin film for forming a thin film resistor is patterned by wet-etching. The wet-etching produces a residue of the barrier metal. The residue is removed after the oxidation thereof. Accordingly the residue is completely removed. As a result, the patterning of the thin film resistor is stably performed, and short-circuit does not occur to a wiring pattern disposed above the barrier metal.

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.

Abstract: A method for fabricating a passivation layer on a metal pad. A conformal first silicon dioxide layer is formed on a substrate having a metal pad. A conformal first silicon nitride layer is formed on the first silicon dioxide layer, and then a second silicon dioxide layer is formed on the first silicon nitride layer by high density plasma chemical vapor deposition. The second silicon dioxide layer is planarized to expose the first silicon nitride layer. A portion of the first silicon nitride layer aligned over the metal pad is removed to expose the first silicon dioxide layer. A second silicon nitride layer is formed to cover the first silicon dioxide layer and the second silicon dioxide layer. In the above process, a thickness of the first silicon dioxide layer and a thickness of the second silicon nitride layer are precisely controlled.

Abstract: A silicate glass is selectively etched employing a composition containing a fluoride containing compound and certain organic solvents. Preferred compositions also include water.

Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.