Abstract: In order to mitigate erosion of exposed processing elements in a processing system by the process and any subsequent contamination of the substrate in the processing system, processing elements exposed to the process are coated with a protective barrier. The protective barrier comprises a protective layer that is resistant to erosion by the plasma, and a bonding layer that improves the adhesion of the protective layer to the processing element to mitigate possible process contamination by failure of the protective layer.

Abstract: A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.

Abstract: A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

Abstract: A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.

Abstract: It is an object of the present invention to provide a method for manufacturing SIMOX wafer, wherein roughness Rms of a measurement area of 10 square micrometers in a surface of an SOI layer and roughness Rms of a measurement area of 10 square micrometers in an interface between the SOI layer and a BOX layer can be reduced respectively and a SIMOX obtained by the method. The method is to manufacture a SIMOX wafer comprising; a step of forming a first ion-implanted layer 12 containing highly concentrated oxygen within a wafer 11; a step of forming a second ion-implanted amorphous layer 13; and a high temperature heat treatment step of transforming the first and second ion-implanted layers into a BOX layer 15 by holding the wafer at a temperature between 1300° C.

Abstract: A SIMOX wafer is produced by implanting an oxygen ion, in which a hydrogen ion is implanted at a dose of 1015?1017/cm2 before or after the step of the oxygen ion implantation.

Abstract: A system and method for selectable area laser treatment of a substrate, such as thin film transistors, the system including a holder holding a substrate in proximity to reactant, and laser beams each addressing independently selectable mutually set apart locations on the substrate to induce a reaction between the substrate and the reactant.

Abstract: A SIMOX wafer having a BOX layer with a thin film thickness is obtained without a reduction in productivity or deterioration in quality. In a method for manufacturing a SIMOX wafer comprising: a step of forming a first ion-implanted layer in a silicon wafer; a step of forming a second ion-implanted layer that is in an amorphous state; and a high-temperature heat treatment step of maintaining the wafer in an oxygen contained atmosphere at a temperature that is not lower than 1300° C. but less than a silicon melting point for 6 to 36 hours to change the first and the second ion-implanted layers into a BOX layer, a gas containing chlorine that is not less than 0.1 volume % but less than 1.0 volume % is mixed into an atmosphere during temperature elevation in the high-temperature heat treatment.

Abstract: A treatment method of annealing and doping a semiconductor including irradiating a semiconductor layer (13) formed on a substrate (11) with a laser beam (a), thereby melting at least a part of the semiconductor layer; irradiating a target material (2) including atoms with which the semiconductor layer is to be doped with the laser beam (a?), thereby ablating the atoms of the target material; and doping the melted semiconductor layer with the ablated atoms.

Abstract: An impurity can be introduced into a semiconductor layer of a workpiece to affect the oxidation and the relative concentration of one element with respect to another element within the semiconductor layer. The impurity can be selectively implanted using one or more masks, manipulating the beam line of an ion implant tool, moving a workpiece relative to the ion beam, or the like. The dose can vary as a function of distance from the center of the workpiece or vary locally based on the design of the electronic device or desires of the electronic device fabricator. In one embodiment, the impurity can be implanted in such a way as to result in a more uniform SiGe condensation across the substrate or across one or more portions of the substrate when the semiconductor layer includes a SiGe layer.

Abstract: A process for passivating polysilicon and a process for fabricating a polysilicon thin film transistor. A polysilicon layer is formed. Next, high-pressure annealing is performed using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, a nitrogen-containing gas, or mixtures thereof to passivate the polysilicon layer.

Abstract: The present invention provides a method for measuring an implantation depth of an impurity injected into a wafer by an ion implantation device, using a measurement device and monitoring whether the measured implantation depth of impurity falls within an allowable range, comprising the steps of using, as a measuring wafer, a wafer having an insulating film and an Si layer formed on the insulating film with a thickness of a 1000 ? unit or less; implanting the impurity in the measuring wafer from above the surface of the Si layer, corresponding to a main surface of the measuring wafer and heat-treating the measuring wafer; and measuring surface resistivity of the main surface of the heat-treated measuring wafer by the measurement device and detecting, as an implantation depth of the impurity from the main surface, a concentration peak depth from the main surface, which corresponds to the surface resistivity and at which a concentration of the impurity implanted in the measuring wafer reaches a peak.

Abstract: An oxidation method is capable of forming oxide films in an improved interfilm thickness uniformity. The oxidation method includes the steps of supplying an oxidizing gas and a reducing gas into a processing vessel 22 capable of being evacuated and holding a plurality of workpieces W arranged at predetermined pitches, and creating a process atmosphere containing active oxygen species and active hydroxyl species in the processing vessel 22 through the interaction of the oxidizing gas and the reducing gas. At least either of the oxidizing gas and the reducing gas is jetted into an upstream region S1, a middle region S2 and a downstream region S3, with respect to the flowing direction of the gas, of a processing space S containing the workpieces W.

Abstract: An oxidation method for a semiconductor process, which oxidizes a surface of a target substrate, includes heating a process container that accommodates the target substrate, and supplying hydrogen gas and oxygen gas into the process container while exhausting the process container. The oxidation method also includes causing the hydrogen gas and the oxygen gas to react with each other in the process container at a process temperature and a process pressure to generate water vapor, and oxidizing the surface of the target substrate by the water vapor. The process pressure is set at 2000 Pa (15 Torr) or more.

Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor wafer. The dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.

Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

Abstract: The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

Abstract: In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made of the material for forming the floating gate and which is exposed to an oxidizing atmosphere in order to coat the sidewalls. At the same time, other regions of the structure have an insulating oxide layer. At a point in time prior to the action of an oxidizing atmosphere, nitrogen is implanted into the material of the floating gate in a quantity that appreciably reduces the oxidation at the sidewalls thereof.

Abstract: A method for fabricating a semiconductor device for reducing coupling noise resulting from high integration of devices, comprises the steps of forming a plurality of metal wiring leads spaced from each other by a predetermined distance and arranged on a semiconductor substrate having a predetermined under layer; forming an insulating interlayer on an entire surface of the semiconductor substrate so that the metal wiring leads are covered with the insulating interlayer; and ion-implanting conductive impurities having a plurality opposite to each other into side end layers of the insulating interlayer disposed between the metal wiring leads so as to reduce the internal charges electrified due to an applied external electric field.

Abstract: Disclosed is an ion implantation method capable of preventing a channeling phenomenon caused by a lattice structure of a semiconductor substrate. The ion implantation method includes the steps of forming a predetermined mask pattern on the semiconductor substrate, performing an ion implantation process with respect to the semiconductor substrate exposed by the predetermined mask without forming a tilt angle, thereby forming an impurity area in the semiconductor substrate, and applying vibration to a lattice structure of the semiconductor substrate when the ion implantation process is carried out with respect to the semiconductor substrate.

Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.

Abstract: A p-GaN layer 5 comprising materials such as a Group III nitride compound semiconductor is formed on a sapphire substrate 1 through MOVPE treatment, and a first metal layer 6 made of Co/Au is formed thereon. Then in a planar electron beam irradiation apparatus using plasma, electron beams are irradiated to the p-GaN layer 5 through the first metal layer 6. Accordingly, the first metal layer 6 prevents the surface of the p-GaN layer 5 from being damaged and resistivity of the p-GaN layer 5 can be lowered. Next, a second metal (Ni) layer 10 is formed on the first metal layer 6. And the first metal layer 6 is etched through the second metal layer 10 by using fluoric nitric acid. As a result, the first metal layer is almost completely removed. Then a light-transmitting p-electrode 7 made of Co/Au is formed thereon. As a result, a p-type semiconductor having decreased contact resistance and lower driving voltage can be obtained and optical transmittance factor of the p-type semiconductor improves.

Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.

Abstract: A method of making a high quality thin dielectric layer includes annealing a substrate and a base oxide layer overlying a top surface of the substrate at a first temperature in a first ambient and annealing the substrate and base oxide layer at a second temperature in a second ambient subsequent to the first anneal. The first ambient includes an inert gas ambient selected from the group consisting of a nitrogen, argon, and helium ambient. Prior to the first anneal, the base oxide layer has an initial thickness and an initial density. The first anneal causes a first density and thickness change in the base oxide layer from the initial thickness and density to a first thickness and density, with no incorporation of nitrogen, argon, or helium of the ambient within the base oxide layer. The first thickness is less than the initial thickness and the first density is greater than the initial density.

Abstract: The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300° C. to 600° C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range of about 50° C. to 150° C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate.

Abstract: A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.

Abstract: A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.

Abstract: A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.

Abstract: A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate in which the strained semiconductor is a thin semiconductor layer having a thickness of less than 50 nm that is located directly atop an insulator layer of a preformed silicon-on-insulator substrate is provided. Wafer bonding is not employed in forming the SSOI substrate of the present invention.

Abstract: A method for manufacturing a semiconductor device is disclosed. One example manufacturing method includes successively depositing gate insulating layer forming material and gate electrode forming material on a semiconductor substrate and patterning the gate insulating layer forming material and the gate electrode forming material to form a gate insulating layer and a gate electrode. The example manufacturing method further includes performing a nitrogen ion-implantation to a front face of the substrate and annealing the substrate so as to form a re-oxidation layer that has different thickness on the sidewalls of the gate electrode and on the substrate. The example method results in semiconductor gate electrodes and sidewalls having different oxidation rates so that a thickness of the re-oxidation layer of the sidewalls of the gate electrode is relatively thickened.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.

Abstract: A method of forming a contact opening is provided. First, a substrate having a plurality of conductive structures formed thereon is provided. An ion implantation is performed. Thereafter, a thermal treatment is carried out to form a liner layer on the sidewall of the conductive structure and the exposed substrate. The liner layer on the sidewall of the conductive structure has a thickness smaller than the liner layer on the substrate surface. A spacer is formed on each side of the conductive structure and then an insulation layer is formed over the substrate. The insulation layer is patterned to form a contact opening between two neighboring conductive structures. Since the liner layer on the sidewall of the conductive structures is already quite thin, there is no need to reduce thickness through an etching operation and uniformity of the liner layer on the substrate can be ensured.

Abstract: A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an N2O atmosphere.

Abstract: A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.

Abstract: A method for forming a reliable and ultra-thin oxide layer, such as a gate oxide layer of an MOS transistor, comprises an annealing step immediately performed prior to oxidizing a substrate. The annealing step is performed in an inert gas ambient to avoid oxidation of the semiconductor surface prior to achieving a required low oxidizing temperature. Preferably, the annealing step and the oxidizing step are carried out as an in situ process, thereby minimizing the thermal budget of the overall process.

Abstract: A method for mask-free molecular or atomic patterning of surfaces of reactive solids is disclosed. Molecules adsorb at surfaces in patterns, governed by the structure of the surface, the chemical nature of the adsorbate, and the adsorbate coverage at the surface. The surface is patterned and then imprinted with the pattern by inducing localized chemical reaction between adsorbate molecules and the surface of the solid, resulting in an imprint being formed in the vicinity of the adsorbate molecules. When the imprinted molecular patterns are conjugated chains containing ? bonds along which electrical charge can flow the molecular patterns constitute molecular wires or the imprinted molecules constitute a molecular-scale device. The surface of the substrate can be doped by including n- or p-type dopants in the adsorbate molecules. These molecular wires are anchored to the substrate by using conjugated chains which can be chemically bound at intervals along the chains to the substrates.

Abstract: A method for forming a plurality of grooves of a semiconductor device having of a plurality of MOS transistors is provided. A plurality of photoresist patterns are formed on a semiconductor substrate. Ions are implanted on a portion of the semiconductor substrate using the plurality of photoresist patterns as a mask. The plurality of photoresist patterns are removed. An oxide layer is formed on the semiconductor substrate having the implanted ions by thermal oxidation. The plurality of grooves are formed on the semiconductor substrate by removing the oxide layer.

Abstract: A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.

Abstract: In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

Abstract: Methods for forming a patterned SOI region in a Si-containing substrate are provided which has geometries of about 0.25 ?m or less. The methods disclose each utilize a patterned dielectric mask that includes at least one opening having a size of about 0.25 ?m or less which exposes a portion of a Si-containing substrate. Oxygen ions are implanted through the opening using at least a base ion implantation process which is carried out at an oxygen beam energy of about 120 keV or less and an oxygen dosage of about 4E17 cm?2 or less. These conditions minimize erosion of the vertical edges of the patterned dielectric mask and minimize formation of lateral straggles.

Abstract: A single, or common, ion beam source is utilized for ion beam deposition (IBD) of defect-free multilayer coatings, e.g., multilayer, carbon-based protective overcoats for magnetic and/or magneto-optical (MO) data recording/information storage and retrieval media such as hard disks. According to the inventive methodology, a plurality of source gas supply means for supplying a single IBD source with different source gases for each of the layers of the multilayer are selectively operated in “vent” and “run” modes by means of a plurality of valves, the opening and closing of which are determined by a programmable gas flow controller. The inventive method and apparatus advantageously provide IBD of multilayer coatings with minimum cross-contamination of individual layers, at a reduced equipment cost and size obtained by elimination of the need for separate ion beam sources and associated vacuum pump for each constituent layer of the multilayer.

Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: A method of forming a contact opening is provided. First, a substrate having a plurality of conductive structures formed thereon is provided. An ion implantation is performed. Thereafter, a thermal treatment is carried out to form a liner layer on the sidewall of the conductive structure and the exposed substrate. The liner layer on the sidewall of the conductive structure has a thickness smaller than the liner layer on the substrate surface. A spacer is formed on each side of the conductive structure and then an insulation layer is formed over the substrate. The insulation layer is patterned to form a contact opening between two neighboring conductive structures. Since the liner layer on the sidewall of the conductive structures is already quite thin, there is no need to reduce thickness through an etching operation and uniformity of the liner layer on the substrate can be ensured.

Abstract: A method of preparing an oxidized metal surface is disclosed. The oxidized metal is placed in a controlled environment and carbon monoxide is allowed to flow over the oxidized metal while the controlled environment is maintained at temperature level where the metal oxide becomes less stable than carbon dioxide so that the carbon monoxide reacts with the metal oxide to form carbon dioxide, which is removed from the controlled environment.

Abstract: In accordance with one embodiment of the present invention, a method of forming an etch stop layer in a semiconductor structure is provided. A polysilicon layer on the semiconductor substrate and ions are implanted into the polysilicon layer to form an etch stop layer. An oxide layer can be provided between the semiconductor substrate and the polysilicon layer.

Abstract: A semiconductor device including an insulation film superior in both planarization and water resistance is obtained. In this semiconductor device, a first insulation film including impurities is formed on a conductive layer. A film is formed between the first insulation film and the conductive layer for substantially preventing impurities from entering the conductive layer. Water resistance of the first insulation film is improved since impurities are included in the first insulation film. By using an insulation film superior in planarization as the first insulation film, a first insulation film superior in both planarization and water resistance can be obtained. The film provided between the first insulation film and the conductive layer prevents the impurities of the first insulation film from entering the conductive layer. Therefore, reduction in the reliability of the conductive layer can be prevented.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N2 atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.

Abstract: The aim of the invention is a method for producing a layer (2) of a first material embedded in a substrate (1) comprising at least one second material. The method comprises the following stages: formation in the substrate (1), at the level of the desired embedded layer, of a layer of microcavities intended to serve as centers of nucleation to produce said first material in said second material, formation of precipitate embryos from the nucleation centers formed, the precipitate embryos corresponding to the first material, growth of the precipitates from the embryos through species concentration corresponding to the first material and carried to the microcavity layer.

Abstract: Process for the preparation of thin monocrystalline or polycrystalline semiconductor material films, characterized in that it comprises subjecting a semiconductor material wafer having a planar face to the three following stages: a first stage of implantation by bombardment (2) of the face (4) of the said wafer (1) by means of ions creating in the volume of said wafer a layer (3) of gaseous microbubbles defining in the volume of said wafer a lower region (6) constituting the mass of the substrate and an upper region (5) constituting the thin film, a second stage of intimately contacting the planar face (4) of said wafer with a stiffener (7) constituted by at least one rigid material layer, a third stage of heat treating the assembly of said wafer (1) and said stiffener (7) at a temperature above that at which the ion bombardment (2) was carried out and sufficient to create by a crystalline rearrangement effect in said wafer (1) and a pressure effect in the said microbubbles, a separation between the thin film