Reaction With Silicon Semiconductive Region (e.g., Oxynitride Formation, Etc.) Patents (Class 438/769)
  • Patent number: 7378358
    Abstract: A substrate-processing apparatus (100, 40) comprises a radical-forming unit (26) for forming the nitrogen radicals and oxygen radicals through a high-frequency plasma, a processing vessel (21) in which a substrate (W) to be processed is held, and a gas-supplying unit (30) which is connected to the radical-forming unit. The gas-supplying unit (30) controls the mixture ratio between a first raw material gas containing the nitrogen and a second raw material gas containing oxygen, and supplies a mixture gas of a desired mixture ratio to the radical-forming unit. By supplying the nitrogen radicals and oxygen radicals mixed at the controlled mixture ratio to the surface of the substrate, an insulating film having a desired nitrogen concentration is formed on the surface of the substrate.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: May 27, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Igeta, Shintaro Aoyama, Hiroshi Shinriki
  • Patent number: 7361613
    Abstract: A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ratio of subject nitrogen atoms to a total number of nitrogen atoms in the gate insulating film is 20% or smaller, wherein three bonds of each subject nitrogen atom are all coupled to silicon atoms and remaining three bonds of each of three silicon atoms connected to the subject nitrogen atom are all coupled to other nitrogen atoms.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: April 22, 2008
    Assignee: Fujitsu Limited
    Inventors: Mitsuaki Hori, Naoyoshi Tamura, Mayumi Shigeno
  • Patent number: 7358171
    Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Don Carl Powell
  • Patent number: 7358198
    Abstract: A method is provided with: arranging nitrogen atoms on a surface of a silicon substrate; performing a heat treatment in a hydrogen atmosphere so that the nitrogen atoms and silicon atoms existing on the surface of the silicon substrate are brought into a three-coordinate bond state; and forming a silicon oxide film on the silicon substrate with the three-coordinate bond state of nitrogen atoms and the silicon atoms being maintained.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: April 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutoshi Aoki, Koichi Kato, Katsuyuki Sekine, Ichiro Mizushima
  • Patent number: 7358595
    Abstract: Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD region in the substrate under the buffer pattern; forming a spacer on a top surface of the buffer pattern and sidewalls of the gate electrode; and forming a source/drain region in the substrate under the buffer pattern.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: April 15, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Eun Jong Shin
  • Patent number: 7335606
    Abstract: A NiSi layer over silicon that is thermally stable and can form even in the presence of oxides. The method of fabricating the nickel silicide layer includes providing a substrate comprising silicon, depositing a layer of at least a 3-component metal alloy comprising nickel on a surface of the substrate, and annealing the alloy and the substrate. The annealing temperature is less than 1000° C. The 3-component metal alloy can include Ni, Ti and Pt.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: February 26, 2008
    Assignee: Agency for Science, Technology and Research
    Inventors: Dongzhi Chi, Tek Po Rinus, Soo Jin Chua
  • Publication number: 20080014761
    Abstract: Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 17, 2008
    Inventors: Ritwik Bhatia, Li-Qun Xia, Chad Peterson, Hichem M'Saad
  • Patent number: 7304002
    Abstract: A method for oxidation of an object to be processed is provided wherein an oxide film can provide favorable film quality and a laminate structure of nitride film and oxide film can be obtained by a thermal oxidation of a nitride film. In a method for oxidation of a surface of an object to be processed in a single processing container 8 which can contain a plurality of objects to be processed, at least a nitride film is exposed on said surface, and said oxidation is performed by mainly using active hydroxyl/oxygen species in a vacuum atmosphere, setting a processing pressure to 133 Pa or below, and setting a processing temperature to 400° C. or above. Under these conditions, high interplanar uniformity is maintained and oxide films with favorable film quality are obtained by oxidizing nitride films on the surfaces of a plurality of objects to be processed.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: December 4, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuo Nishita, Tsukasa Yonekawa, Keisuke Suzuki, Toru Sato
  • Patent number: 7294553
    Abstract: A plasma-enhanced chemical vapor deposition process for depositing relatively high dielectric constant silicon nitride or oxynitride to form an MIM capacitor is described. The flow rate ratios for the silicon nitride layer are: silane-to-ammonia between 1:20 and 6:5 and silane-to-nitrogen flow between 1:40 and 3:5. A pressure in the process chamber is between 260 Pa and 530 Pa. The flow rate ratios for the silicon oxynitride layer are: silane-to-dinitrogen monoxide between 1:2 and 25:4 and silane-to-nitrogen between 1:100 and 1:10. A larger, non-stoichiometric amount of silicon is incorporated in the layers as the flow rate of the silicon precursor is increased. The layers are deposited in substeps in which the deposition is interrupted between successive substeps. The layer is exposed to an oxygen-containing plasma such that electrically conductive regions of the layer are converted into electrically insulating regions as a result of interaction with the plasma.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: November 13, 2007
    Assignee: Infineon Technologies AG
    Inventor: Mirko Vogt
  • Publication number: 20070259533
    Abstract: A semiconductor device includes: a structure comprising at least two heterogeneous layers having different stress levels; and a stress relief layer disposed between the two heterogeneous layers to relive a difference in the stress levels. The stress relief layer may include: a first layer formed over a first heterogeneous layer; a second layer formed over the first layer; and a third layer formed between the second layer and a second heterogeneous layer.
    Type: Application
    Filed: October 13, 2006
    Publication date: November 8, 2007
    Inventors: Hyun Ahn, Jeong-Hoon Park
  • Patent number: 7282457
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace is disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmosphere to 25 atmosphere N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 7250375
    Abstract: A method of processing a for an electronic device, comprising, at least: a nitridation step (a) of supplying nitrogen radicals on the surface of the electronic device substrate, to thereby form a nitride film on the surface thereof; and a hydrogenation step (b) of supplying hydrogen radicals to the surface of the electronic device substrate. By use of this method, it is possible to recover the degradation in the electric property of an insulating film due to a turnaround phenomenon which can occur at the time of nitriding an Si substrate, etc.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: July 31, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Toshio Nakanishi, Takuya Sugawara, Seiji Matsuyama, Masaru Sasaki
  • Patent number: 7235502
    Abstract: A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: June 26, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sriram S. Kalpat, Voon-Yew Thean, Hsing H. Tseng, Olubunmi O. Adetutu
  • Patent number: 7232772
    Abstract: A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a planar antenna.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: June 19, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Seiji Matsuyama, Takuya Sugawara, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki
  • Patent number: 7202184
    Abstract: The present invention relates to a semiconductor device fabrication method, which includes forming an inter metal dielectric on a semiconductor substrate having wirings and planarizing the inter metal dielectric through a chemical mechanical polishing, wherein the inter metal dielectric is formed by carrying out at least one cycle of depositing polycrystalline silicon, plasma-processing the polycrystalline silicon, and oxidizing the polycrystalline silicon.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: April 10, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae-Suk Lee
  • Patent number: 7192887
    Abstract: A method of manufacturing a MOS transistor is provided that achieves high-speed devices by reducing nitrogen diffusion to a silicon substrate interface due to redistribution of nitrogen and further suppressing its diffusion to a polysilicon interface, which prevents realization of faster transistors. An oxide film is exposed to a nitriding atmosphere to introduce nitrogen into the oxide film, and a thermal treatment process is performed in an oxidizing atmosphere. The thermal treatment process temperature in the oxidizing atmosphere is made equal to or higher than the maximum temperature in all the thermal treatment processes that are performed later than that thermal treatment process step.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: March 20, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 7189661
    Abstract: There are provided a method and an apparatus of forming an insulating layer including silicon oxynitride. The method includes performing a plasma treatment process for supplying a plasma reaction gas to a substrate to be treated after completing the annealing process. The apparatus includes a sealed processing room having gas supply and exhaust lines running thereto. A quartz inner tube and quartz inlet pipe both include holes therethrough, but in orthogonal directions to one another, to flow a reaction gas onto the wafers loaded within the sealed processing room.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: March 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Cheol-Kyu Yang, Woong Lee, Jae-Chul Lee, Hun-Hyeoung Leam
  • Patent number: 7183143
    Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 27, 2007
    Assignee: Macronix International Co., Ltd.
    Inventor: Tzu-Yu Wang
  • Patent number: 7166519
    Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.
    Type: Grant
    Filed: June 12, 2004
    Date of Patent: January 23, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song
  • Patent number: 7160818
    Abstract: An aspect of the present invention includes; a silicon oxynitride film having an oxynitride layer which is formed on at least the surface of a silicon substrate and in which nitrogen atoms are in a three-coordinate bond state, and a silicon oxide layer which is formed between said oxynitride layer and said silicon substrate.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: January 9, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutoshi Aoki, Koichi Kato, Katsuyuki Sekine, Ichiro Mizushima
  • Patent number: 7157360
    Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 2, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Hung-Yu Chiu, U-Way Tseng, Wen-Pin Lu, Cheng-Chen Huseh, Pei-Ren Jeng, Fu-Hsiang Hsu
  • Patent number: 7157384
    Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: January 2, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Melissa M. Tam, Dian Sugiarto, Chi-I Lang, Peter Wai-Man Lee, Li-Qun Xia
  • Patent number: 7135417
    Abstract: In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation between the clustered process chambers takes place in a controlled environment such as nitrogen or a vacuum. In some embodiments, the method provides an oxide layer to be used as part of the device, such as a tunnel oxide for a flash-EEPROM, or as a general gate oxide. Alternatively, the steps can be used to sculpt through oxidation various levels of a substrate, thereby allowing for embedded memory architecture. Cleaning between oxidation steps offers the advantage of providing a more defect-free oxide layer or providing access to a more defect-free level of substrate.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: November 14, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Randhir P. Thakur
  • Patent number: 7129187
    Abstract: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: October 31, 2006
    Assignee: Tokyo Electron Limited
    Inventor: Raymond Joe
  • Patent number: 7129128
    Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: October 31, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Patent number: 7125811
    Abstract: An oxidation method for a semiconductor process, which oxidizes a surface of a target substrate, includes heating a process container that accommodates the target substrate, and supplying hydrogen gas and oxygen gas into the process container while exhausting the process container. The oxidation method also includes causing the hydrogen gas and the oxygen gas to react with each other in the process container at a process temperature and a process pressure to generate water vapor, and oxidizing the surface of the target substrate by the water vapor. The process pressure is set at 2000 Pa (15 Torr) or more.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: October 24, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kazuhide Hasebe
  • Patent number: 7115532
    Abstract: This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: October 3, 2006
    Assignee: Micron Technolgoy, Inc.
    Inventor: Jon P. Daley
  • Patent number: 7101812
    Abstract: A process for forming and/or modifying dielectric films on semiconductor substrates is disclosed. According to the present invention, a semiconductor wafer is exposed to a process gas containing a reactive component. The temperature to which the semiconductor wafer is heated and the partial pressure of the reactive component are selected so that, sometime during the process, diffusion of the reactive components occurs through the dielectric film to the film/semiconductor substrate interface. Further, diffusion also occurs of semiconductor atoms through the dielectric film to an exterior surface of the film. The process of the present invention has been found well suited to forming and/or modifying very thin dielectric films, such as films having a thickness of less than 8 nm.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: September 5, 2006
    Assignee: Mattson Technology, Inc.
    Inventors: Ignaz Eisele, Alexandra Ludsteck, Jörg Schulze, Zsolt Nenyei, Waltraud Dietl, Georg Roters
  • Patent number: 7098147
    Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: August 29, 2006
    Assignee: Fujitsu Amd Semiconductor Limited
    Inventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
  • Patent number: 7098153
    Abstract: A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ratio of subject nitrogen atoms to a total number of nitrogen atoms in the gate insulating film is 20% or smaller, wherein three bonds of each subject nitrogen atom are all coupled to silicon atoms and remaining three bonds of each of three silicon atoms connected to the subject nitrogen atom are all coupled to other nitrogen atoms.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: August 29, 2006
    Assignee: Fujitsu Limited
    Inventors: Mitsuaki Hori, Naoyoshi Tamura, Mayumi Shigeno
  • Patent number: 7081419
    Abstract: The present invention provides a semiconductor device capable of substantially retarding boron penetration within the semiconductor device and a method of manufacture therefor. In the present invention the semiconductor device includes a gate dielectric located over a substrate of a semiconductor wafer, wherein the gate dielectric includes a nitrided layer and a dielectric layer. The present invention further includes a nitrided transition region located between the dielectric layer and the nitrided layer and a gate located over the gate dielectric.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: July 25, 2006
    Assignee: Agere Systems Inc.
    Inventors: Yuan Chen, Feng Li, Yi Ma, Kurt G. Steiner
  • Patent number: 7078815
    Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: July 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
  • Patent number: 7074701
    Abstract: A method of forming an opening in a stack of insulator layers featuring an underlying etch stop layer comprised of a tri-layer insulator composite, has been developed. The tri-layer insulator composite comprised of a bottom silicon rich, silicon oxide layer and a top silicon nitride layer, is first formed on a conductive region of a semiconductor substrate. After deposition of overlying insulator layers a photoresist shape is used as a etch mask to allow the desired contact or via hole shape to be defined in the overlying insulator layers via a first phase of an anisotropic dry etch procedure, with the first phase of the dry etching procedure terminating at the top surface of the silicon nitride layer. An over etch procedure used to insure complete removal of overlying insulator layer from the surface of the tri-layer insulator composite, is next performed as a second phase of the anisotropic dry etch procedure.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: July 11, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Lung Cheng, Shih-Chia Cheng
  • Patent number: 7064083
    Abstract: A composition and method of preparation, to provide silane compounds that are free of chlorine. The compounds are hexakis(monohydrocarbylamino)disilanes with general formula (I) ((R)HN)3—Si—Si—(NH(R))3??(I) wherein each R independently represents a C1 to C4 hydrocarbyl. These disilanes may be synthesized by reacting hexachlorodisilane in organic solvent with at least 6-fold moles of the monohydrocarbylamine RNH2 (wherein R is a C1 to C4 hydrocarbyl). Such compounds have excellent film-forming characteristics at low temperatures. These films, particularly in the case of silicon nitride and silicon oxynitride, also have excellent handling characteristics.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: June 20, 2006
    Assignee: L'Air Liquide, Societe Anonyme a Directoire et Conseil de Surveillance pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Christian Dussarrat, Jean-Marc Girard
  • Patent number: 7056842
    Abstract: According to the invention, while performing plasma-enhanced chemical vapor deposition on a substrate by exposing the substrate in a vacuum to a flow of particles generated by a plasma, which particles react to form a passivation layer on the substrate, a grid is interposed between the plasma and the substrate, thereby reducing the flow of charged particles towards the substrate while conserving a flow of neutral particles. The grid is formed of metal wires that are crossed at a pitch that is less than two or three times the Debye length (?D) of the plasma used, at least at the beginning of deposition. The aging properties of semiconductor components made by such a method is thereby improved.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: June 6, 2006
    Assignee: Alcatel
    Inventors: Christophe Jany, Michel Puech
  • Patent number: 7056835
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: June 6, 2006
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Patent number: 7057263
    Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: June 6, 2006
    Assignee: Micron Technology, Inc.
    Inventors: John T. Moore, Scott Jeffrey DeBoer, Mark Fischer, J. Brett Rolfson, Annette L. Martin, Ardavan Niroomand
  • Patent number: 7053007
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: May 30, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Patent number: 7041530
    Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 9, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Nunoshita, Ichiro Yamashita, Shigeo Yoshii
  • Patent number: 7037861
    Abstract: A method for oxidizing a nitride film is disclosed, which includes the steps of: providing a nitride film formed on an electrically conductive substrate; irradiating the nitride film with a light beam and getting close to the nitride film with a electrically conductive probe; and exerting a bias between the electrically conductive substrate and the electrically conductive probe. The method can oxidize the nitrides quickly and reduce the cost building a nano-structure in the nitride film. An apparatus for oxidizing a nitride film is also disclosed herewith.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: May 2, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Hung-Ming Tai, Forest Shih-Sen Chien
  • Patent number: 7033956
    Abstract: Methods for making memory devices are disclosed for forming germanium nanocrystals in an oxynitride layer. The method includes: forming a first dielectric layer over a substrate; forming an oxynitride layer containing germanium nanocrystals over the first dielectric layer; forming a second dielectric layer over the oxynitride layer; forming a gate over the second dielectric layer; and providing source, drain, and channel regions in the substrate. In one example, the channel region is positioned to correspond to at least a portion of the gate.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: April 25, 2006
    Assignee: ProMOS Technologies, Inc.
    Inventor: Yung-Hsien Wu
  • Patent number: 7030038
    Abstract: This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low temperature method for forming a thin, uniform oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; and stabilizing the substrate at a first temperature. The method further includes exposing the silicon surface to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, oxide film 16. This method is suitable for room temperature processing.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace, Berinder P. S. Brar
  • Patent number: 7019159
    Abstract: A composition and method of preparation, to provide silane compounds that are free of chlorine. The compounds are hexakis(monohydrocarbylamino)disilanes with general formula (I) ((R)HN)3—Si—Si—(NH(R))3??(I) wherein each R independently represents a C1 to C4 hydrocarbyl. These disilanes may be synthesized by reacting hexachlorodisilane in organic solvent with at least 6-fold moles of the monohydrocarbylamine RNH2 (wherein R is a C1 to C4 hydrocarbyl). Such compounds have excellent film-forming characteristics at low temperatures. These films, particularly in the case of silicon nitride and silicon oxynitride, also have excellent handling characteristics.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: March 28, 2006
    Assignee: L'air Liquide Societe Anonyme a Directoire et Conseil de Surveillance pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Christian Dussarrat, Jean-Marc Girard
  • Patent number: 7011734
    Abstract: A method of manufacturing a semiconductor device has the steps of: (a) evacuating a sputtering chamber to a pressure of 1.5×10?8 torr to 9×10?8 torr and heating a silicon substrate to a temperature of 330° C. to 395° C.; (b) sputtering Co on the heated silicon substrate; (c) after the step (b), forming a cap layer having a small oxygen transmission performance on the silicon substrate without exposing the silicon substrate in air; (d) after the step (c), performing primary annealing; (e) after the step (d), removing the cap layer and unreacted Co; and (f) after the step (e), performing secondary annealing by heating the silicon substrate to a temperature of 450° C. to 750° C.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: March 14, 2006
    Assignee: Fujitsu Limited
    Inventor: Kazuto Ikeda
  • Patent number: 7005393
    Abstract: A method of fabricating a semiconductor device which includes introducing, after a step of patterning a gate electrode, nitrogen atoms into an oxide film covering a device region on a semiconductor substrate, by exposing said oxide film to an atmosphere containing-nitrogen, such that said nitrogen atoms do not reach a region underneath said gate electrode, covering, after said step of introducing nitrogen atoms, said oxide film including said gate electrode by a CVD oxide film continuously without taking out said semiconductor substrate out of a processing chamber and forming a sidewall oxide film on a sidewall surface of said gate electrode by etching back said CVD oxide film.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: February 28, 2006
    Assignee: Fujitsu Limited
    Inventor: Kiyoshi Irino
  • Patent number: 6979658
    Abstract: A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode includes a first region located immediately underneath the gate electrode and a second region adjacent to the first region, wherein the first and second regions contain N atoms with respective concentrations such that the second region contains N with a higher concentration as compared with the first region.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: December 27, 2005
    Assignee: Fujitsu Limited
    Inventor: Kiyoshi Irino
  • Patent number: 6974779
    Abstract: A method is provided for forming a microstructure with an interfacial oxide layer by using a diffusion filter layer to control the oxidation properties of a substrate associated with formation of a high-k layer into the microstructure. The diffusion filter layer controls the oxidation of the surface. The interfacial oxide layer can be formed during an oxidation process that is carried out following deposition of a high-k layer onto the diffusion filter layer, or during deposition of a high-k layer onto the diffusion filter layer.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: December 13, 2005
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: David L O'Meara, Cory Wajda, Tsuyoshi Takahashi, Alessandro Callegari, Kristen Scheer, Sufi Zafar, Paul Jamison
  • Patent number: 6969689
    Abstract: A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 29, 2005
    Inventors: Krishnaswamy Ramkumar, Manuj Rathor, Biju Parameshwaran, Loren Lancaster
  • Patent number: 6960537
    Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: November 1, 2005
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Christophe Pomarede
  • Patent number: 6955996
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: October 18, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Daniel F Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur