Reaction With Silicon Semiconductive Region (e.g., Oxynitride Formation, Etc.) Patents (Class 438/769)
  • Patent number: 7935638
    Abstract: Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: James A. Culp, John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
  • Publication number: 20110092079
    Abstract: A method of producing an anti-reflection and/or passivation coating for semiconductor devices is provided. The method includes: providing a semiconductor device precursor 30 having a surface to be provided with the anti-reflection and/or passivation coating; treating the surface with ions; and depositing a hydrogen containing anti-reflection and/or passivation coating onto the treated surface.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 21, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nicolas AURIAC, Roland TRASSL
  • Patent number: 7928018
    Abstract: The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of <2.24 eV electron temperature, so that the generation of ions tending to damage any insulating film is reduced to thereby realize high-quality oxynitriding. Further, there is provided a process for producing an electronic appliance in which use is made of the method of plasma treatment.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: April 19, 2011
    Assignee: Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Yamauchi, Yukio Hayakawa
  • Publication number: 20110076857
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an oxide, nitride, or oxynitride film on the substrate by alternately repeating: (a) forming a layer containing a predetermined element on the substrate by supplying and exhausting first and second source gases containing the element into and from the process vessel; and (b) changing the layer containing the element into an oxide, nitride, or oxynitride layer by supplying and exhausting reaction gas different from the first and second source gases into and from the process vessel; and unloading the substrate from the process vessel. The first source gas is more reactive than the second source gas, and an amount of the first source gas supplied into the process vessel is set to be less than that of the second source gas supplied into the process vessel.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 31, 2011
    Applicant: HITACHI-KOKUSAI ELECTRIC INC.
    Inventors: Naonori AKAE, Yoshiro HIROSE, Yushin TAKASAWA, Yosuke OTA, Ryota SASAJIMA
  • Patent number: 7915177
    Abstract: In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration in the gate insulation film formed by the plasma nitridation is 5 to 20% in atomic percentage. Even without subsequent annealing, it is possible to effectively prevent a boron penetration phenomenon in the DRAM and to reduce traps in the film causing deterioration in driving capability of the device.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: March 29, 2011
    Assignee: Toyko Electron Limited
    Inventors: Tatsuo Nishita, Shuuichi Ishizuka, Yutaka Fujino, Toshio Nakanishi, Yoshihiro Sato
  • Patent number: 7910494
    Abstract: A gas delivery system for supplying a process gas from a gas supply to a thermal processing furnace, a thermal processing furnace equipped with the gas delivery system, and methods for delivering process gas to a thermal processing furnace. The gas delivery system comprises a plurality of regulators, such as mass flow controllers, in a process gas manifold coupling a gas supply with a thermal processing furnace. The regulators establish a corresponding plurality of flows of a process gas at a plurality of flow rates communicated by the process gas manifold to the thermal processing furnace. The gas delivery system may be a component of the thermal processing furnace that further includes a liner that surrounds a processing space inside the thermal processing furnace.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: March 22, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Anthony Dip, Eric J. Malstrom
  • Patent number: 7910493
    Abstract: A nitrided region is formed on a surface of a polysilicon layer by a nitriding treatment wherein plasma of a processing gas is generated by introducing microwaves into a processing chamber by a planar antenna having a plurality of slots. Then, a CVD oxide film or the like is formed on the nitrided region and after patterning the polysilicon layer and the like after the prescribed shape, and then, a thermal oxide film is formed by thermal oxidation on exposed side walls and the like of the polysilicon layer by having the nitrided region as an oxidation barrier layer. Thus, generation of bird's beak can be suppressed in the process at a temperature lower than the temperature in a conventional process.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: March 22, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Junichi Kitagawa, Takashi Kobayashi
  • Patent number: 7906440
    Abstract: A semiconductor device manufacturing method includes forming a gate insulating film on a semiconductor substrate; forming, on the gate insulating film, a multilayered structure including at least a polysilicon layer and a metal layer containing a refractory metal; forming a gate electrode by etching the multilayered structure; and performing a plasma process by a plasma processing apparatus, which is configured to supply microwaves into a process chamber from a planar antenna including a plurality of slots and thereby to generate plasma, at a process pressure of 133.3 to 1,333 Pa and a process temperature of 250 to 800° C. by using a process gas containing at least hydrogen gas and oxygen gas, thereby selectively oxidizing the polysilicon layer in the gate electrode.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: March 15, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Masaru Sasaki
  • Patent number: 7892984
    Abstract: Methods for reducing defects on the surface of a silicon oxynitride film are disclosed. In one embodiment, the methods include forming a silicon oxynitride film on a semiconductor substrate and heating the silicon oxynitride film to increase a hydrophilicity of a surface of the silicon oxynitride film prior to treating the surface of the silicon oxynitride film with a hydrofluoric acid.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: February 22, 2011
    Assignee: Spansion LLC
    Inventor: Noriyuki Yokonaga
  • Publication number: 20110003481
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 6, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
  • Patent number: 7851343
    Abstract: A method of forming an ohmic layer for a semiconductor device includes forming a metal layer on a Silicon Carbide (SiC) layer and forming an ablation capping layer on the metal layer. Laser light is impinged through the ablation capping layer to form a metal-SiC material.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: December 14, 2010
    Assignee: Cree, Inc.
    Inventors: Eric Mayer, Marc Alberti
  • Patent number: 7842621
    Abstract: The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2?T2N)/(T2?T1N)}×100 (1).
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: November 30, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Jiro Katsuki, Tetsuro Takahashi, Shuuichi Ishizuka
  • Patent number: 7838400
    Abstract: A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the dopant into the substrate, smoothing the concentration profile. The smoothed concentration gradient enables the oxide layer to act as a passivating layer. Anti-reflective coatings may be applied over the oxide layers, and a reflective layer may be applied on the surface opposite the doped surface to complete the solar cell.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Peter Borden
  • Patent number: 7829413
    Abstract: Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device includes a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: November 9, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Jea Hee Kim
  • Patent number: 7825036
    Abstract: A method of synthesizing silicon wires generally includes the steps of: providing a substrate; forming a copper catalyst particle layer on a top surface of the substrate; heating the reactive device at a temperature of above 450° C. in a flowing protective gas; and introducing a mixture of a protective gas and a silicon-based reactive gas at a temperature of above 450° C. at a pressure of below 700 Torr, thereby forming the silicon wires on the substrate.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: November 2, 2010
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yuan Yao, Li-Guo Xu, Shou-Shan Fan
  • Patent number: 7820504
    Abstract: Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: October 26, 2010
    Inventors: Daniela Brazzelli, Livio Baldi, Giorgio Servalli
  • Patent number: 7811896
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: October 12, 2010
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Bishnu Prasanna Gogoi
  • Publication number: 20100244114
    Abstract: A nonvolatile memory device includes: at least one first interconnection extending in a first direction; at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction; a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element; and an element isolation layer disposed between the memory cells. At least one dielectric film with a higher density than the element isolation layer is disposed on a sidewall surface of the memory cell.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 30, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takuya Konno, Hiroyuki Fukumizu, Kazuhito Nishitani
  • Patent number: 7799628
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: September 21, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Hsiang-Yi Wang, Cheng-Tung Lin, Chen-Hua Yu
  • Patent number: 7799703
    Abstract: A processing method includes a gas having a Si—CH3 bond supplied into a processing chamber after a target substrate to be processed is loaded into the processing chamber; and a silylation process performed on the target substrate. The internal pressure of the chamber by the supply of the gas having the Si—CH3 bond and the gas supply time are set to be within ranges where the silylation process can be performed while the internal pressure of the chamber is decreased to reach an eligible pressure level where the wafer can be unloaded after the internal pressure of the chamber is increased up to a preset pressure by the supply of the gas.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: September 21, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhiro Kubota, Naotsugu Hoshi, Yuki Chiba, Ryuichi Asako
  • Patent number: 7790627
    Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 7, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Patent number: 7776701
    Abstract: A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Alessandro C. Callegari, Michael A. Gribelyuk, Vijay Narayanan, Vamsi K. Paruchuri, Sufi Zafar
  • Patent number: 7776761
    Abstract: A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing a silicon oxide layer on the semiconductor substrate to form gate insulating layers having different thicknesses from one another on the first and second regions.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Sik Park
  • Publication number: 20100200963
    Abstract: The present invention relates to a process for preparing a functionalized Si/Ge-surface, wherein an unfunctionalised Si/Ge-surface is contacted in the presence of ultraviolet radiation with a C2-C50 alkene and/or a C2-C50 alkyne, and/or alkyne being optionally substituted and/or being optionally interrupted by one or more heteroatoms. The present invention further relates to articles or substrates comprising the functionalized Si/Ge-surface and the use of the functionalised Si/Ge-surface to prevent or to reduce adsorption of a biomolecule to an article or a substrate.
    Type: Application
    Filed: July 31, 2008
    Publication date: August 12, 2010
    Inventors: Catharina Gerarda Petronella Henrica Schroën, Michel Rosso, Johannes Teunis Zuilhof
  • Patent number: 7772129
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
  • Patent number: 7763317
    Abstract: Surface preparation of a compound semiconductor surface, such as indium antimonide (InSb), with a triflating agent, such as triflic anhydride or a trifluoroacetylating agent, such as trifluoroacetic anhydride is described. In one embodiment, the triflating or trifluoroacetylating passivates the compound semiconductor surface by terminating the surface with triflate trifluoroacetate groups. In a further embodiment, a triflating agent or trifluoroacetylating agent is employed to first convert a thin native oxide present on a compound semiconductor surface to a soluble species. In another embodiment, the passivated compound semiconductor surface is activated in an ALD chamber by reacting the triflate or trifluoroacetate protecting groups with a protic source, such as water (H2O). Metalorganic precursors are then introduced in the ALD chamber to form a good quality interfacial layer, such as aluminum oxide (Al2O3), on the compound semiconductor surface.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 27, 2010
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Willy Rachmady, Gregory J. Kearns, Darryl J. Morrison
  • Patent number: 7754557
    Abstract: A method for manufacturing a vertical CMOS image sensor related to a semiconductor device is disclosed. A high-temperature double annealing process and/or an additional passivation nitride film are selectively applied in order to improve dark leakage characteristics and also to prevent or reduce an incidence of circular defects, thereby enhancing the quality and reliability of the vertical CMOS image sensor.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: July 13, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong Su Park
  • Patent number: 7737048
    Abstract: A method for forming an oxide film includes a first in-situ steam generation (ISSG) process using a 1%-H2 concentration in the ambient gas and a subsequent second ISSG process using a 5%-H2 concentration in the ambient gas, wherein the second ISSG process compensates an in-plane thickness distribution of the film formed by the first ISSG process. The time length for the first and second ISSG steps is determined based on a desired film thickness, a time length dependency of a film formed by the second ISSG process, and the oxidation rate of the first and second ISSG processes.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: June 15, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Takayuki Kanda
  • Patent number: 7723205
    Abstract: There is provided a semiconductor device, in which characteristics of the semiconductor device are improved by thinning a gate insulating film and a leak current can be reduced, and a manufacturing method thereof. An aluminum film which is a metal film is formed over a polycrystalline semiconductor film, and plasma oxidizing treatment is performed to the aluminum film, whereby an aluminum oxide film is formed by oxidizing the aluminum film, and a silicon oxide film is formed between the polycrystalline semiconductor film and the aluminum oxide film.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: May 25, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventor: Tetsuya Kakehata
  • Patent number: 7718548
    Abstract: A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: May 18, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Sang M. Lee, Vladimir Zubkov, Zhenijiang Cui, Meiyee Shek, Li-Qun Xia, Hichem M'Saad
  • Patent number: 7718553
    Abstract: A method for forming an insulation film on a semiconductor substrate by plasma reaction includes: introducing into a reaction chamber a source gas of a silicon-containing hydrocarbon compound comprising in its molecule at least one Si—O bond and at least one bond selected from the group consisting of a Si—Si bond, Si—N bond, and Si—H bond; introducing into the reaction chamber an additive gas constituted by C, H, and optionally O; controlling a susceptor at a temperature of ?50° C. to 50° C.; forming by plasma reaction an insulation film constituted by Si, O, H, and optionally N on an irregular surface of a substrate at a deposition rate of 100 nm/min or less; and heat-treating the substrate with the insulation film, thereby increasing a density of the insulation film to more than 2.1 g/cm3 as a result of the heat treatment.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 18, 2010
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Nobuo Matsuki
  • Patent number: 7718231
    Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kwang Su Choe, Keith E. Fogel, Siegfried L. Maurer, Ryan M. Mitchell, Devendra K. Sadana
  • Publication number: 20100120225
    Abstract: An object is to reduce occurrence of defective bonding between a base substrate and a semiconductor substrate even when a silicon nitride film or the like is used as a bonding layer. Another object is to provide a method for manufacturing an SOI substrate by which an increase in the number of steps can be suppressed.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 13, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuya KAKEHATA, Kazutaka KURIKI
  • Patent number: 7713883
    Abstract: An object of this invention is to make it possible to suppress early-stage oxidation of a substrate surface prior to oxidation processing, and to remove a natural oxidation film. For this reason, a method is provided comprising the steps of loading a substrate into a processing chamber, supplying a hydrogen-containing gas and an oxygen-containing gas into the processing chamber, and subjecting a surface of the substrate to oxidation processing, and unloading the substrate subjected to oxidation processing from the processing chamber. In the oxidation processing step, the hydrogen-containing gas is introduced in advance into the processing chamber, with the pressure inside the processing chamber set at a pressure that is less than atmospheric pressure, and the oxygen-containing gas is then introduced in the state in which the introduction of the hydrogen-containing gas is continued.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: May 11, 2010
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Yuasa, Yasuhiro Megawa
  • Patent number: 7696107
    Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 13, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Toshiharu Yamauchi, Tunenori Yamauchi, Kumiko Toyota
  • Patent number: 7682988
    Abstract: A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Husam N. Alshareef, Rajesh Khamankar, Ajith Varghese, Cathy A. Chancellor, Anand Krishnan, Malcolm J. Bevan
  • Patent number: 7678678
    Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Don Carl Powell
  • Patent number: 7678709
    Abstract: A deposition method modulates the reaction rate and thickness of highly conformal dielectric films deposited by forming a saturated catalytic layer on the surface and then exposing the surface to silicon-containing precursor gas and a reaction modulator, which may accelerate or quench the reaction. The modulator may be added before, after, or during exposure of the silicon-containing precursor gas. The film thickness after one cycle of deposition may be increased up to 20 times or decreased up to 20 times.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: March 16, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Brian Lu, Wai-Fan Yau, Collin Mui, Bunsen Nie, Raihan Tarafdar
  • Patent number: 7674722
    Abstract: In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration in the gate insulation film formed by the plasma nitridation is 5 to 20% in atomic percentage. Even without subsequent annealing, it is possible to effectively prevent a boron penetration phenomenon in the DRAM and to reduce traps in the film causing deterioration in driving capability of the device.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: March 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuo Nishita, Shuuichi Ishizuka, Yutaka Fujino, Toshio Nakanishi, Yoshihiro Sato
  • Patent number: 7670965
    Abstract: A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 2, 2010
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Yoshinobu Nakada, Hiroyuki Shiraki
  • Patent number: 7666800
    Abstract: Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor device includes forming first sidewall spacers on a first hard mask, removing the first hard mask, and forming a first material layer over the first sidewall spacers. A second hard mask is formed over the first material layer and the first sidewall spacers. Second sidewall spacers are formed on the second hard mask, and the second hard mask is removed. At least the first sidewall spacers are patterned using the second sidewall spacers as a mask.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: February 23, 2010
    Assignee: Infineon Technologies AG
    Inventors: Sajan Marokkey, Alois Gutmann, Klaus Herold, Chandrasekhar Sarma
  • Patent number: 7659214
    Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a first wet process gas comprising water vapor into the process chamber, and reacting the substrate with the first wet process gas to grow an oxide film on the substrate. The method further includes flowing a second wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber, and reacting the oxide film and the substrate with the second wet process gas to grow an oxynitride film. In another embodiment, the method further comprises annealing the substrate containing the oxynitride film in an annealing gas. According to one embodiment of the method where the substrate is silicon, a silicon oxynitride film can be formed that exhibits a nitrogen peak concentration of approximately 3 atomic % or greater.
    Type: Grant
    Filed: September 30, 2007
    Date of Patent: February 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Kimberly G. Reid, Anthony Dip
  • Patent number: 7658973
    Abstract: A method of forming a dielectric film that includes nitrogen. The method includes incorporating nitrogen into a dielectric film using a nitridation gas and a rapid thermal annealing process, wherein an ultra-low pressure of equal to or less than about 10 Torr is used for the rapid thermal annealing process.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Pravin K. Narwankar, Gary E. Miner, Arnaud Lepert
  • Patent number: 7651959
    Abstract: A method of forming a dielectric film includes: introducing a source gas essentially constituted by Si, N, H, and optionally C and having at least one bond selected from Si—N, Si—Si, and Si—H into a reaction chamber where a substrate is placed; depositing a silazane-based film essentially constituted by Si, N, H, and optionally C on the substrate by plasma reaction at ?50° C. to 50° C., wherein the film is free of exposure of a solvent constituted essentially by C, H, and optionally O; and heat-treating the silazane-based film on the substrate in a heat-treating chamber while introducing an oxygen-supplying source into the heat-treating chamber to release C from the film and increase Si—O bonds in the film.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: January 26, 2010
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Jeongseok Ha, Nobuo Matsuki
  • Patent number: 7651955
    Abstract: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or other silicon-containing materials. The photoexcitation process may expose the substrate and/or gases to an energy beam or flux prior to, during, or subsequent a deposition process. Therefore, the photoexcitation process may be used to pre-treat or post-treat the substrate or material, to deposit the silicon-containing material, and to enhance chamber cleaning processes.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: January 26, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Joseph M. Ranish, Kaushal K. Singh
  • Patent number: 7648923
    Abstract: A method of fabricating a flash memory device is disclosed. The method comprises forming a first insulating layer on a semiconductor substrate; accumulating nitrogen at an interface between the semiconductor substrate and the first insulating layer to form a second insulating layer at the interface; and implanting oxygen into the second insulating layer to convert the second insulating layer to a third insulating layer.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: January 19, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Shil Park, Kwon Hong, Jae Hong Kim, Jae Hyoung Koo
  • Publication number: 20100003833
    Abstract: A method of forming a fluorine-containing dielectric film on a substrate by plasma CVD, includes: introducing as a process gas a fluorinated carbon compound having at least two double bonds in its molecule and an unsaturated hydrocarbon compound into a reaction space wherein a substrate is placed; and applying RF power to the reaction space to deposit a fluorine-containing dielectric film on the substrate by plasma CVD.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 7, 2010
    Applicant: ASM JAPAN K.K.
    Inventors: Naoto Tsuji, Akinori Nakano
  • Patent number: 7641736
    Abstract: A method of manufacturing an SiC single crystal wafer according to the present invention includes the steps of: (a) preparing an SiC single crystal wafer 10 with a mirror-polished surface; (b) oxidizing the surface of the SiC single crystal wafer 10 with plasma, thereby forming an oxide layer 12 on the surface of the SiC single crystal wafer; and (c) removing at least a portion of the oxide layer 12 by a reactive ion etching process. Preferably, the surface of the wafer is planarized by repeatedly performing the steps (b) and (c) a number of times.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: January 5, 2010
    Assignee: Hitachi Metals, Ltd.
    Inventor: Taisuke Hirooka
  • Patent number: 7638442
    Abstract: A process for forming a silicon nitride layer on a gate oxide film as part of formation of a gate structure in a semiconductor device includes: forming a layer of silicon nitride on top of a gate oxide film on a semiconductor substrate by a nitridation process, heating the semiconductor substrate in an annealing chamber, exposing the semiconductor substrate to N2 in the annealing chamber, and exposing the semiconductor substrate to a mixture of N2 and N2O in the annealing chamber.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: December 29, 2009
    Assignee: ProMOS Technologies, Inc.
    Inventors: Cheng-Ta Wu, Da-Yu Chuang, Yen-Da Chen, Lihan Lin
  • Patent number: 7635655
    Abstract: A method for performing an oxidation process on a plurality of substrates in a batch processing system. According to one embodiment, the method includes selecting a N2O-based oxidation process for the substrates including a first process gas containing N2O that thermally decomposes in a process chamber of the batch processing system to N2, O2, and NO byproducts, and generating a replacement NO-based oxidation process for the substrates including a second process gas containing N2, O2, and NO with molar concentrations that mimic that of the N2, O2, and NO byproducts in the N2O-based oxidation process. According to another embodiment of the invention, the NO-based oxidation process contains NO, O2, and an inert gas.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: December 22, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Anthony Dip