Abstract: A method for protecting a semiconductor film comprised of one or more layers during processing. The method includes placing a surface of the semiconductor film in direct contact with a surface of a protective covering, such as a separate substrate piece, that forms an airtight or hermetic seal with the surface of the semiconductor film, so as to reduce material degradation and evaporation in the semiconductor film. The method includes processing the semiconductor film under some conditions, such as a thermal annealing and/or controlled ambient, which might cause the semiconductor film's evaporation or degradation without the protective covering.

Abstract: The present invention designs a measurement scheme for the longitudinal temperature of the film during nitride epitaxial growth, belongs to the field of semiconductor measurement technology. Epitaxial growth technology is one of the most effective methods for preparing nitride materials. The temperature during the growth process restricts the performance of the device. The non-contact temperature measurement method is generally used to measure the temperature of the graphite disk as the base, which can't obtain the longitudinal temperature.

Abstract: A carrier-type heat-treatment apparatus including a furnace main body that includes heaters and a mesh belt that transports an object to be heat-treated into the furnace main body includes a gas pipe arranged inside the furnace main body, the gas pipe being configured to inject a gas into the furnace main body, in which a low-temperature zone and a high-temperature zone are provided inside the furnace main body with the gas, the low-temperature zone being provided on an entrance side of the furnace main body, the high-temperature zone being provided on an exit side of the furnace main body and having a temperature higher than the low-temperature zone.

Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.

Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

Abstract: Methods of forming photo detectors are provided. The method includes providing a semiconductor layer on a substrate, forming a trench in the semiconductor layer, forming a first single crystalline layer and a second single crystalline layer using a selective single crystalline growth process in the trench, and patterning the first and second single crystalline layers and the semiconductor layer to form a first single crystalline pattern, a second single crystalline pattern and an optical waveguide.

Abstract: Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.

Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.

Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.

Abstract: According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga1?z1Inz1N (0<z1?1). The second semiconductor layer is provided on the light emitting part. The In-containing layer is provided at at least one of first and second positions. The first position is between the first semiconductor layer and the light emitting part. The second position is between the second semiconductor layer and the light emitting part. The In-containing layer includes In with a composition ratio different from the In composition ratio z1 and has a thickness 10 nm to 1000 nm.

Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.

Abstract: A solar cell and method for producing same is disclosed. The solar cell includes a multijunction solar cell structure and a notch filter designed to reflect solar energy that does not contribute to the current output of the multijunction solar cell. By reflecting unused solar energy, the notch filter allows the solar cell to run cooler (and thus more efficiently) yet it still allows all junctions to fully realize their electrical current production capability.

Abstract: A backside illuminated multi junction solar cell module includes a substrate, multiple multi junction solar cells, and a cell interconnection that provides a series connection between at least two of the multi junction solar cells. The substrate may include a material that is substantially transparent to solar radiation. Each multi junction solar cell includes a first active cell, grown over the substrate, for absorbing a first portion of the solar radiation for conversion into electrical energy and a second active cell, grown over the first active cell, for absorbing a second portion of the solar radiation for conversion into electrical energy. At least one of the first and second active cells includes a nitride.

Abstract: In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed.

Abstract: Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.

Abstract: The disclosure relates to a making a matrix of III-V nitride, the matrix including at least an active first portion through which an electrical current passes and at least a passive second portion through which no electrical current passes, the matrix including at least a first zone forming a first quantum confinement region made of a III-V nitride, the first zone being positioned in the active first portion, and at least a second zone forming a second quantum confinement region made of III-V nitride, such that the second zone is positioned to the passive portion of the matrix.

Abstract: The present invention relates to a process for producing a doped silicon layer on a substrate, comprising the steps of (a) providing a liquid silane formulation and a substrate, (b) applying the liquid silane formulation to the substrate, (c) introducing electromagnetic and/or thermal energy to obtain an at least partly polymorphic silicon layer, (d) providing a liquid formulation which comprises at least one aluminum-containing metal complex, (e) applying this formulation to the silicon layer obtained after step (c) and then (f) heating the coating obtained after step (e) by introducing electromagnetic and/or thermal energy, which decomposes the formulation obtained after step (d) at least to metal and hydrogen, and then (g) cooling the coating obtained after step (f) to obtain an Al-doped or Al- and metal-doped silicon layer, to doped silicon layers obtainable by the process and to the use thereof for production of light-sensitive elements and electronic components.

Abstract: Nanostructures and photovoltaic structures are disclosed. A nanostructure according to one embodiment includes an array of nanocables extending from a substrate, the nanocables in the array being characterized as having a spacing and surface texture defined by inner surfaces of voids of a template; an electrically insulating layer extending along the substrate; and at least one layer overlaying the nanocables. A nanostructure according to another embodiment includes a substrate; a portion of a template extending along the substrate, the template being electrically insulative; an array of nanocables extending from the template, portions of the nanocables protruding from the template being characterized as having a spacing, shape and surface texture defined by previously-present inner surfaces of voids of the template; and at least one layer overlaying the nanocables.

Abstract: Provided is a method for manufacturing an organic thin film solar cell module that can be manufactured by simple steps. As the method for manufacturing an organic thin film solar cell module, the method for manufacturing an organic thin film solar cell module in which a plurality of organic photovoltaic cells (100A1) and (100A2) comprising a pair of electrodes comprising a first electrode (20) and a second electrode (70) and an active layer (50) that is placed between the pair of electrodes are arranged on a substrate (10), the method comprises: forming the first electrodes on the substrate; and forming a lyophobic pattern (30a) on a part of each of the first electrodes.

Abstract: An image sensor includes a semiconductor layer that filters light of different wavelengths. For example, the semiconductor layer absorbs photons of shorter wavelengths and passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed near a front side of the semiconductor layer. A dopant layer is formed below the photodiode near a back side of the semiconductor layer. A mirror that primarily reflects photons of longer visible wavelengths is disposed on the back side of the semiconductor layer.

Abstract: The present invention relates to a photovoltaic cell, a method of manufacturing such photovoltaic cell, and to uses of such cell.

Abstract: A method of manufacturing a light generating device with required wavelength is disclosed. According to the method, a) a required wavelength is determined. b) A polar angle and an azimuthal angle corresponding to the required wavelength in a nitride semiconductor are determined. Then, c) a nitride semiconductor crystal is grown according to the polar angle and the azimuthal angle. Therefore, a light generating device with required wavelength may be manufactured without adjusting amounts of elements of compound semiconductor.

Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: A semiconductor photodetector device (PD1) comprises a multilayer structure (LS1) and a glass substrate (1) optically transparent to incident light. The multilayer structure includes an etching stop layer (2), an n-type high-concentration carrier layer (3), an n-type light-absorbing layer (5), and an n-type cap layer (7) which are laminated. A photodetecting region (9) is formed near a first main face (101) of the multilayer structure, whereas a first electrode (21) is provided on the first main face. A second electrode (27) and a third electrode (31) are provided on a second main face (102). A film (10) covering the photodetecting region and first electrode is formed on the first main face. A glass substrate (1) is secured to the front face (10a) of this film.

Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.

Abstract: According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a portion of the gate insulating film where is not located under the semiconductor layer is removed during manufacturing steps of the present invention.

Abstract: A photovoltaic nanostructure according to one embodiment of the present invention includes an electrically conductive nanocable coupled to a first electrode, a second electrode extending along at least two sides of the nanocable, and a photovoltaically active p-n junction formed between the nanocable and the second electrode. A photovoltaic array according to one embodiment includes a plurality of photovoltaic nanostructures as recited above. Methods for forming nanostructures are also presented.

Abstract: A backside illuminated multi-junction solar cell module includes a substrate, multiple multi-junction solar cells, and a cell interconnection that provides a series connection between at least two of the multi-junction solar cells. The substrate may include a material that is substantially transparent to solar radiation. Each multi-junction solar cell includes a first active cell, grown over the substrate, for absorbing a first portion of the solar radiation for conversion into electrical energy and a second active cell, grown over the first active cell, for absorbing a second portion of the solar radiation for conversion into electrical energy. At least one of the first and second active cells includes a nitride.

Abstract: A nitride semiconductor laser element includes a substrate and a nitride semiconductor layer in which a first semiconductor layer, an active layer, and a second semiconductor layer are laminated in this order on the substrate. At least one of the first semiconductor layer and the second semiconductor layer includes a first section forming recessed and raised portions and a second section embedding the recessed and raised portions of the first section. A region with a higher aluminum mixed crystal ratio than the second section that embeds the recessed and raised portions is disposed on top faces of the raised portions. The nitride semiconductor layer defines resonant planes, and the recessed and raised portions are formed in a shape of stripes that extend substantially parallel to the resonant planes.

Abstract: There is provided a method for manufacturing a nitride semiconductor device which has a p-type nitride semiconductor layer having a high carrier concentration (low resistance) by activating an acceptor without raising a problem of forming nitrogen vacancies which are generated when a high temperature annealing is carried out over an extended time. A semiconductor lamination portion (6) made of nitride semiconductor is formed on a substrate (1) so as to form a light emitting layer, and irradiated by a laser beam having a wavelength ? of ?=h·c/E or less (E is energy capable of separating off the bonding between Mg and H) from the front surface side of the semiconductor lamination portion. Then, a heat treatment is carried out at a temperature of 300 to 400° C.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: InSb infrared photodiodes and sensor arrays with improved passivation layers and methods for making same are disclosed. In the method, a passivation layer of AlInSb is deposited on an n-type InSb substrate using molecular beam epitaxy before photodiode detector regions are formed in the n-type substrate. Then, a suitable P+ dopant is implanted directly through the AlInSb passivation layer to form photodiode detector regions. Next, the AlInSb passivation layer is selectively removed, exposing first regions of the InSb substrate, and gate contacts are formed in the first regions of the InSb substrate. Then, additional portions of the AlInSb passivation layer are selectively removed above the photodiode detectors exposing second regions. Next, metal contacts are formed in the second regions, and bump contacts are formed atop the metal contacts. Then, an antireflection coating is applied to a side of the substrate opposite from the side having the metal and bump contacts.

Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.

Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

Abstract: Methods and systems are provided of fabricating a compound nitride semiconductor structure. A substrate is disposed within a processing chamber into which a group-III precursor and a nitrogen precursor are flowed. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process using the precursors. The substrate is transferred to a transfer chamber where a temperature and a curvature of the layer are measured. The substrate is then transferred to a second processing chamber where a second layer is deposited.

Abstract: A semiconductor device includes an active layer, an n-side contact layer, and a p-side contact layer. The nitride semiconductor device includes at least a first n-side layer, a second n-side layer, a third n-side layer and a fourth n-side layer formed in this order from the n-side contact layer between the n-side contact layer and the active layer, while at least the second n-side layer and the fourth n-side layer each contain an n-type impurity, and the concentration of the n-type impurity in at least the second n-side layer and the fourth n-side layer is higher than the concentration of the n-type impurity in the first n-side layer and the third n-side layer.

Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all

Abstract: The optical modulator may include a strained layer of SiGe to confine carriers in a quantum well. The strained layer of SiGe may be doped with arsenic to provide electrons. The optical modulator may receive an optical signal and modulate the received signal by altering the absorption coefficient of the strained layer of SiGe responsive to an electrical signal. The optical modulator device device may be suitable for use in chip-to-chip and on-chip interconnections.

Abstract: A high temperature non-aqueous synthetic procedure for the preparation of substantially monodisperse IV-VI semiconductor nanoparticles is provided. The procedure includes introducing a first precursor selected from the group consisting of a molecular precursor of a Group IV element and a molecular precursor of a Group VI element into a reaction vessel that comprises at least an organic solvent to form a mixture. Next, the mixture is heated and thereafter a second precursor of a molecular precursor of a Group IV element or a molecular precursor of a Group VI element that is different from the first is added. The reaction mixture is then mixed to initiate nucleation of IV-VI nanocrystals and the temperature of the reaction mixture is controlled to provide nanoparticles having a diameter of about 20 nm or less.

Abstract: An apparatus is directed to increasing the resolution of digital color imaging that includes a photosensing semiconductor structure. The apparatus provides a monocrystalline silicon substrate, a first buffer layer epitaxially formed and overlying the monocrystalline silicon substrate, and a first photodiode layer overlying the first buffer layer and operable to provide a first signal indicative of a color associated with a first wavelength of light. The apparatus may further provide a second buffer layer overlying the first photodiode layer and a second photodiode layer overlying the second buffer layer operable to provide a second signal indicative of a color associated with a second wavelength of light.

Abstract: There is provided a semiconductor laser device having on a single substrate a plurality of laser portions each oscillating laser light of a different wavelength, the plurality of laser portions containing different types, respectively, of dopant. There is also provided a method of fabricating a semiconductor laser device, forming on a single substrate a plurality of laser portions each oscillating laser light of a different wavelength, initially forming a laser portion in a crystal growth method and subsequently forming another laser portion in a different crystal growth method.

Abstract: A quantum well infrared photodetector (QWIP) that provides two-color image sensing. Two different quantum wells are configured to absorb two different wavelengths. The QWIPs are arrayed in a focal plane array (FPA). The two-color QWIPs are selected for readout by selective electrical contact with the two different QWIPs or by the use of two different wavelength sensitive gratings.

Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.

Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.

Abstract: Disclosed is a photodiode with improved light-receiving efficiency and coupling effect with an optical fiber, whose capacitance may be decreased. The inventive photodiode includes a substrate; a buffer layer and a light-absorbing layer laminated in sequence on the substrate; an epitaxial layer formed on the upper surface of the light absorbing layer and having an active region with a surface in a convex lens shape so that it has greater surface area and more effective light-receiving area than an active region defined in a two-dimensional plane, the active region further having a convex surface can harvest light with its convex-lens characteristics; a dielectric layer formed on the upper surface of the epitaxial layer; a first metal electrode formed on an upper surface of the dielectric layer; and, a second metal electrode formed on an under surface of the substrate.