Compound Semiconductor Patents (Class 438/77)
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Patent number: 6734452Abstract: An AlxGa1−xAs/GaAs/AlxGa1−xAs quantum well exhibiting a bound-to-quasibound intersubband absorptive transition is described. The bound-to-quasibound transition exists when the first excited state has the same energy as the “top” (i.e., the upper-most energy barrier) of the quantum well. The energy barrier for thermionic emission is thus equal to the energy required for intersubband absorption. Increasing the energy barrier in this way reduces dark current. The amount of photocurrent generated by the quantum well is maintained at a high level.Type: GrantFiled: April 3, 2001Date of Patent: May 11, 2004Assignee: California Institute of TechnologyInventors: Sarath Gunapala, John K. Liu, Jin S. Park, True-Lon Lin, Mani Sundaram
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Publication number: 20040087055Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions.Type: ApplicationFiled: October 27, 2003Publication date: May 6, 2004Applicant: NSC-Nanosemiconductor GmbHInventor: Nikolai Ledentsov
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Patent number: 6724059Abstract: The present invention provides a thin magnetoelectric transducer which has a projected size substantially equal to that of a pellet and which can be subjected to an inspection test nondestructively. The magnetoelectric transducer has a semiconductor device provided on the upper surface of a projecting portion of a projecting nonmagnetic insulating substrate 9 and comprising a magnetosensitive section 3 and inner electrodes 2 made of metal. A conductive resin layer 4 is formed on the internal electrodes 2 and on part of the side surfaces of the projecting portion. A strain buffering layer 5 is formed at least on the magnetosensitive section 3. Furthermore, at least the strain buffering layer 5 on the magnetosensitive section 3 is coated with a protective layer 6.Type: GrantFiled: December 6, 2001Date of Patent: April 20, 2004Assignee: Asahi Kasei Electronics Co., Ltd.Inventor: Toshiaki Fukunaka
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Patent number: 6709903Abstract: A method to obtain thin (<300 nm) strain-relaxed Si1−xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. <106 cm−2. The approach begins with the growth of a pseudomorphic Si1−xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1−xGex interface, parallel to the Si(001) surface.Type: GrantFiled: April 30, 2003Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Silke H. Christiansen, Jack O. Chu, Alfred Grill, Patricia M. Mooney
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Patent number: 6653166Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions.Type: GrantFiled: May 9, 2001Date of Patent: November 25, 2003Assignee: NSC-Nanosemiconductor GmbHInventor: Nikolai Ledentsov
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Patent number: 6653701Abstract: A semiconductor device having laminated successively a porous semiconductor layer, an inorganic semiconductor layer, and optionally an organic substance layer formed therebetween is disclosed. The semiconductor device is produced by immersing a porous semiconductor layer or a semiconductor layer having an organic substance layer on the surface thereof in a solution containing the elements constituting an inorganic semiconductor or compounds of the elements and forming the inorganic semiconductor layer on the porous semiconductor layer or the organic substance layer in the solution.Type: GrantFiled: March 7, 2000Date of Patent: November 25, 2003Assignee: Fuji Xerox Co., Ltd.Inventors: Yoshihisa Yamazaki, Yoshiyuki Ono, Hokuto Takada, Katsuhiro Sato, Akira Imai, Hidekazu Hirose
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Publication number: 20030203531Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.Type: ApplicationFiled: June 6, 2003Publication date: October 30, 2003Inventors: Vitaly Shchukin, Nikolai Ledentsov
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Patent number: 6635505Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.Type: GrantFiled: November 18, 2002Date of Patent: October 21, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yukio Tanaka, Shou Nagao
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Article comprising an oxide layer on a GaAs-based semiconductor structure and method of forming same
Publication number: 20030137018Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide.Type: ApplicationFiled: January 18, 2002Publication date: July 24, 2003Inventors: Matthias Passlack, Nicholas William Medendorp -
Patent number: 6566161Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.Type: GrantFiled: November 20, 2000Date of Patent: May 20, 2003Assignee: Honeywell International Inc.Inventors: Harry Rosenberg, Bahri Ozturk, Guangxin Wang, Wesley LaRue
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Patent number: 6559058Abstract: One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over the substrate and the second layer. Finally, an etching operation using a selective etchant is used to remove the second layer, thereby leaving the substrate, which forms a first active layer, and leaving the third layer, which forms a second active layer.Type: GrantFiled: January 31, 2002Date of Patent: May 6, 2003Assignee: The Regents of the University of CaliforniaInventors: Jeffrey J. Peterson, Charles E. Hunt
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Publication number: 20030020144Abstract: Integrated communications apparatus and methods are used to receive, transmit, and operate on communications signals. A composite semiconductor structure may be formed for providing an integrated communications device that may include transceiver circuitry, data converter circuitry, and processor circuitry. The data converter circuitry may include an analog-to-digital and/or digital-to-analog data converter that is implemented at least partly using compound semiconductors (e.g., using compound semiconductor transistors for implementing comparators and/or switches in the data converter). The processor circuitry may include some circuitry that is formed from non-compound semiconductors, which is better suited than compound semiconductors to perform digital signal processing operations. The transceiver circuitry may include compound and/or non-compound semiconductor circuitry depending on the signal frequency and whether the signal is optical or electrical.Type: ApplicationFiled: July 24, 2001Publication date: January 30, 2003Applicant: MOTOROLA, INC.Inventors: Keith Warble, Steven F. Gillig, Barry W. Herold
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Patent number: 6492193Abstract: An optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rather than elsewhere in the buffer structure.Type: GrantFiled: November 22, 2000Date of Patent: December 10, 2002Assignee: Cree, Inc.Inventors: John Adam Edmond, Hua-Shuang Kong, Kathleen Marie Doverspike, Michelle Turner Leonard
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Publication number: 20020132388Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.Type: ApplicationFiled: January 15, 2002Publication date: September 19, 2002Inventors: Harry Rosenberg, Bahri Ozturk, Guangxin Wang, Wesley LaRue
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Patent number: 6431455Abstract: A data carrier for noncontacting control of persons with nontransferable entitlement to utilize a service is integrated into a bracelet (1) so as to be useless after the bracelet (1) is opened.Type: GrantFiled: September 27, 2000Date of Patent: August 13, 2002Assignee: SkiData AGInventor: Gregor Ponert
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Patent number: 6380005Abstract: In a charge transfer device of the two-layer electrode, two-phase drive type, an N−− semiconductor region 108 and a first insulator film 103 are formed on a P-type semiconductor substrate 101 in the named order. Then, first transfer electrodes 104A are formed on the first insulator film 103, and a second insulator film 105 is formed on the surface of the N−− semiconductor region 108 and a third insulator film 105 is formed on a top surface and a side surface of each first transfer electrode 104A. Phosphorus is ion-implanted with an incident angle of 0 degree, so that an N-type semiconductor region 102A is formed in N−− semiconductor region 108 between the first transfer electrodes 104A in self-alignment. Second transfer electrodes 109A are formed, and an interlayer insulator 110 is formed on the whole, and metal interconnections 111-1A and 111-2A are formed.Type: GrantFiled: April 7, 2000Date of Patent: April 30, 2002Assignee: NEC CorporationInventor: Yasutaka Nakashiba
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Patent number: 6380601Abstract: A multilayer semiconductor structure includes a germanium substrate having a first surface. The germanium substrate has two regions, a bulk p-type germanium region, and a phosphorus-doped n-type germanium region adjacent to the first surface. A layer of a phosphide material overlies and contacts the first surface of the germanium substrate. A layer of gallium arsenide overlies and contacts the layer of the phosphide material, and electrical contacts may be added to form a solar cell. Additional photovoltaic junctions may be added to form multijunction solar cells. The solar cells may be assembled together to form solar panels.Type: GrantFiled: March 29, 1999Date of Patent: April 30, 2002Assignee: Hughes Electronics CorporationInventors: James H. Ermer, Li Cai, Moran Haddad, Bruce T. Cavicchi, Nasser H. Karam
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Patent number: 6355511Abstract: A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rough surface of the substrate. Then, a thin insulating layer, for example SiO2, is formed over the exposed surface of the substrate, this insulating layer being irregular because of its formation over the relatively rough etched surface. Contact material is provided in the trench, and electrical potential is applied across the contact and substrate sufficient to increase the conductivity of the insulating layer, i.e., to break down the insulating layer. Nitrogen may be implanted into the exposed surface of the substrate to slow subsequent growth of the insulating layer, resulting in an even thinner insulating layer, i.e., one even less resistant to breakdown upon application of electrical potential thereacross.Type: GrantFiled: June 16, 2000Date of Patent: March 12, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Todd P. Lukanc, Kurt O. Taylor
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Publication number: 20010053618Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.Type: ApplicationFiled: June 15, 2001Publication date: December 20, 2001Inventors: Tokuya Kozaki, Hiroyuki Kiyoku, Kazuyuki Chocho, Hitoshi Maegawa
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Patent number: 6323055Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.Type: GrantFiled: May 21, 1999Date of Patent: November 27, 2001Assignee: The Alta Group, Inc.Inventors: Harry Rosenberg, Bahri Ozturk, Guangxin Wang, Wesley LaRue
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Publication number: 20010018227Abstract: A semiconductor device includes an electrically conductive III-V doped semiconductor substrate of a first conduction type, a photodiode array having photodiode structures disposed on the III-V doped semiconductor substrate, a first III-V doped semiconductor layer of a second conduction type disposed between the photodiode structures and the III-V doped semiconductor substrate, etching trenches disposed on the III-V doped semiconductor substrate, each of the trenches having inner sides, the inner sides having an insulation layer and a metallization layer for electrically connecting the photodiode structures in series, the metallization layer disposed on the insulation layer; and partition lines separating each of the photodiode structures from others of the photodiode structures for producing an individual photodiode structure when the array is cut through the first III-V doped semiconductor layer along the partition lines.Type: ApplicationFiled: April 10, 2001Publication date: August 30, 2001Applicant: Siemens AktiengesellschaftInventor: Alfred Lell
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Patent number: 6239354Abstract: A monolithically interconnected photovoltaic module having cells which are electrically connected which comprises a substrate, a plurality of cells formed over the substrate, each cell including a primary absorber layer having a light receiving surface and a p-region, formed with a p-type dopant, and an n-region formed with an n-type dopant adjacent the p-region to form a single pn-junction, and a cell isolation diode layer having a p-region, formed with a p-type dopant, and an n-region formed with an n-type dopant adjacent the p-region to form a single pn-junction, the diode layer intervening the substrate and the absorber layer wherein the absorber and diode interfacial regions of a same conductivity type orientation, the diode layer having a reverse-breakdown voltage sufficient to prevent inter-cell shunting, and each cell electrically isolated from adjacent cells with a vertical trench trough the pn-junction of the diode layer, interconnects disposed in the trenches contacting the absorber regions of adjaType: GrantFiled: October 8, 1999Date of Patent: May 29, 2001Assignee: Midwest Research InstituteInventor: Mark W. Wanlass
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Patent number: 6211529Abstract: An AlxGa1−xAs/GaAs/AlxGa1−xAs quantum well exhibiting a bound-to-quasibound intersubband absorptive transition is described. The bound-to-quasibound transition exists when the first excited state has the same energy as the “top” (i.e., the upper-most energy barrier) of the quantum well. The energy barrier for thermionic emission is thus equal to the energy required for intersubband absorption. Increasing the energy barrier in this way reduces dark current. The amount of photocurrent generated by the quantum well is maintained at a high level.Type: GrantFiled: January 17, 1997Date of Patent: April 3, 2001Assignee: California Institute of TechnologyInventors: Sarath Gunapala, John K. Liu, Jin S. Park, True-Lon Lin, Mani Sundaram
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Patent number: 5906708Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.Type: GrantFiled: December 6, 1995Date of Patent: May 25, 1999Assignee: Lawrence Semiconductor Research Laboratory, Inc.Inventors: McDonald Robinson, Richard C. Westhoff, Charles E. Hunt, Li Ling
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Patent number: 5877520Abstract: The lateral overflow drain for charge coupled devices includes: a semiconductor region 70 of a first conductivity type having a trench 92; a drain region 24 of a second conductivity type below the trench 92; a gate 20 in the trench 92 overlying and separated from a portion of the semiconductor region 70; and a virtual gate 30 of the first conductivity type in the semiconductor region 70 adjacent the trench 92.Type: GrantFiled: August 21, 1997Date of Patent: March 2, 1999Assignee: Texas Instruments IncorporatedInventor: Jaroslav Hynecek
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Patent number: 5753050Abstract: A thermophotovoltaic device and a method for making the thermophotovoltaic device. The device includes an n-type semiconductor material substrate having top and bottom surfaces, a tunnel junction formed on the top surface of the substrate, a region of active layers formed on top of the tunnel junction and a back surface reflector (BSR). The tunnel junction includes a layer of heavily doped n-type semiconductor material that is formed on the top surface of the substrate and a layer of heavily doped p-type semiconductor material formed on the n-type layer. An optional pseudomorphic layer can be formed between the n-type and p-type layers. A region of active layers is formed on top of the tunnel junction. This region includes a base layer of p-type semiconductor material and an emitter layer of n-type semiconductor material. An optional front surface window layer can be formed on top of the emitter layer.Type: GrantFiled: August 29, 1996Date of Patent: May 19, 1998Assignee: The United States of America as represented by the Department of EnergyInventors: Greg W. Charache, Paul F. Baldasaro, James L. Egley