Abstract: In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

Abstract: In a method of fabricating a SiC semiconductor device, a surface of a SiC layer (5, 48, 102) is processed into a cleaned surface terminated at Si. An oxide film (7, 49, 105) is formed on the cleaned surface of the SiC layer. The SiC layer with the oxide film is subjected to thermal oxidation at a temperature in a range of 700° C. to 900° C. so that only terminal Si at the cleaned surface of the SiC layer is oxidated and an interface between the oxide film and the SiC layer becomes an SiO2/SiC cleaned interface.

Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).

Abstract: Porous dielectric films useful in the semiconductor industry are prepared by depositing a Si—O—C film using precursors that contain carbon and oxygen, then heating the Si—O—C to decompose organic fragments trapped within.

Abstract: A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.

Abstract: There is provided a process for preparing a composite material of an oxide crystal film and a substrate by forming a Y123 type oxide crystal film from a solution phase on a substrate using a liquid phase method, wherein problems such as cracking of the oxide crystal film, separation of the oxide crystal film from the substrate, and development of a reaction layer between the substrate and the solution can be minimized. The solvent for forming the solution phase uses either a BaO—CuO—BaF2 system or a BaO—CuO—Ag—BaF2 system, and when the substrate with a seed crystal film bonded to the surface is brought in contact with the solution to form (grow) the oxide crystal film on the substrate, the temperature of the solution is controlled to a temperature of no more than 850° C.

Abstract: In order to vaporize an organic monomer at a high temperature and a high saturated vapor pressure in good efficiency and to grow an organic polymer film at a high rate in high vacuum by a plasma polymerization reaction of the resulting organic monomer gas, a liquid divinylsiloxanebisbenzocyclobutene (DVS-BCB) monomer is mixed with a carrier gas, and the mixture is then sprayed on a vaporization vacuum chamber held at a high temperature to form an aerosol made of liquid fine particles of the organic monomer, and a BCB monomer (organic monomer) is instantaneously vaporized via the aerosol to generate a BCB monomer gas (organic monomer gas). Consequently, the aerosol having a large specific surface area has a large vaporization area, and vaporization occurs by heating at a high temperature before a polymerization reaction occurs. Thus, 0.1 g/min or more of the BCB monomer gas can be formed at 200° C.

Abstract: A method with which all semiconductor lasers can be used as products is provided by regulating reflectance variations of all the semiconductor laser end faces arranged in an electron beam deposition apparatus after completion of deposition to a predetermined range when semiconductor laser end faces are coated. An end face (3) that is placed at a position at which the film thickness is made relatively thicker than those of other coat batches due to the large flux of a deposition beam is inclined by an angle &bgr; to adjust the incident angle of the deposition beam. The relationship, actual film thickness (9b)=film thickness (9b) in direction of deposition beams central axis (8a)×cos &bgr;, is utilized to reduce the film thickness of the end face (3) to the predetermined range.

Abstract: Methods of forming a spin-on-glass (SOG) layer are disclosed. An SOG layer is formed on an integrated circuit substrate. A first curing process is performed on the SOG layer. Less than all of the SOG layer is removed from the integrated circuit substrate through a mask pattern on the SOG layer to provide a remaining portion of the SOG layer on the integrated circuit substrate. A second curing process is performed on the SOG layer. The remaining portion of the SOG layer is removed to expose the integrated circuit substrate.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising a III-V semiconductor substrate, and an insulating layer deposited on the substrate by Atomic Layer Deposition (ALD). The use of ALD to deposit the insulating layer was found to facilitate the creation of active devices that avoid Fermi layer pinning. In addition, such insulating layer may be advantageously used as a passivation layer in III-V substrate based active devices and transistors.

Abstract: Polarization modulator devices can be formed to take advantage of multi-layered semiconductor structures. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: A semiconductor laser of present invention is constructed by an aluminium oxide (Al2O3) film on an end surface opposed to a beam emission surface of the semiconductor laser, a silicon nitride (SiNx, or Si3N4) film on the aluminium oxide film, and a silicon oxide (SiO2) film on the silicon nitride film. These films are made successively by a method of Electron Cyclotron Resonance (ECR) sputtering.

Abstract: A method passivates a surface of a semiconductor structure. The method provides III-V semiconductor material having a surface to be passivated. Upon the surface of the III-V semiconductor material to be passivated an oxide layer is formed. Thereafter, the surface of the III-V semiconductor material having the oxide layer is passivated, without desorption of the oxide layer and in a vacuum of 2×10−6 Torr, with a material having the ability to intermix with the oxide layer so as to exchange oxygen, passivation layer material, and III-V semiconductor material therebetween to form graded layers of oxidized III-V and passivation material.

Abstract: In one aspect, a method of forming an electronic device includes forming a layer of undoped oxide over a layer of doped oxide. A first electrode is formed proximate thereto. With the undoped oxide layer being outwardly exposed, a silicon nitride layer is formed on the undoped oxide layer and over the first electrode by low pressure chemical vapor deposition to a thickness of no greater than 80 Angstroms. The substrate is exposed to oxidizing conditions of at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride on the undoped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed, over the silicon dioxide layer and the first electrode. Other aspects are contemplated.

Abstract: A method for utilizing a rough insulator to enhance metal-insulator-semiconductor reliability is provided. The method includes steps of: (a) providing a semiconductor substrate; (b) prebaking the semiconductor substrate under a relatively high vacuum to form a rough surface on the semiconductor substrate; and (c) growing an insulator on the semiconductor substrate to form a rough insulator and increase the metal-insulator-semiconductor reliability when the insulator is applied.

Abstract: The invention includes providing gallium nitride material devices having backside vias and methods to form the devices. The devices include a gallium nitride material formed over a substrate, such as silicon. The device also may include one or more non-conducting layers between the substrate and the gallium nitride material which can aid in the deposition of the gallium nitride material. A via is provided which extends from the backside of the device through the non-conducting layer(s) to enable electrical conduction between an electrical contact deposited within the via and, for example, an electrical contact on the topside of the device. Thus, devices of the invention may be vertically conducting. Exemplary devices include laser diodes (LDs), light emitting diodes (LEDs), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varactor diodes, among others.

Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.

Abstract: A method for providing a dielectric film having a low dielectric constant. The deposited film is particularly useful as an intermetal or premetal dielectric layer in an integrated circuit. The low dielectric constant film is a carbon-doped silicon oxide layer deposited from a thermal, as opposed to plasma, CVD process. The layer is deposited from a process gas of ozone and an organosilane precursor having at least one silicon-carbon (Si—C) bond. During the deposition process the wafer is heated to a temperature less than 250° C. and preferably to a temperature between 100-200° C. Enhancements to the process include adding Boron and/or Phosphorus dopants, two step deposition, and capping the post cured layer.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer has lattice registry to both the underlying silicon wafer and the overlying monocrystalline material layer. Formation of a compliant substrate preferably includes utilizing enhanced epitaxy of a surfactant template layer. The surfactant template layer may be formed by depositing an organometallic compound on the accommodating buffer layer using atomic layer epitaxy. In certain preferred embodiments, the organometallic compound is an aluminum-containing compound.

Abstract: One aspect of the present invention relates to a method of forming a low k material layer on a semiconductor substrate, involving the steps of depositing a mixture containing a low k material and a casting solvent on the semiconductor substrate; optionally contacting the mixture with a transition solvent whereby the casting solvent is removed from the mixture to form a second mixture containing the low k material and the transition solvent; contacting the second mixture with a supercritical fluid whereby the transition solvent is removed from the second mixture; and permitting the supercritical fluid to evaporate thereby forming the low k material layer.

Abstract: A substrate is first provided, and a first oxide layer is formed on the surface of the substrate. A rapid thermal nitrifying (RTN) process anneals the first oxide layer and simultaneously nitrifies the surface of the first oxide layer. Then, a low-pressure chemical vapor deposition (LPCVD) process forms a nitride layer on the surface of the first oxide layer. Finally, a second oxide layer is formed on the surface of the nitride layer. The second oxide layer, the nitride layer and the first oxide layer together construct the ONO layer.

Abstract: Gap-fill and damascene methods are disclosed for depositing an insulating thin film of nitrofluorinated silicate glass on a substrate in a process chamber. A high-density plasma, generated from a gaseous mixture of silicon-, fluorine-, oxygen-, and nitrogen-containing gases, deposits a layer of nitrofluorinated silicate glass onto the substrate. For gap-fill applications, the substrate is biased with a bias power density between 4.8 and 11.2 W/cm2 and the ratio of flow rate for the oxygen-containing gas to the combined flow rate for all silicon-containing gases in the process chamber is between 1.0 and 1.8, preferably between 1.2 and 1.4. For damascene applications, the bias power density is less than 3.2 W/cm2, preferably 1.6 W/cm2, and the flow rate ratio is between 1.2 and 3.0. Using optimized parameters, the thin film has a lower dielectric constant and better adhesion properties than fluorosilicate glass.

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract: A system for coating the surface of compound semiconductor wafers includes providing a single-wafer epitaxial production system in a cluster-tool architecture with a loading, storage, and transfer modules, a III-V deposition chamber, and an insulator deposition chamber. The compound semiconductor wafer is placed in the loading and transfer module and the pressure is reduced to less than 5×10−10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The single wafer is then moved through the transfer module to the insulator chamber and an insulating cap layer is formed by thermally evaporating molecules, consisting essentially of gallium and oxygen, from an effusion cell using a thermal evaporation source that utilizes a metallic iridium crucible that is manufactured using the electroforming process.

Abstract: Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.

Abstract: A method for forming a film includes forming the film on a substrate, followed by performing a first annealing of the film at a temperature lower than a crystallization temperature of the film. A second annealing of the film is performed at a temperature higher that the crystallization temperature. Forming the film and the first annealing of the film are performed in situ in a chamber. Alternatively, the first and second annealing are performed in situ in an apparatus.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition at a pressure of at least 1 Torr, a temperature of less than 700° C. and using feed gases comprising a silicon hydride and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In another implementation, a layer comprising undoped oxide is formed over a doped oxide layer.

Abstract: In a method of manufacturing an aluminum oxide film using atomic layer deposition, alcohol is delivered as an oxygen source instead of water vapor into a reactor via a different delivery line from an aluminum source. Thus, the disclosed method can prevent degradation of an aluminum oxide thin film in uniform fashion by a chemical vapor deposition method that is parasitically generated. Also, an activation gas is delivered into the reactor at about the same time an aluminum source and an alcoholic gas is delivered. Therefore, the disclosed method can prevent reduction in the deposition rate and also prohibit degradation in an electrical property by impurity.

Abstract: Low k dielectrics such as black diamond have a tendency to delaminate from the edges of a silicon wafer, causing multiple problems, including blinding of the alignment mark. This problem has been overcome by inserting a layer of silicon nitride between the low k layer and the substrate. A key requirement is that said layer of silicon nitride be under substantial compressive stress (at least 5×109dynes/cm2). In the case of a layer of black diamond, on which material the invention is particularly focused, a nucleating layer is also inserted between the silicon nitride and the black diamond. A process for laying down the required layers is described together with an example of applying the invention to a dual damascene structure.

Abstract: A method of fabricating a MOSEFT device, which is suitable for fabricating an III-V group semiconductor device. A substrate comprises a buffer layer and a channel layer, wherein silicon oxide is formed on the channel layer by a liquid phase deposition method (LPD) to control the parameters of growth solution. A silicon oxide insulating layer that is formed on the channel layer has a thickness of approximately 40 Å, wherein the silicon oxide insulating layer is used as a gate oxide layer. A source, a drain and a gate are formed on the gate oxide layer. The LPD process is performed in a temperature range from room temperature to 60° C. Thus, the low temperature of the LPD technique will not lead to a negative heat effect on other fabrications or on the wafer, therefore the low temperature will not cause thermal stress, dopant redistribution, dopant diffusion or material interaction, for example.

Abstract: Methods are provided for producing a compound semiconductor substrate including: a mica substrate; and a III-V group compound semiconductor layer containing nitrogen as its main component grown on the mica substrate.

Abstract: A device includes an electrical circuit carried by a carrier element, an electrically conductive structure being provided on a surface of the carrier element. In accordance with the invention the one or more components of the electrical circuit are arranged on the side of the electrically conductive structure facing the carrier element.

Abstract: A method for manufacturing a SiC device embraces (a) depositing a polysilicon film above a SiC substrate; (b) delineating the polysilicon film into required pattern; and (c) annealing the SiC substrate in a water rich ambient to selectively grow a thick localized thermal oxide film above the SiC substrate. At the surface of SiC substrate, source/drain regions and substrate contact region are formed. In the water rich ambient, the H2O partial pressure is so maintained that it is more than 0.95.

Abstract: A process and a package for achieving wafer scale packaging is described. A layer of silicone elastomer is deposited on the surface of a chip. Via holes through this layer connect to the top surfaces of the studs that pass through the passivating layer of the chip. In one version, the elastomer layer covers a redistribution network on a previously planarized surface of the chip. Individual chip-level networks are then connected together in the kerf so that conductive posts may be formed inside the via holes through electroplating. In another version, no redistribution network is present. A key feature of the package is that the solder bumps are not located directly over the posts but are connected to them by surface pads, thereby isolating them from stresses due to rigidity of the posts. After formation of the solder bumps, the wafer is diced into individual chips thereby isolating the individual redistribution networks.

Abstract: Disclosed is a method for manufacturing a metal oxide semiconductor FET (MOSFET), which utilizes a low-temperature liquid phase oxidation for III-V group. The method includes the steps of (a) providing a substrate, (b) forming an epitaxial layer on the substrate, (c) defining and forming a drain and a source on a portion of the epitaxial layer, (d) forming a recess in an another portion of the epitaxial layer, (e) forming an oxide layer on a surface of the recess by relatively low-temperature oxidation, and (f) forming a gate on a portion of the oxide layer between the drain and source. In addition, the method further includes two selective procedures, that is, a synchronic sulfurated passivation process which can be performed with the growth of the oxide film simultaneously, and a rapid thermal annealing (RTA) process.

Abstract: Semiconductor integrated devices such as transistors are formed in a film of semiconductor material formed on a substrate. For improved device characteristics, the semiconductor material has regular, quasi-regular or single-crystal structure. Such a structure is made by a technique involving localized irradiation of the film with one or several pulses of a beam of laser radiation, locally to melt the film through its entire thickness. The molten material then solidifies laterally from a seed area of the film. The semiconductor devices can be included as pixel controllers and drivers in liquid-crystal display devices, and in image sensors, static random-access memories (SRAM), silicon-on-insulator (SOI) devices, and three-dimensional integrated circuit devices.

Abstract: Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or epitaxial re-growth, with gate oxide that is primarily Ga2O3, and with low midgap interface state density (e.g., at most 1×1011 cm−2 eV−1 at 20° C.). The method involves ion implantation, implant activation in an As-containing atmosphere, surface reconstruction, and in situ deposition of the gate oxide. In preferred embodiments, no processing step subsequent to gate oxide formation is carried out above 300° C. in air, or above about 700° C. in UHV. The method makes possible fabrication of planar enhancement-type MOS-FETs having excellent characteristics, and also makes possible fabrication of complementary MOS-FETs, as well as ICs comprising MOS-FETs and MES-FETs.

Abstract: An oxidation process that produces multi-layer, yet very thin oxides of silicon, formed on silicon substrates, includes pushing wafers at a particular range of speeds, into a furnace at a particular range of temperatures, sequentially oxidizing the wafers in varying chemical ambients, and operating an external chlorine compound generator coupled to the furnace. Oxides formed in this manner have good uniformity and low interface state density and are suitable for forming FETs. In a particular embodiment, a first portion of an oxide stack is formed in an oxygen/nitrogen ambient, a second portion of an oxide stack is formed in a carbon dioxide/hydrogen chloride/oxygen ambient, and a third portion of an oxide stack is formed by a wet oxidation. The second portion of the oxide stack is formed when 1,2-dichloroethylene is treated with heat and oxygen to produce carbon dioxide and hydrogen chloride gas that is then introduced into the furnace.

Abstract: The subject invention pertains to a method and device for producing large area single crystalline III-V nitride compound semiconductor substrates with a composition AlxInyGal-x-y N (where O≦x≦1, 0≦y≦1, and 0≦x+y≦1). In a specific embodiment, GaN substrates, with low dislocation densities (˜107 cm2) can be produced. These crystalline III-V substrates can be used to fabricate lasers and transistors. Large area free standing single crystals of III-V compounds, for example GaN, can be produced in accordance with the subject invention. By utilizing the rapid growth rates afforded by hydride vapor phase epitaxy (HVPE) and growing on lattice matching orthorhombic structure oxide substrates, good quality III-V crystals can be grown. Examples of oxide substrates include LiGaO2, LiAlO2, MgAlScO4, Al2MgO4, and LiNdO2. The subject invention relates to a method and apparatus, for the deposition of III-V compounds, which can alternate between MOVPE and HVPE, combining the advantages of both.

Abstract: The present invention provides a method of depositing a silicon oxide layer on a semiconductor wafer. The semiconductor wafer comprises a plurality of transistors positioned on its surface. The method comprises performing a cleaning process on the semiconductor wafer by using an alkaline solution to make a more uniform deposition rate of the silicon oxide layer on the transistors and other areas over the surface of the semiconductor wafer, then performing a deposition process by employing ozone as a reactive gas to form a silicon oxide layer of even thickness and without voids.

Abstract: A gate quality oxide-compound semiconductor structure (10) is formed by the steps of providing a III-V compound semiconductor wafer structure (13) with an atomically ordered and chemically clean semiconductor surface in an ultra high vacuum (UHV) system (20), directing a molecular beam (26) of gallium oxide onto the surface of the wafer structure to initiate the oxide deposition, and providing a second beam (28) of atomic oxygen to form a Ga.sub.2 O.sub.3 layer (14) with low defect density on the surface of the wafer structure. The second beam of atomic oxygen is supplied upon completion of the first 1-2 monolayers of Ga.sub.2 O.sub.3. The molecular beam of gallium oxide is provided by thermal evaporation from a crystalline Ga.sub.2 O.sub.3 or gallate source, and the atomic beam of oxygen is provided by either RF or microwave plasma discharge, thermal dissociation, or a neutral electron stimulated desorption atom source.

Abstract: An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere, slowly increasing the wafer temperature to the hard bake temperature at a predetermined ramp rate, and heating the wafer at the hard bake temperature for a predetermine amount of time. As a result, the dielectric material can repel wet etch chemicals and minimize the formation of holes in the dielectric materials due to etching by wet etch chemicals.

Abstract: A method is provided for forming a solder joint to a pad, in which the thickness of the intermetallic layer formed by nickel in contact with solder is significantly reduced. A first layer of nickel is provided on the pad; a second layer of a noble metal (preferably gold) is then provided overlying the first layer. The first layer and the second layer are then annealed, thereby forming an alloy layer including nickel and the noble metal between the first layer and the second layer. Contacting the second layer with a molten solder (where the solder includes tin) then causes the noble metal to dissolve in the solder and the solder to subsequently wet the alloy layer, forming an intermetallic layer including nickel, the noble metal and tin. Only a thin intermetallic film grows, thus improving the reliability of the solder joint.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new "trench-less" or "self-planarizing" method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

Abstract: A process for thermal oxidation of a semiconductor substrate comprising exposing the substrate to a chlorine plasma, and then heating the substrate in an oxidizing ambient. The substrate may comprise silicon, germanium, or a combination thereof. The heating step may further comprise heating at a temperature of between about 750.degree. C. and about 850.degree. C.

Abstract: In the manufacture of semiconductor components, a SiC single crystal is exposed, during storage or transport between two process steps, to an oxygen-containing gas atmosphere, for example air. In order to prevent an oxide coating from forming on the SiC surface of the SiC single crystal, a carbon coating which does not react chemically with oxygen, preferably a graphite coating, is produced on said SiC surface.

Abstract: Spacings between metal features are gap filled with HSQ without degradation of the electromigration resistance by depositing a conformal dielectric liner encapsulating the metal features before depositing the HSQ gap fill layer. Embodiments include depositing a conformal layer of a high density plasma oxide by high density plasma chemical deposition to a thickness of about 100 .ANG. to about 1,000 .ANG..

Abstract: An electro-conductive ultraviolet light transmitting Ga.sub.2 O.sub.3 material (10) with a metallic oxide phase is deposited on a GaAs substrate or supporting structure (12). The Ga.sub.2 O.sub.3 material or thin layer comprises a minor component of metallic IrO.sub.2. The Ga.sub.2 O.sub.3 thin layer may be positioned using thermal evaporation (106) of Ga.sub.2 O.sub.3 or of a Ga.sub.2 O.sub.3 containing a compound from an Iridium crucible (108). Alternatively, the Ir may be co-evaporated (110) by electron beam evaporation. The electro-conductive ultraviolet light transmitting material Ga.sub.2 O.sub.3 with a metallic oxide phase is suitable for use on solar cells and in laser lithography.

Abstract: An optoelectronic semiconductor device, whereby at least one functional semiconductor structure is arranged on a II-V semiconductor substrate. Inventively, an electrically conductive III-V semiconductor substrate is provided that exhibits a charge carrier concentration of more than 1*10.sup.15 cm.sup.-3. At least one electrically insulating oxide layer is provided between the functional semiconductor structure and the III-V semiconductor substrate.