Compound Semiconductor Substrate Patents (Class 438/779)
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Patent number: 6030453Abstract: A production process for protecting the surface of compound semiconductor wafers includes providing a multi-wafer epitaxial production system with a transfer and load module, a III-V growth chamber and an insulator chamber. The wafer is placed in the transfer and load module and the pressure is reduced to .ltoreq.10.sup.-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer.Type: GrantFiled: March 4, 1997Date of Patent: February 29, 2000Assignee: Motorola, Inc.Inventors: Matthias Passlack, Jonathan K. Abrokwah, Ravi Droopad, Corey D. Overgaard
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Patent number: 6028012Abstract: A method of fabricating a semiconductor structure involving the steps of providing a SiC substrate, treating the SiC substrate with an N.sub.2 O-containing plasma, and forming a dielectric layer on the surface of the pretreated SiC substrate. A semiconductor structure produced by the method above. An apparatus for forming a dielectric layer on a SiC substrate including a deposition chamber in which the SiC substrate is placed, a first valve that connects a first source providing N.sub.2 O to the deposition chamber, a second valve that connects a second source providing reactants that form the dielectric layer to the deposition chamber, an energy source for producing an N.sub.2 O-containing plasma from N.sub.2 O released from the first source by the first valve, and a controller that programs providing power to the energy source and opening and closing the first and second valves into two phases.Type: GrantFiled: December 4, 1996Date of Patent: February 22, 2000Assignee: Yale UniversityInventor: Xiewen Wang
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Patent number: 6025281Abstract: A method of passivating interface states of oxide-compound semiconductor interfaces using molecular, atomic, or isotopic species wherein said species are applied before oxide deposition in ultra-high vacuum, or during interruption of oxide deposition in ultra-high vacuum (preferentially after oxide surface coverage of a submonolayer, a monolayer, or a few monolayers), or during oxide deposition in ultra-high vacuum, or after completion of oxide deposition, or before or after any processing steps of the as deposited interface structure. In a preferred embodiment, hydrogen or deuterium atoms are applied to a Ga.sub.2 O.sub.3 --GaAs interface at some point before, during, or after oxide deposition in ultra-high vacuum, or before or after any processing steps of the as deposited interface structure, at any given and useful substrate temperature wherein the atomic species can be provided by any one of RF discharge, microwave plasma discharge, or thermal dissociation.Type: GrantFiled: December 18, 1997Date of Patent: February 15, 2000Assignee: Motorola, Inc.Inventors: Matthias Passlack, Jonathan K. Abrokwah, Sandeep Pendharkar, Stephen B. Clemens, Jimmy Z. Yu, Brian Bowers
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Patent number: 6004886Abstract: A method for growing a silicon dioxide film on a HgCdTe substrate includes a first step in which the HgCdTe substrate is cleaned with an alkaline aqueous solution. The cleaned HgCdTe substrate is then dried before being immersed in a liquid phase deposition solution in which the silicon dioxide film is deposited on the surface of the HgCdTe substrate at the rate as high as 1672 .ANG./hr. The silicon dioxide film has a refraction rate as high as 1.465.Type: GrantFiled: October 30, 1997Date of Patent: December 21, 1999Assignee: National Science CouncilInventors: Mau-Phon Houng, Yeong-Her Wang, Na-Fu Wang
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Patent number: 5998304Abstract: A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.Type: GrantFiled: September 2, 1997Date of Patent: December 7, 1999Assignee: National Science CouncilInventors: Mau-Phon Houng, Yeong-Her Wang, Chien-Jung Huang
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Patent number: 5994241Abstract: A method of forming metal lines in a patterned dielectric layer. First, a thin (50 .ANG.-500 .ANG.) metal layer of a group VB metal, preferably niobium, is formed on a patterned dielectric layer. Next, an aluminum layer or an aluminum alloy layer is formed on the thin niobium layer. The aluminum layer is preferably formed by depositing a first thickness of collimated aluminum at low temperature followed by high temperature deposition of an equal thickness of aluminum. The aluminum layer is Chem-Mech polished (CMP) with an oxidizing acidic colloidal alumina slurry to expose and oxidize the thin niobium liner which acts as a polish stop. Then, the exposed thin niobium liner is removed using CMP. Alternatively, instead of niobium, the liner may be a thin layer of a group VB metal or an alloy thereof.Type: GrantFiled: July 31, 1996Date of Patent: November 30, 1999Assignee: International Business Machines CorporationInventor: Maria Ronay
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Patent number: 5970381Abstract: A method is provided that produces a good, strong organic monomolecular film having its atoms arranged in a three-dimensionally ordered manner by cleaving a III-V group compound semiconductor substrate in film formation molecules or in a solution containing them, in order to cause selective chemisorption which forms a monomolecular film and then deposits another layer of organic molecule film. In this method, the III-V group compound semiconductor substrate is cleaved in a solution containing SH groups dissolved into a solvent in order to form a self-assembled monolayer and is then placed in another solution, where metallic ions are adsorbed to the surface of the film or where the functional groups are converted by chemical treatment. The substrate is then immersed in a solution containing organic molecules that are selectively chemisorbed to the functional groups.Type: GrantFiled: September 5, 1997Date of Patent: October 19, 1999Assignee: National Institute for Advanced Interdisciplinary ResearchInventors: Hirotaka Ohno, Larry A. Nagahara, Hiroshi Tokumoto
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Patent number: 5930656Abstract: A substrate for forming a compound semiconductor device is placed in a reaction chamber. An MOCVD method or a GS-MBE method is used to grow compound semiconductor layers on the substrate. The grown layers include, for example, a GaN buffer layer, an n-GaN layer, an InGaN active layer, a p-AlGaN layer, and a p.sup.+ -GaN contact layer. After the growth of the layers, the substrate is kept in the reaction chamber, and a passivation film of, for example, SiNx, SiO2, or SiON is formed on top of the grown layers according to a CVD or GS-MBE method. Since the top of the grown layers is not exposed to air outside the reaction chamber, no oxidization or contamination occurs on the top of the grown layers. The compound semiconductor device is manufactured through simpler processes compared with a prior art that needs separate apparatuses for growing and forming the layers and passivation film.Type: GrantFiled: October 17, 1997Date of Patent: July 27, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Chisato Furukawa, Masayuki Ishikawa, Hideto Sugawara, Kenji Isomoto
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Patent number: 5904553Abstract: A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.Type: GrantFiled: August 25, 1997Date of Patent: May 18, 1999Assignee: Motorola, Inc.Inventors: Matthias Passlack, Jonathan K. Abrokwah, Ravi Droopad, Brian Bowers
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Patent number: 5903037Abstract: It has been found that a Ga-oxide-containing layer is substantially not etched in HF solution if the layer is a Ga-Gd-oxide with Gd:Ga atomic ratio of more than about 1:7.5, preferably more than 1:4 or even 1:2. This facilitates removal of a protective dielectric (typically SiO.sub.2) layer after an ohmic contact anneal, with the Ga-Gd-oxide gate oxide layer serving as etch stop and not being adversely affected by contact with the HF etchant. Gd-Ge-oxide also exhibits a composition-dependent etch rate in HCl:H.sub.2 O.Type: GrantFiled: February 24, 1997Date of Patent: May 11, 1999Assignee: Lucent Technologies Inc.Inventors: Alfred Yi Cho, Minghwei Hong, James Robert Lothian, Joseph Petrus Mannaerts, Fan Ren
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Patent number: 5821171Abstract: A high quality interface between a GaAs-based semiconductor and a Ga.sub.2 O.sub.3 dielectric an be formed if the semiconductor surface is caused to have less than 1% of a monolayer impurity coverage at completion of the first monolayer of the Ga.sub.2 O.sub.3 on the surface. This is achieved, for instance, by preparing the surface of a GaAs wafer under UHV conditions in a first growth chamber, transferring the wafer through a transfer module under UHV to a second growth chamber that is also under UHV, and growing the dielectric by evaporation of Ga.sub.2 O.sub.3 from a solid source, the process carried out such that the integrated impurity exposure of the surface is at most 100 Langmuirs. Articles according to the invention have low interface state density (<10.sup.11 /cm.sup.2 .multidot.eV) and interface recombination velocity (<10.sup.4 cm/s). Semiconductor/Ga.sub.2 O.sub.3 structures according to the invention can be used advantageously in a variety of electronic or optoelectronic devices, e.g.Type: GrantFiled: March 22, 1995Date of Patent: October 13, 1998Assignee: Lucent Technologies Inc.Inventors: Minghwei Hong, Jueinai Raynien Kwo, Joseph Petrus Mannaerts, Matthias Passlack, Fan Ren, George John Zydzik
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Patent number: 5776837Abstract: A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.Type: GrantFiled: November 19, 1996Date of Patent: July 7, 1998Assignee: Cree Research, Inc.Inventor: John W. Palmour
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Patent number: 5665658Abstract: A method of forming a stable semiconductor device on an at least partially completed semiconductor device including a supporting semiconductor structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer structure. A relatively thin layer of Ga.sub.2 O.sub.3 is deposited on the surface by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide, such as MgO or Gd.sub.2 O.sub.3. A second layer of material with low bulk trap density relative to the Ga.sub.2 O.sub.3 is deposited on the layer of Ga.sub.2 O.sub.3 to complete the dielectric layer structure.Type: GrantFiled: March 21, 1996Date of Patent: September 9, 1997Assignee: MotorolaInventor: Matthias Passlack