Depositing Organic Material (e.g., Polymer, Etc.) Patents (Class 438/780)
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Patent number: 8808798Abstract: A coating method includes supplying a coating liquid from a coating nozzle onto a front side central portion of a substrate held on a substrate holding member, rotating the substrate holding member about a vertical axis to spread the coating liquid toward a peripheral portion of the substrate by a centrifugal force and thereby form a film of the coating liquid, forming a liquid film of a process liquid for preventing a contaminant derived from the coating liquid from being deposited or left on a back side peripheral portion of the substrate, and damping a vertical wobble of the peripheral portion of the substrate being rotated, by a posture regulating mechanism, while delivering a gas from delivery holes onto a back side region of the substrate on an inner side of the peripheral portion on which the liquid film is formed.Type: GrantFiled: August 8, 2012Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventors: Takahiro Kitano, Koichi Obata, Hiroichi Inada, Nobuhiro Ogata
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Patent number: 8802490Abstract: Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.Type: GrantFiled: April 13, 2011Date of Patent: August 12, 2014Assignee: Empire Technology Development LLCInventor: Seth Miller
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Patent number: 8802569Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.Type: GrantFiled: March 13, 2012Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Liang Lu, Ming-Feng Shieh, Ching-Yu Chang
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Patent number: 8802488Abstract: A substrate depositing system and a method of using a substrate depositing system. A substrate depositing system includes a load-lock chamber for loading and unloading a substrate, at least one transfer chamber connected to the load-lock chamber and including a substrate transfer device configured to vertically transfer the substrate, and a pair of depositing chambers connected to opposite sides of the at least one transfer chamber and including a depositing source and a pair of substrate fixing devices, the substrate transfer device including a pair of substrate installing members.Type: GrantFiled: July 8, 2011Date of Patent: August 12, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jeong-Ho Yi, Suk-Won Jung, Seung-Ho Choi
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Patent number: 8796158Abstract: A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.Type: GrantFiled: January 9, 2012Date of Patent: August 5, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Kyoung-sei Choi
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Patent number: 8791033Abstract: A process for coating a semiconductor wafer with a coating composition comprises curing the coating with a pulsed UV light, thereby preventing delamination during reflow operations. In a particular embodiment, the coating composition comprises both epoxy and acrylate resins. The epoxy resin can be cured thermally; the acrylate resin is cured by UV irradiation.Type: GrantFiled: December 7, 2012Date of Patent: July 29, 2014Assignee: Henkel IP & Holding GmbHInventors: Jeffrey Gasa, Dung Nghi Phan, Jeffrey Leon, Sharad Hajela, Shengqian Kong
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Patent number: 8790859Abstract: The present invention relates to a photoresist composition for digital exposure and a method of fabricating a thin film transistor substrate. The photoresist composition for digital exposure includes a binder resin including a novolak resin and a compound represented by the chemical formula (1), a photosensitizer including a diazide-based compound, and a solvent: wherein R1-R9 each include a hydrogen atom, an alkyl group, or a benzyl group, a is an integer from 0 to 10, b is an integer from 0 to 100, and c is an integer from 0 to 10.Type: GrantFiled: November 18, 2009Date of Patent: July 29, 2014Assignee: Samsung Display Co., Ltd.Inventors: Sang-Hyun Yun, Woo-Seok Jeon, Jung-In Park, Hi-Kuk Lee, Byung-Uk Kim, Dong-Min Kim, Seung-Ki Kim, Ja-Hun Byeon
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Patent number: 8790785Abstract: A method of forming a porous insulation film uses an organic silica material gas having a 3-membered SiO cyclic structure and a 4-membered SiO cyclic structure, or an organic silica material gas having a 3-membered SiO cyclic structure and a straight-chain organic silica structure, and uses a plasma reaction in the filming process. A porous interlevel dielectric film having a higher strength and a higher adhesive property can be obtained.Type: GrantFiled: July 23, 2007Date of Patent: July 29, 2014Assignee: Renesas Electronics CorporationInventors: Hironori Yamamoto, Fuminori Ito, Munehiro Tada, Yoshihiro Hayashi
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Publication number: 20140203414Abstract: The invention provides a method for chemically modifying a surface of a substrate, preferably a silicon substrate, including the steps of providing a substrate having at least a portion of a surface thereof coated with an organic coating composition including unsaturated moieties forming a surface coating, and introducing a vapour phase reactive intermediate species based on a Group 14 or Group 15 element from the Periodic Table of Elements to the substrate whereupon the reactive intermediate species is able to react with a number of the unsaturated moieties in the coating composition thereby chemically modifying the surface coating. Also disclosed is a surface-modified substrate obtained or obtainable by the method, and uses thereof in the fabrication of MEMS and IC devices.Type: ApplicationFiled: August 15, 2012Publication date: July 24, 2014Applicant: UNIVERSITY COURT OF THE UNIVERSITY OF ST ANDREWSInventors: Georg Haehner, Malgorzata Adamkiewicz, David O'Hagan
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Patent number: 8785215Abstract: A method for repairing process-related damage of a dielectric film includes: (i) adsorbing a first gas containing silicon on a surface of the damaged dielectric film without depositing a film in the absence of reactive species, (ii) adsorbing a second gas containing silicon on a surface of the dielectric film, followed by applying reactive species to the surface of the dielectric film, to form a monolayer film thereon, and (iii) repeating step (ii). The duration of exposing the surface to the first gas in step (i) is longer than the duration of exposing the surface to the second gas in step (ii).Type: GrantFiled: May 23, 2013Date of Patent: July 22, 2014Assignee: ASM IP Holding B.V.Inventors: Akiko Kobayashi, Yosuke Kimura, Dai Ishikawa, Kiyohiro Matsushita
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Patent number: 8785329Abstract: In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.Type: GrantFiled: December 27, 2012Date of Patent: July 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shimon Maeda, Kenji Konomi
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Patent number: 8786049Abstract: Solid-state thin-film capacitors are provided. Aspects of the solid-state thin-film capacitors include a first electrode layer of a transition metal, a dielectric layer of an oxide of the transition metal, and a second electrode layer of a metal oxide. Also provided are methods of making the solid-state thin-film capacitors, as well as devices that include the same. The capacitor may have one or more cathodic arc produced structures, i.e., structures produced using a cathodic arc deposition process. The structures may be stress-free metallic structures, porous layers and layers displaying crenulations. Aspects of the invention further include methods of producing capacitive structures using chemical vapor deposition and/or by sputter deposition.Type: GrantFiled: July 23, 2010Date of Patent: July 22, 2014Assignee: Proteus Digital Health, Inc.Inventor: Hooman Hafezi
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Patent number: 8785333Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, carbon, nitrogen and a borazine ring skeleton on a substrate by performing a cycle for a first predetermined number of times. The cycle includes forming a first layer containing the predetermined element, a halogen group, carbon and nitrogen by supplying a first precursor gas containing the predetermined element and the halogen group and a second precursor gas containing the predetermined element and an amino group to the substrate, for a second predetermined number of times; and forming a second layer containing the predetermined element, carbon, nitrogen and the borazine ring skeleton by supplying a reaction gas containing a borazine compound to the substrate and allowing the first layer to react with the borazine compound to modify the first layer under a condition where the borazine ring skeleton in the borazine compound is maintained.Type: GrantFiled: August 22, 2013Date of Patent: July 22, 2014Assignee: Hitachi Kokusai Electric Inc.Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Satoshi Shimamoto, Atsushi Sano
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Patent number: 8778809Abstract: A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used.Type: GrantFiled: March 14, 2013Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideaki Kuwabara
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Patent number: 8778814Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: GrantFiled: August 14, 2013Date of Patent: July 15, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tamotsu Owada, Shun-ichi Furuyama, Hirofumi Watantani, Kengo Inoue, Atsuo Shimizu
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Patent number: 8778727Abstract: Provided is a method of manufacturing an organic electroluminescence display device including: an organic compound layer-forming step of forming an organic compound layer on a first electrode; a release layer-forming step of forming a release layer on the organic compound layer; a first processing step for the release layer of patterning the release layer; an organic compound layer-processing step of removing the organic compound layer in a region not covered with the release layer processed in the first processing step for the release layer; and a second processing step for the release layer of removing a part of the release layer, in which the release layer is a deposited film formed of a charge-transportable organic compound and is dissolved by a solvent containing an organic solvent miscible with water.Type: GrantFiled: April 9, 2012Date of Patent: July 15, 2014Assignee: Canon Kabushiki KaishaInventors: Satoru Shiobara, Jun Kamatani, Yosuke Nishide, Taro Endo, Tomoyuki Hiroki, Nobuhiko Sato
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Patent number: 8772180Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.Type: GrantFiled: March 8, 2012Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Ya Ou, Shom Ponoth, Terry A. Spooner
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Patent number: 8766411Abstract: A filler for filling a gap includes a compound represented by the following Chemical Formula 1. SiaNbOcHd.??[Chemical Formula 1] In Chemical Formula 1, a, b, c, and d represent relative amounts of Si, N, 0, and H, respectively, in the compound, 1.96<a<2.68, 1.78<b<3.21, 0?c<0.19, and 4<d<10.Type: GrantFiled: July 13, 2012Date of Patent: July 1, 2014Assignee: Cheil Industries, Inc.Inventors: Eun-Su Park, Bong-Hwan Kim, Sang-Hak Lim, Taek-Soo Kwak, Jin-Hee Bae, Hui-Chan Yun, Sang-Kyun Kim, Jin-Wook Lee
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Patent number: 8759212Abstract: A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.Type: GrantFiled: May 5, 2011Date of Patent: June 24, 2014Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Jun Kawahara, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 8758855Abstract: A coating film forming apparatus that holds a substrate upon a spin chuck and forms a coating film by supplying a chemical liquid upon a top surface of said substrate comprises: an outer cup provided detachably to surround the spin chuck; an inner cup provided detachably to surround a region underneath the substrate held upon the chuck; a cleaning nozzle configured to supply a cleaning liquid for cleaning a peripheral edge part of the substrate, such that the cleaning liquid is supplied to a peripheral part of a bottom surface of the substrate; a cutout part for nozzle mounting, the cutout part being provided to the inner cup to engage with the cleaning nozzle; and a cleaning liquid supply tube connected to the cleaning nozzle, the cleaning nozzle being detachable to the cutout part in a state in which the cleaning liquid supply tube is connected.Type: GrantFiled: March 19, 2012Date of Patent: June 24, 2014Assignee: Tokyo Electron LimitedInventors: Nobuhiro Ogata, Hiroichi Inada, Taro Yamamoto, Akihiro Fujimoto
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Patent number: 8753947Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: February 4, 2012Date of Patent: June 17, 2014Assignees: NthDegree Technologies Worldwide Inc, NASAInventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8753946Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: February 4, 2012Date of Patent: June 17, 2014Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United StatesInventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8753986Abstract: A deposition for producing a porous organosilica glass film comprising: introducing into a vacuum chamber gaseous reagents including one precursor of an organosilane or an organosiloxane, and a porogen distinct from the precursor, wherein the porogen is aromatic in nature; applying energy to the gaseous reagents in the chamber to induce reaction of the gaseous reagents to deposit a film, containing the porogen; and removing substantially all of the organic material by UV radiation to provide the porous film with pores and a dielectric constant less than 2.6.Type: GrantFiled: December 15, 2010Date of Patent: June 17, 2014Assignee: Air Products and Chemicals, Inc.Inventors: Mary Kathryn Haas, Raymond Nicholas Vrtis, Laura M. Matz
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Patent number: 8748325Abstract: A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface.Type: GrantFiled: March 1, 2013Date of Patent: June 10, 2014Inventors: Mitsuhiro Horikawa, Hiroyuki Ode, Masashi Haruki, Shigeki Takishima, Shinichi Kihara
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Patent number: 8736014Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.Type: GrantFiled: November 14, 2008Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Jiun Lin, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao, Chen-Hua Yu
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Patent number: 8736051Abstract: A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH3 near a wave number 1270 cm?1 to a peak height of Si—O near a wave number 1030 cm?1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH2—Si near a wave number 1360 cm?1 to the peak height of Si—CH3 near the wave number 1270 cm?1 is 0.031 or greater.Type: GrantFiled: February 14, 2013Date of Patent: May 27, 2014Assignee: Renesas Electronics CorporationInventors: Tatsuya Usami, Tomoyuki Nakamura, Naoki Fujimoto
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Publication number: 20140141221Abstract: Apparatuses and methods are described that involve the deposition of polymer coatings on substrates. The polymer coatings generally comprise an electrically insulating layer and/or a hydrophobic layer. The hydrophobic layer can comprise fused polymer particles have an average primary particle diameter on the nanometer to micrometer scale. The polymer coatings are deposited on substrates using specifically adapted plasma enhanced chemical vapor deposition approaches. The substrates can include computing devices and fabrics.Type: ApplicationFiled: March 15, 2013Publication date: May 22, 2014Applicant: Liquipel, LLCInventors: Daniel Storey, Demetrius Chrysostomou, Vincent Galbreath, Alex Hill, Daniel McPhail
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Patent number: 8728955Abstract: A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido)silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant andType: GrantFiled: March 1, 2012Date of Patent: May 20, 2014Assignee: Novellus Systems, Inc.Inventors: Adrien LaVoie, Mark J. Saly, Daniel Moser, Rajesh Odedra, Ravi Konjolia
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Publication number: 20140131882Abstract: This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 ?m.Type: ApplicationFiled: November 12, 2012Publication date: May 15, 2014Applicant: Hong Kong Applied Science and Technology Research Institute Company LimitedInventor: Hong Kong Applied Science and Technology Institute Company Limited
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Patent number: 8716125Abstract: Embodiments of the present invention provide methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers. A copper region is formed in a dielectric layer. A diffusion barrier comprising a self-assembled monolayer is deposited over the copper region. A capping layer is deposited over the self-assembled monolayer. In some embodiments, the capping layer and self-assembled monolayer are deposited in the same process chamber.Type: GrantFiled: August 10, 2012Date of Patent: May 6, 2014Assignee: Globalfoundries Inc.Inventor: Jinhong Tong
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Patent number: 8716151Abstract: The present disclosure relates to a method of fabricating semiconductor devices. In the method provided by the present invention, by filling with diblock copolymer a recess of an interlayer dielectric layer naturally formed between two gate lines and then performing a self-assembly process of the diblock copolymer, a small-sized contact hole precisely aligned with an doped area can be formed, and thus misalignment between the contact hole and the doped area can be eliminated or alleviated.Type: GrantFiled: December 15, 2011Date of Patent: May 6, 2014Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Haiyang Zhang, Dongjiang Wang
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Patent number: 8709943Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.Type: GrantFiled: May 13, 2013Date of Patent: April 29, 2014Assignee: Intermolecular, Inc.Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
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Patent number: 8709957Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.Type: GrantFiled: May 25, 2012Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ibrahim Alhomoudi
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Patent number: 8698189Abstract: An OLED device includes a thin film transistor including an active layer, a gate bottom electrode, a gate top electrode, an insulating layer covering the gate electrode, and a source electrode and a drain electrode on the insulating layer contacting the active layer; an organic light-emitting device electrically connected to the thin film transistor and including a sequentially stacked pixel electrode, on the same layer as the gate bottom electrode, emissive layer, and, opposite electrode, a pad bottom electrode on the same layer as the gate bottom electrode and a pad top electrode pattern on the same layer as the gate top electrode, the pad top electrode pattern including openings exposing the pad bottom electrode, and an insulation pattern covering the upper surface of the pad top electrode pattern on the same layer as the insulating layer, on an upper surface of the pad bottom electrode.Type: GrantFiled: November 18, 2011Date of Patent: April 15, 2014Assignee: Samsung Display Co., Ltd.Inventors: Sun Park, Jong-Hyun Park, Yul-Kyu Lee, Kyung-Hoon Park, Sang-Ho Moon
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Patent number: 8692367Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.Type: GrantFiled: October 1, 2012Date of Patent: April 8, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Chiung C. Lo, Arkadii V. Samoilov, Reynante T. Alvarado
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Patent number: 8691336Abstract: A coating treatment method includes: a first step of discharging a coating solution from a nozzle to a central portion of a substrate while acceleratingly rotating the substrate, to apply the coating solution over the substrate; a second step of then decelerating the rotation of the substrate and continuously rotating the substrate; and a third step of then accelerating the rotation of the substrate to dry the coating solution on the substrate. In the first step, the acceleration of the rotation of the substrate is changed in the order of a first acceleration, a second acceleration higher than the first acceleration, and a third acceleration lower than the second acceleration to acceleratingly rotate the substrate at all times.Type: GrantFiled: March 23, 2011Date of Patent: April 8, 2014Assignee: Tokyo Electron LimitedInventors: Kousuke Yoshihara, Katsunori Ichino
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Patent number: 8685865Abstract: A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.Type: GrantFiled: September 10, 2012Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-ju Park, Kyoung-mi Kim, Min-jung Kim, Dong-jun Lee, Boo-deuk Kim
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Patent number: 8673792Abstract: An object of the invention is to provide a method of making a p-terphenyl compound mixture which includes two symmetric p-terphenyl compounds respectively represented by formula (1) and formula (2) and an asymmetric p-terphenyl compound represented by formula (3)Type: GrantFiled: June 12, 2013Date of Patent: March 18, 2014Assignee: Hodogaya Chemical Co., Ltd.Inventors: Shinya Nagai, Atsushi Takesue, Makoto Koike, Katsumi Abe, Takehiro Nakajima
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Patent number: 8673702Abstract: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.Type: GrantFiled: August 4, 2006Date of Patent: March 18, 2014Assignee: Creator Technology B.V.Inventors: Fredericus Johannes Touwslager, Gerwin Hermanus Gelinck
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Patent number: 8658462Abstract: Provided is a method of forming a method of forming a titanium dioxide (TiO2) array using a zinc oxide (ZnO) template. In the method, polymer nanopatterns are formed on the substrate, and monomolecular monolayers are formed between the polymer nanopatterns on the substrate. A seed layer pattern is formed between the monomolecular monolayers on the substrate, and a zinc oxide template is formed by growing zinc oxide on the seed layer.Type: GrantFiled: November 9, 2011Date of Patent: February 25, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Mi Hee Jung, Man Gu Kang
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Patent number: 8657889Abstract: An arrangement (1) for holding a substrate (10) in a material deposition apparatus, which substrate (10) has a deposition side (10a) upon which material (M) is to be deposited, and which arrangement (1) comprises: a shadow mask (20) comprising a number of deposition openings (Di); a support structure (30) comprising a number of surround openings (Si); and a support structure holding means (6) for holding the support mask (30) and/or a substrate holding means (5) for holding the substrate (10), such that the support structure (30) is on the same side as the deposition side (10a) of the substrate (10), and the shadow mask (20) is positioned between the substrate (10) and the support structure (30) such that at least one deposition opening (Di) of the shadow mask (10) lies within a corresponding surround opening (Si) of the support structure (30).Type: GrantFiled: March 29, 2010Date of Patent: February 25, 2014Assignee: OSRAM Opto Semiconductors GmbHInventors: Johannes Krijne, Erwin Eiling, Karl-Heinz Hohaus, Wolfgang Goergen, Andreas Lovich, Marc Philippens, Richard Scheicher, Ansgar Fischer, Martin Mueller
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Patent number: 8659114Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench formed in an element isolating area of the semiconductor substrate, and a silicon oxide film that is embedded in the trench and contains an alkali metal element or alkali earth metal element.Type: GrantFiled: December 2, 2011Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Keisuke Nakazawa
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Patent number: 8652950Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.Type: GrantFiled: February 25, 2013Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Alfred Grill, Thomas J. Haigh, Jr., Sanjay Mehta
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Patent number: 8652965Abstract: One object of the present invention is to provide a method for producing a thick film metal electrode that is able to form a positive-negative reverse type resist, which has a thickness of 7 ?m or more and excellent in-plane uniformity, on the circuit element formed on the silicon carbide substrate, and a method for producing a thick film resist, and the present invention provides a method for producing a thick film resist wherein a first positive-negative reverse type resist having a first viscosity is formed on an upper surface of a circuit element layer which is treated with HMDS, and a second positive-negative reverse type resist having a second viscosity, which is larger than the first viscosity, on the first positive-negative reverse type resist such that a total thickness of the first and second positive-negative reverse type resists constituting a thick film resist be 7 ?m or more.Type: GrantFiled: March 9, 2012Date of Patent: February 18, 2014Assignee: Showa Denko K.K.Inventor: Kenji Suzuki
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Patent number: 8652571Abstract: A spin coating apparatus that supplies a coating liquid to a substrate and rotating the substrate to form a coating film, has a holding part that holds the substrate mounted thereon in a horizontal position; a rotationally driving source that rotationally drives the holding part about a rotational axis parallel with the vertical direction, thereby rotating the substrate; and a coating liquid supplying part that supplies the coating liquid to the substrate held by the holding part.Type: GrantFiled: March 3, 2009Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Keisuke Nakazawa
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Publication number: 20140038428Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Tsung-Min Huang, Chung-Ju Lee, Chien-Hua Huang
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Patent number: 8644598Abstract: A method of pattern recognition is disclosed. The method includes steps of: providing a cellular computer structure with processing cell units arranged in layers; sensing the threshold parameter in an unknown pattern accessible; creating a binary number for each sensed threshold parameter; storing each binary number; creating a binary sequence; calculating a decimal number from each binary sequence; storing each decimal number in the central hexagram cell; outputting the binary sequence; preserving position information of each binary sequence; enabling the hidden layer to adjust the threshold parameter; and analyzing the binary numbers in the hidden layer to compare with known patterns to establish a recognized pattern.Type: GrantFiled: May 27, 2011Date of Patent: February 4, 2014Inventor: Neven Dragojlovic
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Patent number: 8642485Abstract: A method for fabricating a patterned polyimide film, wherein the method comprises steps as follows: Firstly, a polyimide film is provided on a substrate. A wet planarization process is then performed to remove a portion of the polyimide film. Subsequently the planarized polyimide film is patterned.Type: GrantFiled: June 14, 2012Date of Patent: February 4, 2014Assignee: United Microelectronics CorporationInventor: Chin-Yi Lin
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Patent number: 8637396Abstract: A method is provided for depositing a dielectric barrier film including a precursor with silicon, carbon, oxygen, and hydrogen with improved barrier dielectric properties including lower dielectric constant and superior electrical properties. This method will be important for barrier layers used in a damascene or dual damascene integration for interconnect structures or in other dielectric barrier applications. In this example, specific structural properties are noted that improve the barrier performance.Type: GrantFiled: November 23, 2009Date of Patent: January 28, 2014Assignee: Air Products and Chemicals, Inc.Inventors: Laura M. Matz, Raymond Nicholas Vrtis, Mark Leonard O'Neill, Dino Sinatore
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Patent number: RE44941Abstract: A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad.Type: GrantFiled: June 29, 2012Date of Patent: June 10, 2014Assignee: Emagin CorporationInventors: Amalkumar P. Ghosh, Yachin Liu, Hua Xia Ji