Depositing Organic Material (e.g., Polymer, Etc.) Patents (Class 438/780)
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Publication number: 20110244695Abstract: The present invention relates to a method for preparation of an ultraviolet (UV)-curable inorganic-organic hybrid resin containing about or less than 4% volatiles and less than 30% organic residues. The UV-curable inorganic-organic hybrid resin obtained according to this method can be UV-cured within a markedly very short time and enables, upon curing, the formation of a transparent shrink- and crack-free glass-like product having high optical quality, high thermal stability and good bonding properties. In view of these properties, this hybrid resin can be used in various applications such as electro-optic, microelectronic, stereolithography and biophotonic applications.Type: ApplicationFiled: December 3, 2009Publication date: October 6, 2011Applicant: SOREQ NUCLEAR rESEARCH CENTERInventor: Raz Gvishi
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Publication number: 20110241229Abstract: In various embodiments, the present invention relates to production of encapsulated nanoparticles by dispersing said nanoparticles and an encapsulating medium in a common solvent to form a first solution system and applying a stimulus to said first solution system to induce simultaneous aggregation of the nanoparticles and the encapsulating medium.Type: ApplicationFiled: March 30, 2011Publication date: October 6, 2011Applicant: NANOCO TECHNOLOGIES LIMTEDInventors: Imad Naasani, James Gillies, Emma Fitzgerald, Xiaojuan Wang, Ombretta Masala
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Publication number: 20110241210Abstract: The invention provides a composition for sealing a semiconductor, the composition being able to form a thin resin layer, suppress the diffusion of a metal component to a porous interlayer dielectric layer, and exhibit superior adherence with respect to an interconnection material. The composition for sealing a semiconductor contains a resin having two or more cationic functional groups and a weight-average molecular weight of from 2,000 to 100,000; contains sodium and potassium each in an amount based on element content of not more than 10 ppb by weight; and has a volume average particle diameter, measured by a dynamic light scattering method, of not more than 10 nm.Type: ApplicationFiled: May 28, 2010Publication date: October 6, 2011Applicant: MITSUI CHEMICALS, INC.Inventors: Shoko Ono, Kazuo Kohmura
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Patent number: 8030126Abstract: Exemplary embodiments provide materials and processes for forming organic semiconductor features by heating a liquid composition containing semiconductor particles into a Newtonian solution for a uniform deposition.Type: GrantFiled: September 15, 2009Date of Patent: October 4, 2011Assignee: Xerox CorporationInventors: Yiliang Wu, Stephan Drappel, Nan-Xing Hu, Paul F. Smith
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Patent number: 8028621Abstract: Methods of fabricating three-dimensional structures comprise: contacting a printing plate face with a suspension comprising particles to arrange the particles at predefined positions on the printing plate face, the predefined positions comprising a first position laterally adjacent to a second position; positioning the printing plate with the printing plate face turned toward a substrate and the first position aligned to a protrusion on the substrate; contacting the protrusion with a first layer of particles disposed at the first position of the printing plate to transfer the first layer of particles to a protrusion surface; moving the printing plate laterally to align the second position to the protrusion; and contacting the first layer of particles disposed on the protrusion surface with a second layer of particles disposed at the second position of the printing plate to transfer the second layer of particles to on top of the first layer of particles.Type: GrantFiled: May 2, 2008Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Tobias Kraus, Heiko Wolf
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Patent number: 8030200Abstract: A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.Type: GrantFiled: September 23, 2009Date of Patent: October 4, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yong Sung Eom, Kwang-Seong Choi, Hyun-Cheol Bae, Jong-Hyun Lee, Jong Tae Moon
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Patent number: 8026114Abstract: An emitter has a plurality of types of light-emitting units with different changes in emission characteristics over time. In addition, the emitter includes a deterioration adjustment device which adjusts the deterioration of the emission characteristics over time in a predetermined type of light-emitting unit. The light-emitting units respectively include a light-emitting layer and a hole donor which supplies positive holes to the light-emitting layer, and the deterioration adjustment device may be the hole donor in which the thickness is adjusted based on the deterioration in emission characteristics over time in the predetermined type of light-emitting unit.Type: GrantFiled: October 27, 2006Date of Patent: September 27, 2011Assignee: Seiko Epson CorporationInventor: Hirofumi Sakai
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Patent number: 8026185Abstract: An object of the present invention is to provide a method for manufacturing an electronic circuit component such as an organic TFT 1, which can manufacture an electronic circuit component excellent in reliability and having quality on a practical level, because an insulating layer and a conductive layer which have more excellent characteristics can be formed, particularly, on a general-purpose plastic substrate or the like by treatment at a process temperature of 200° C. or lower which has no influence on the above-mentioned plastic substrate. The method for manufacturing an electronic circuit component according to the invention includes heating a layer containing at least one of a polyimide and a precursor thereof at a temperature of 200° C.Type: GrantFiled: August 3, 2007Date of Patent: September 27, 2011Assignees: Sumitomo Electric Industries, Ltd., Nissan Chemical Industries, Ltd.Inventors: Shinichi Maeda, Go Ono, Issei Okada, Kohei Shimoda
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Patent number: 8021975Abstract: A plasma processing method for forming a film on a substrate using a gas processed by a plasma. The plasma processing method for forming a film includes the steps of forming a CF film on the substrate by using a CaFb gas (here, a is a counting number, and b is a counting number which satisfies an equation of “b=2×a?2”), processing the CF film with the gas processed by the plasma, and forming an insulating film on the CF film processed by using an insulating material processed with the plasma.Type: GrantFiled: December 28, 2007Date of Patent: September 20, 2011Assignee: Tokyo Electron LimitedInventors: Kotaro Miyatani, Kohei Kawamura, Toshihisa Nozawa, Takaaki Matsuoka
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Patent number: 8017527Abstract: Apparatuses and methods for diverting a flow of a liquid precursor during flow stabilization and plasma stabilization stages during PECVD processes are effective at eliminating particle defects in PECVD films deposited using a liquid precursor.Type: GrantFiled: December 16, 2008Date of Patent: September 13, 2011Assignee: Novellus Systems, Inc.Inventors: Arul N. Dhas, Ming Li, Joseph Bradley Laird
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Patent number: 8012887Abstract: Methods of depositing silicon oxide layers on substrates involve flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that a uniform silicon oxide growth rate is achieved across the substrate surface. The surface of silicon oxide layers grown according to embodiments may have a reduced roughness when grown with the additive precursor. In other aspects of the disclosure, silicon oxide layers are deposited on a patterned substrate with trenches on the surface by flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that the trenches are filled with a reduced quantity and/or size of voids within the silicon oxide filler material.Type: GrantFiled: June 22, 2009Date of Patent: September 6, 2011Assignee: Applied Materials, Inc.Inventors: Shankar Venkataraman, Hiroshi Hamana, Manuel A. Hernandez, Nitin K. Ingle, Paul Edward Gee
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Patent number: 8003487Abstract: In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.Type: GrantFiled: December 16, 2008Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Du-Hyun Cho, Jong-Heui Song, Sang-Sup Jeong, Tae-Woo Kang, Seung-Joo Yoo
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Publication number: 20110200790Abstract: The present invention concerns a method for localized grafting of an organic film in a selected area of an electrically conducting or semiconducting substrate, in the presence of a liquid solution containing at least one organic adhesion primer and at least one radically polymerizable monomer, different from the organic adhesion primer, by applying an electric potential to the substrate in the presence of a polarized microelectrode. The present invention also concerns an insulating organic film grafted on a conducting or semiconducting substrate, capable of being prepared using said method.Type: ApplicationFiled: March 26, 2009Publication date: August 18, 2011Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Julienne Charlier, Serge Palacin, Achraf Ghorbal, Federico Grisotto
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Patent number: 7998875Abstract: A method of treating a nanoporous low-k dielectric material formed on a semiconductor substrate is provided. The low-k dielectric material has etched openings with an etch damaged region containing silanol groups on exterior surfaces of the etched openings and on interior surfaces of interconnected pores. First, the low-k dielectric material is contacted with a vapor phase catalyst in an amount effective to form hydrogen bonds between the catalyst and the silanol groups in the etch damaged region, forming a catalytic intermediary.Type: GrantFiled: December 8, 2008Date of Patent: August 16, 2011Assignee: Lam Research CorporationInventor: James DeYoung
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Patent number: 7994069Abstract: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.Type: GrantFiled: March 31, 2005Date of Patent: August 9, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Brad Smith, Cindy Goldberg, Robert E. Jones
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Patent number: 7994071Abstract: Disclosed are compositions for forming organic insulating films and methods for forming organic insulating films using one or more of the compositions. The compositions include at least one ultraviolet (UV) curing agent, at least one water-soluble polymer and at least one water-soluble fluorine compound, and the method includes applying the composition to a substrate to form a coating layer, irradiating the coating layer with UV light to form an exposed layer and developing the exposed layer with an aqueous developing solution to obtain an organic insulating film and/or pattern. Also disclosed are organic thin film transistors comprising an organic insulating film formed by one of the methods using one of the compositions that may exhibit improved hysteresis performance and/or acceptable surface properties without the need for additional processing, thereby simplifying the fabrication process.Type: GrantFiled: December 4, 2006Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Bon Won Koo, Sang Yoon Lee, Jung Seok Hahn, Joo Young Kim
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Patent number: 7989291Abstract: A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width.Type: GrantFiled: February 25, 2010Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Bruce B. Doris, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Patent number: 7989361Abstract: This invention pertains to a composition for a dielectric thin film, which is capable of being subjected to a low-temperature process. Specifically, the invention is directed to a metal oxide dielectric thin film formed using the composition, a preparation method thereof, a transistor device comprising the dielectric thin film, and an electronic device comprising the transistor device. The electronic device to which the dielectric thin film has been applied exhibits excellent electrical properties, thereby satisfying both a low operating voltage and a high charge mobility.Type: GrantFiled: July 31, 2007Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Baek Seon, Hyun Dam Jeong, Sang Yoon Lee
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Patent number: 7989366Abstract: Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.Type: GrantFiled: August 24, 2007Date of Patent: August 2, 2011Assignee: Applied Materials, Inc.Inventors: Jeffrey C. Munro, Srinivas D. Nemani, Young S. Lee, Marlon Menezes, Christopher Dennis Bencher, Vijay Parihar
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Patent number: 7989271Abstract: A method for fabricating an LCD device is disclosed, in which a reliable thin film pattern is formed as process deviation is minimized. The method includes forming a thin film on a substrate; forming an etch resist solution on the thin film; applying a soft mold having a concave portion and a convex portion to the etch resist solution, wherein the convex portion includes a first width and a second width different than the first width; forming an etch resist pattern having a predetermined linewidth controlled by the pressure applied by the soft mold; hardening the etch resist pattern; separating the soft mold from the substrate; and patterning the thin film using the etch resist pattern as a mask.Type: GrantFiled: October 31, 2007Date of Patent: August 2, 2011Assignee: LG Display Co., Ltd.Inventors: Yeon Heui Nam, Jin Wuk Kim
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Patent number: 7985698Abstract: This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated.Type: GrantFiled: July 5, 2006Date of Patent: July 26, 2011Assignee: Micron Technology, Inc.Inventor: Jon P. Daley
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Patent number: 7985629Abstract: A resin sealing method of a semiconductor device, is provided with: providing a semiconductor device on which a dummy dump is formed; providing a support body including an adhesive layer provided on a surface of the support body; forming a recess in the adhesive layer; inserting the dummy bump of the semiconductor device into the recess of the adhesive layer; adhering the semiconductor device to the adhesive layer with the semiconductor device positioned on the support body; setting the supporting body having the semiconductor device in a resin sealing mold; supplying a resin into a cavity of the resin sealing mold; sealing the semiconductor device with the resin on the support body while using the dummy bump to inhibit displacement of the semiconductor device caused by a flow of the resin supplied into the cavity of the resin sealing mold; and removing the support body, the adhesive layer, and the dummy bump from the semiconductor device sealed with the resin.Type: GrantFiled: December 22, 2009Date of Patent: July 26, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Patent number: 7981706Abstract: A photoresist composition includes an alkali-soluble resin, a dissolution inhibitor including a quinone diazide compound, a first additive including a benzenol compound represented by the following Chemical Formula 1, a second additive including an acrylic copolymer represented by the following Chemical Formula 2 and an organic solvent. Accordingly, heat resistance of a photoresist pattern may be improved, and the photoresist pattern may be readily stripped. As a result, crack formation in the photoresist pattern may be reduced and/or prevented.Type: GrantFiled: September 28, 2010Date of Patent: July 19, 2011Assignees: Samsung Electronics Co., Ltd., Dongwoo Fine-ChemInventors: Jeong-Min Park, Jung-Soo Lee, Won-Young Chang, Eun-Sang Lee, In-Ho Yu, Seong-Hyeon Kim
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Patent number: 7981812Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.Type: GrantFiled: July 3, 2008Date of Patent: July 19, 2011Assignee: Applied Materials, Inc.Inventors: Kang-Lie Chiang, Chia-Ling Kao
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Patent number: 7981810Abstract: The present invention addresses this need by providing a method for forming transparent PECVD deposited ashable hardmasks (AHMs) that have high plasma etch selectivity to underlying layers. Methods of the invention involve depositing the AHM using dilute hydrocarbon precursor gas flows and/or low process temperatures. The AHMs produced are transparent (having absorption coefficients of less than 0.1 in certain embodiments). The AHMs also have the property of high selectivity of the hard mask film to the underlying layers for successful integration of the film, and are suitable for use with 193 nm generation and below lithography schemes wherein high selectivity of the hard mask to the underlying layers is required. The lower temperature process also allows reduction of the overall thermal budget for a wafer.Type: GrantFiled: June 8, 2006Date of Patent: July 19, 2011Assignee: Novellus Systems, Inc.Inventors: Pramod Subramonium, Zhiyuan Fang, Jon Henri
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Patent number: 7977226Abstract: A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates.Type: GrantFiled: December 21, 2009Date of Patent: July 12, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Ki Jun Yun
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Patent number: 7977170Abstract: A method of manufacturing an electronic device (10) provides a substrate (20) that has a plastic material and has a metallic coating on one surface. A portion of the metallic coating is etched to form a patterned metallic coating. A particulate material (16) is embedded in at least one surface of the substrate. A layer of thin-film semiconductor material is deposited onto the substrate (20).Type: GrantFiled: October 3, 2006Date of Patent: July 12, 2011Assignee: Eastman Kodak CompanyInventors: Timothy J. Tredwell, Roger S. Kerr
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Publication number: 20110165772Abstract: Compositions and methods useful for the coating of polymeric materials onto substrates, for example, electronic device substrates such as semiconductor wafers, are provided. These compositions and methods are particularly suitable manipulating thickness of a polymeric coating in a single coating event. Such methods to control photoresist thickness are used to facilitate the layering of electronic circuitry in a three-dimensional fashion. Furthermore, the compositions of the present invention may be effectively used to deposit thick films of polymeric material in a uniform manner onto inorganic substrates which provides a significant benefit over conventional systems.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Applicant: EASTMAN CHEMICAL COMPANYInventors: Michael Wayne Quillen, Loady Palmer Holbrook, Stephanie Ann Roane, Dale Edward O'Dell, John Cleaon Moore
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Publication number: 20110163424Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.Type: ApplicationFiled: March 10, 2011Publication date: July 7, 2011Applicant: Intermolecular, Inc.Inventors: David E. Lazovsky, Tony P. Chiang, Majid Keshavarz
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Patent number: 7972975Abstract: The invention relates to dielectric layers with a low dielectric constant, said layers being used to separate metallic interconnections especially during the production of integrated circuit boards (in the BEOL part of the circuit). According to the invention, the dielectric layer comprises SiC and/or SiOC, and is obtained from at least one precursor comprising at least one —Si—C<SUB>n</SUB>—Si chain where n=1.Type: GrantFiled: June 21, 2006Date of Patent: July 5, 2011Assignee: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges ClaudeInventor: Christian Dussarrat
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Patent number: 7968471Abstract: The present invention provides a process of producing a porous insulating film effective as an insulating film constituting a semiconductor device and a process of producing a porous insulating film having high adhesion to a semiconductor material, which is in contact with the upper and lower interfaces of the insulating film. Gas containing molecule vapor of at least one or more organic silica compounds, which have a cyclic silica skeleton in its molecule and have at least one or more unsaturated hydrocarbon groups bound with the cyclic silica skeleton is introduced into plasma to grow a porous insulating film on a semiconductor substrate.Type: GrantFiled: November 29, 2004Date of Patent: June 28, 2011Assignee: NEC CorporationInventors: Yoshimichi Harada, Yoshihiro Hayashi, Fuminori Itoh, Kenichiro Hijioka, Tsuneo Takeuchi
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Patent number: 7964503Abstract: The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist.Type: GrantFiled: August 21, 2008Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventors: Lucien J. Bissey, William A. Stanton
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Patent number: 7960295Abstract: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.Type: GrantFiled: September 29, 2006Date of Patent: June 14, 2011Assignee: LG Display Co., Ltd.Inventor: Jae Bum Park
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Patent number: 7960291Abstract: The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for example, as masks.Type: GrantFiled: August 28, 2008Date of Patent: June 14, 2011Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Patent number: 7960724Abstract: Provided are a composition for organic thin film transistors including a material including an anthracenyl group and a cross-linker including a maleimide group, an organic thin film transistor formed by using the composition, and a method for manufacturing the same.Type: GrantFiled: August 17, 2009Date of Patent: June 14, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yong-Young Noh, Jae Bon Koo, In-Kyu You, Kang-Jun Baeg, Dong-Yu Kim
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Patent number: 7960290Abstract: A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.Type: GrantFiled: May 2, 2007Date of Patent: June 14, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
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Patent number: 7955990Abstract: Provided herein are improved methods of depositing carbon-based films using acetylene as a precursor. The methods involve using a low-vapor pressure solvent, e.g., dimethylfluoride (DMF) to stabilize the acetylene and delivering the acetylene to a deposition chamber. The methods provide improved wafer-to-wafer thickness uniformity and increase the usable amount of acetylene in an acetylene source to over 95%.Type: GrantFiled: December 12, 2008Date of Patent: June 7, 2011Assignee: Novellus Systems, Inc.Inventors: Jon Henri, Gishun Hsu, Robert Sculac, Scott Stoddard
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Patent number: 7955945Abstract: A process for making a dielectric material where a precursor polymer selected from poly(phenylene vinylene) polyacetylene, poly(p-phenylene), poly(thienylene vinylene), poly(1,4-naphthylene vinylene), and poly(p-pyridine vinylene) is energized said by exposure by radiation or increase in temperature to a level sufficient to eliminate said leaving groups contained within the precursor polymer, thereby transforming the dielectric material into a conductive polymer. The leaving group in the precursor polymer can be a chloride, a bromide, an iodide, a fluoride, an ester, an xanthate, a nitrile, an amine, a nitro group, a carbonate, a dithiocarbamate, a sulfonium group, an oxonium group, an iodonium group, a pyridinium group, an ammonium group, a borate group, a borane group, a sulphinyl group, or a sulfonyl group.Type: GrantFiled: September 28, 2010Date of Patent: June 7, 2011Assignee: Sandia CorporationInventors: Shawn M. Dirk, Ross S. Johnson, David R. Wheeler, Gregory R. Bogart
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Patent number: 7951729Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.Type: GrantFiled: February 12, 2010Date of Patent: May 31, 2011Assignee: NXP B.V.Inventors: Janos Farkas, Srdjan Kordic, Cindy Goldberg
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Patent number: 7951726Abstract: The present invention relates to an organic/inorganic hybrid thin film passivation layer comprising an organic polymer passivation layer prepared by a UV/ozone curing process and an inorganic thin film passivation layer for blocking moisture and oxygen transmission of an organic electronic device fabricated on a substrate and improving gas barrier property of a plastic substrate; and a fabrication method thereof. Since the organic/inorganic hybrid thin film passivation layer of the present invention converts the surface polarity of an organic polymer passivation layer into hydrophilic by using the UV/ozone curing process, it can improve the adhesion strength between the passivation layer interfaces, increase the light transmission rate due to surface planarization of the organic polymer passivation layer, and enhance gas barrier property by effectively blocking moisture and oxygen transmission.Type: GrantFiled: January 27, 2009Date of Patent: May 31, 2011Assignee: Korea Institute of Science and TechnologyInventors: Jai Kyeong Kim, Jung Soo Park, June Whan Choi, Dae-Seok Na, Jae-Hyun Lim, Joo-Won Lee
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Patent number: 7947611Abstract: A method for depositing a low dielectric constant film by flowing a oxidizing gas into a processing chamber, flowing an organosilicon compound from a bulk storage container through a digital liquid flow meter at an organosilicon flow rate to a vaporization injection valve, vaporizing the organosilicon compound and flowing the organosilicon compound and a carrier gas into the processing chamber, maintaining the organosilicon flow rate to deposit an initiation layer, flowing a porogen compound from a bulk storage container through a digital liquid flow meter at a porogen flow rate to a vaporization injection valve, vaporizing the porogen compound and flowing the porogen compound and a carrier gas into the processing chamber, increasing the organosilicon flow rate and the porogen flow rate while depositing a transition layer, and maintaining a second organosilicon flow rate and a second porogen flow rate to deposit a porogen containing organosilicate dielectric layer.Type: GrantFiled: July 9, 2008Date of Patent: May 24, 2011Assignee: Applied Materials, Inc.Inventors: Dustin W. Ho, Juan Carlos Rocha-Alvarez, Alexandros T. Demos, Kelvin Chan, Nagarajan Rajagopalan, Visweswaren Sivaramakrishnan
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Patent number: 7939922Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.Type: GrantFiled: April 20, 2009Date of Patent: May 10, 2011Assignee: Intel CorporationInventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
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Patent number: 7939453Abstract: A method of producing an organic transistor which can form directly an organic semiconductor layer in pattern by simple processes and can produce an organic transistor excellent in transistor characteristics.Type: GrantFiled: February 26, 2009Date of Patent: May 10, 2011Assignees: Dai Nippon Printing Co., Ltd., RikenInventors: Masataka Kano, Kazuhito Tsukagoshi, Takeo Minari
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Publication number: 20110101507Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.Type: ApplicationFiled: November 2, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hakeem Akinmade Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
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Patent number: 7932188Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same. In one aspect of the present invention, an organosilicate glass film is exposed to an ultraviolet light source wherein the film after exposure has an at least 10% or greater improvement in its mechanical properties (i.e., material hardness and elastic modulus) compared to the as-deposited film.Type: GrantFiled: October 31, 2008Date of Patent: April 26, 2011Assignee: Air Products and Chemicals, Inc.Inventors: Aaron Scott Lukas, Mark Leonard O'Neill, Jean Louise Vincent, Raymond Nicholas Vrtis, Mark Daniel Bitner, Eugene Joseph Karwacki, Jr.
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Publication number: 20110076797Abstract: A method for producing at least one pattern on a top surface of a support made from a material presenting a first thermal conductivity comprises a step of arranging of a mask made from a material presenting a second thermal conductivity and comprising at least one recess having a shape corresponding to that of the pattern, in contact with a bottom surface of the support, the ratio of the first conductivity over the second conductivity being greater than or equal to 2, or smaller than or equal to ½, throughout the duration of the method. The method further comprises a step of depositing on the top surface a solution comprising a material designed to form the pattern, and a step of evaporating the solution.Type: ApplicationFiled: September 10, 2010Publication date: March 31, 2011Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Mohamed BENWADIH
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Publication number: 20110076858Abstract: The invention provides methods for depositing a coating onto the entire backside of a semiconductor wafer. The methods of the invention address the deficiencies typically associated with deposition of coatings onto the backside of semiconductor wafers. Since the methods of the invention result in wafers wherein a coating has been dispensed all the way to the edge of the wafer, there is minimal chip flying during dicing, and minimal wafer breakage and chip breakage. In addition, the methods of the invention result in a marked decrease in waste when compared to traditional spin coating methods.Type: ApplicationFiled: December 9, 2010Publication date: March 31, 2011Inventor: Hoseung Yoo
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Patent number: 7915181Abstract: Methods of repairing voids in a material are described herein that include: a) providing a material having a plurality of reactive silanol groups; b) providing at least one reactive surface modification agent; and c) chemically capping at least some of the plurality of reactive silanol groups with the at least one of the reactive surface modification agents. Methods of carbon restoration in a material are also described that include: a) providing a carbon-deficient material having a plurality of reactive silanol groups; b) providing at least one reactive surface modification agent; and c)chemically capping at least some of the plurality of reactive silanol groups with the at least one of the reactive surface modification agents.Type: GrantFiled: January 26, 2004Date of Patent: March 29, 2011Assignee: Honeywell International Inc.Inventors: Wenya Fan, Victor Lu, Michael Thomas, Brian Daniels, Tiffany Nguyen, De-Ling Zhou, Ananth Naman, Lei Jin, Anil Bhanap
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Patent number: 7915166Abstract: Films having high hermeticity and a low dielectric constant can be used as copper diffusion barrier films, etch stop films, CMP stop films and other hardmasks during IC fabrication. Hermetic films can protect the underlying layers, such as layers of metal and dielectric, from exposure to atmospheric moisture and oxygen, thereby preventing undesirable oxidation of metal surfaces and absorption of moisture by a dielectric. Specifically, a bi-layer film having a hermetic bottom layer composed of hydrogen doped carbon and a low dielectric constant (low-k) top layer composed of low-k silicon carbide (e.g., high carbon content hydrogen doped silicon carbide) can be employed. Such bi-layer film can be deposited by PECVD methods on a partially fabricated semiconductor substrate having exposed layers of dielectric and metal.Type: GrantFiled: February 22, 2007Date of Patent: March 29, 2011Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Pramod Subramonium, Zhiyuan Fang, Jon Henri, Elizabeth Apen, Dan Vitkavage
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Patent number: 7915180Abstract: A method of fabricating a dielectric material that has an ultra low dielectric constant (or ultra low k) using at least one organosilicon precursor is described. The organosilicon precursor employed in the present invention includes a molecule containing both an Si—O structure and a sacrificial organic group, as a leaving group. The use of an organosilicon precursor containing a molecular scale sacrificial leaving group enables control of the pore size at the nanometer scale, control of the compositional and structural uniformity and simplifies the manufacturing process. Moreover, fabrication of a dielectric film from a single precursor enables better control of the final porosity in the film and a narrower pore size distribution resulting in better mechanical properties at the same value of dielectric constant.Type: GrantFiled: April 17, 2009Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Stephen M. Gates, Alfred Grill, Robert D. Miller, Deborah A. Neumayer, Son Nguyen