Tertiary Silicon Containing Compound Formation (e.g., Oxynitride Formation, Etc.) Patents (Class 438/786)
  • Publication number: 20120164846
    Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Applicant: ASM JAPAN K.K.
    Inventors: Jeongseok Ha, Hideaki Fukuda, Shintaro Kaido
  • Publication number: 20120156894
    Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.
    Type: Application
    Filed: February 9, 2012
    Publication date: June 21, 2012
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum
  • Publication number: 20120156895
    Abstract: A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6×10?-11 to about 8×10?-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.
    Type: Application
    Filed: June 28, 2010
    Publication date: June 21, 2012
    Applicant: CORNELL UNIVERSITY
    Inventors: James R. Shealy, Richard Brown
  • Patent number: 8198731
    Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: June 12, 2012
    Assignee: Aptina Imaging Corporation
    Inventor: Mattia Cichocki
  • Patent number: 8187973
    Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Kazuhei Yoshinaga
  • Publication number: 20120100727
    Abstract: A method of manufacturing a semiconductor device includes steps of: generating positively or negatively charged fine bubbles having substantially zero buoyancy in a coating solution as an insulating film forming material; coating the coating solution including the bubbles on a substrate to form a coating film; and baking the coating film by heating the substrate before the bubbles are removed to obtain a porous low dielectric constant insulating film.
    Type: Application
    Filed: August 5, 2008
    Publication date: April 26, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Sumie Nagaseki
  • Patent number: 8163660
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 24, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Helmut Puchner, Igor Polishchuk, Sagy Levy
  • Patent number: 8158535
    Abstract: A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface, a step of performing oxidizing to the silicon on the surface, and forming a silicon oxide thin film on the surface of the silicon, a step of performing first nitriding to the silicon oxide film and the base silicon thereof, and forming a silicon oxynitride film, and a step of performing first heat treatment to the silicon oxynitride film in N2O atmosphere. In such method, a step of performing second nitriding to the silicon oxynitride film may be further included after the first heat treatment, and furthermore, a step of performing second heat treatment to the silicon oxynitride film after the second nitriding may be included.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 17, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
  • Publication number: 20120083117
    Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: April 5, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Ahn, Byung-Hee Kim, Sang-Don Nam, Kyu-Hee Han, Gil-Heyun Choi, Jang-Hee Lee, Jong-Min Baek, Kyoung-Hee Kim
  • Publication number: 20120071005
    Abstract: A heat treating apparatus, which performs a specified heat treatment on a target object, includes a processing chamber accommodating therein the target object; a mounting table for mounting thereon the target object; a vacuum exhaust system for vacuum evacuating the processing chamber; an electromagnetic wave supply unit for irradiating an electromagnetic wave onto the target object to heat the target object; and a controller for controlling the heat treating apparatus such that the electromagnetic wave is irradiated onto the target object at a high vacuum level at which plasma is not generated. Further, a heat treating method performs a specified heat treatment on a target object, wherein the target object is accommodated in a processing chamber capable of being vacuum evacuated, and the target object is heated by irradiating an electromagnetic wave thereon at a high vacuum level at which plasma is not generated in the processing chamber.
    Type: Application
    Filed: November 28, 2011
    Publication date: March 22, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Masahiro SHIMIZU
  • Publication number: 20120045905
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying at least two types of source gases into the process vessel, each of the at least two types of source gases containing the element, and (b) changing the layer containing the element by supplying reaction gas into the process vessel, the reaction gas being different from the at least two types of source gases; and unloading the processed substrate from the process vessel.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Inventors: Naonori AKAE, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
  • Publication number: 20120045904
    Abstract: Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF4, SiCl4, Si2Cl6, and forming a hydrogen free silicon containing layer on the substrate in the presence of the gas mixture.
    Type: Application
    Filed: August 20, 2011
    Publication date: February 23, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Soo Young Choi
  • Patent number: 8119483
    Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Patent number: 8110469
    Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: February 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dan Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
  • Publication number: 20110312191
    Abstract: A semiconductor device manufacturing method includes forming an insulation film containing silicon, oxygen and carbon over a semiconductor substrate by chemical vapor deposition; making UV cure on the insulation film being heated at a temperature of 350° C. or below after the forming the insulation film; and making helium plasma processing on the insulation film after the UV cure.
    Type: Application
    Filed: March 24, 2011
    Publication date: December 22, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yoshiyuki Ohkura, Toshiki Mori
  • Patent number: 8076251
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an oxide, nitride, or oxynitride film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying and exhausting first and second source gases containing the element into and from the process vessel; and (b) changing the layer containing the element into an oxide, nitride, or oxynitride layer by supplying and exhausting reaction gas different from the first and second source gases into and from the process vessel; and unloading the substrate from the process vessel. The first source gas is more reactive than the second source gas, and an amount of the first source gas supplied into the process vessel is set to be less than that of the second source gas supplied into the process vessel.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 13, 2011
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
  • Patent number: 8043980
    Abstract: The invention provides compounds of, and methods for the preparation of compounds of, the molecular formula, SixGeyHz—aXa; wherein X is halogen, and x, y, z, and a are defined herein, and methods for the deposition of high-Ge content Si films on silicon substrates using compounds of the invention.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: October 25, 2011
    Assignee: Arizona Board of Regents, A Body Corporate Acting for and on Behalf of Arizona State University
    Inventors: John Kouvetakis, Jesse Tice, Yan-Yan Fang
  • Patent number: 8039404
    Abstract: A production method for a semiconductor device comprising the first step of supplying a first reaction material to a substrate housed in a processing chamber to subject to a ligand substitution reaction a ligand as a reaction site existing on the surface of the substrate and the ligand of the first reaction material, the second step of removing the excessive first reaction material from the processing chamber, the third step of supplying a second reaction material to the substrate to subject a ligand substituted by the first step to a ligand substitution reaction with respect to a reaction site, the fourth step of removing the excessive second reaction material from the processing chamber, and a fifth step of supplying a third reaction material excited by plasma to the substrate to subject a ligand, not subjected to a substitution reaction with respect to a reaction site in the third step, to a ligand substitution reaction with respect to a reaction site, wherein the steps 1-5 are repeated a specified number
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 18, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Hironobu Miya, Kazuyuki Toyoda, Norikazu Mizuno, Taketoshi Sato, Masanori Sakai, Masayuki Asai, Kazuyuki Okuda, Hideki Horita
  • Patent number: 8039402
    Abstract: There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: October 18, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Patent number: 8030198
    Abstract: A semiconductor device includes a silicon substrate, an SiO film, and a High-K film. The SiO film is first formed on the silicon substrate and then subjected to a nitridation process to obtain an SiON film from the SiO film. The nitridation process is performed such that nitrogen concentration in the SiO film decreases from an interface with the silicon substrate below and an interface with the High-K film above, and nitrogen having predetermined concentration or more is introduced in a thickness within a range of 0.2 nm to 1 nm from the interface with the silicon substrate. The SiON film is etched up to a depth to which nitrogen of the predetermined concentration or more is introduced. The High-K film is then formed on the SiON film.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Shimizu
  • Patent number: 8021988
    Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kouichi Muraoka
  • Publication number: 20110217851
    Abstract: Methods, materials, and systems are described for forming conformal dielectric layers containing silicon and nitrogen (e.g., a silicon-nitrogen-hydrogen (Si—N—H) film) from a carbon-free silicon-and-nitrogen precursor and radical-nitrogen precursor. The carbon-free silicon-and-nitrogen precursor is predominantly excited by contact with the radical-nitrogen precursor. Because the silicon-and-nitrogen film is formed without carbon, the conversion of the film into hardened silicon oxide is done with less pore formation and less volume shrinkage. The deposited silicon-and-nitrogen-containing film may be wholly or partially converted to silicon oxide which allows the optical properties of the conformal dielectric layer to be selectable. The deposition of a thin silicon-and-nitrogen-containing film may be performed at low temperature to form a liner layer in a substrate trench.
    Type: Application
    Filed: February 10, 2011
    Publication date: September 8, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Jingmei Liang, Xiaolin Chen, DongQing Li, Nitin K. Ingle
  • Patent number: 8003549
    Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch of features such as vias in subsequent processing steps.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: August 23, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Ming Li, Bart Van Schravendijk, Tom Mountsier, Chiu Chi, Kevin Ilcisin, Julian Hsieh
  • Publication number: 20110195582
    Abstract: A method of producing silicon containing thin films by the thermal polymerization of a reactive gas mixture bisaminosilacyclobutane and source gas selected from a nitrogen providing gas, an oxygen providing gas and mixtures thereof. The films deposited may be silicon nitride, silicon carbonitride, silicon dioxide or carbon doped silicon dioxide. These films are useful as dielectrics, passivation coatings, barrier coatings, spacers, liners and/or stressors in semiconductor devices.
    Type: Application
    Filed: August 11, 2009
    Publication date: August 11, 2011
    Inventor: Xiaobing Zhou
  • Patent number: 7994019
    Abstract: Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: August 9, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Sasha Kweskin, Paul Edward Gee, Shankar Venkataraman, Kedar Sapre
  • Publication number: 20110189862
    Abstract: Provided is a process of forming a silicon oxynitride film having concentration of hydrogen atoms below or equal to 9.9×1020 atoms/cm3 as measured by using secondary ion mass spectrometry (SIMS), using a plasma CVD device, which generates plasma by introducing microwaves into a process chamber by using a planar antenna having a plurality of apertures, by setting a pressure inside the process chamber within a range from 0.1 Pa to 6.7 Pa, and performing plasma CVD by using process gases including SiCl4 gas, nitrogen gas, and oxygen gas.
    Type: Application
    Filed: September 29, 2009
    Publication date: August 4, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Minoru Honda, Tatsuo Nishita, Junya Miyahara, Masayuki Kohno
  • Publication number: 20110189860
    Abstract: Methods of nitridation and selective oxidation are provided herein. In some embodiments, a method of nitridation includes providing a substrate having a first layer disposed thereon, where the substrate is disposed on a substrate support in a process chamber; forming a remote plasma from a process gas comprising nitrogen; and exposing the first layer to a reactive species formed from the remote plasma to form a nitrogen-containing layer, wherein a density of the reactive species is about 109 to about 1017 molecules/cm3 and wherein a pressure in the chamber during exposure of the first layer is about 5 mTorr to about 3 Torr. In some embodiments, the nitrogen-containing layer is a gate dielectric layer for use in a semiconductor device.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 4, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventor: PETER PORSHNEV
  • Patent number: 7972977
    Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: July 5, 2011
    Assignee: ASM America, Inc.
    Inventors: Chang-Gong Wang, Eric Shero, Glen Wilk
  • Publication number: 20110151678
    Abstract: Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 23, 2011
    Inventors: Kaihan Ashtiani, Michael Wood, John Drewery, Naohiro Shoda, Bart van Schravendijk, Lakshminarayana Nittala, Nerissa Draeger
  • Publication number: 20110143554
    Abstract: Methods for reducing defects on the surface of a silicon oxynitride film are disclosed, in one embodiment, the methods include, forming a silicon oxynitride film on a semiconductor substrate and heating the silicon oxynitride film to increase a hydrophilicity of a surface of the silicon oxynitride film prior to treating the surface of the silicon oxynitride film with a hydrofluoric acid.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 16, 2011
    Inventor: Noriyuki YOKONAGA
  • Patent number: 7955994
    Abstract: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Noriyoshi Suzuki
  • Patent number: 7942965
    Abstract: A method of fabricating silicon parts are provided herein. The method includes growing a silicon sample, machining the sample to form a part, and annealing the part by exposing the part sequentially to one or more gases. Process conditions during silicon growth and post-machining anneal are designed to provide silicon parts that are particularly suited for use in corrosive environments.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: May 17, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Elmira Ryabova, Jie Yuan, Jennifer Sun
  • Patent number: 7923378
    Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa
  • Patent number: 7923336
    Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: April 12, 2011
    Assignee: Infineon Technologies AG
    Inventors: Kil-Ho Lee, Chan Lim
  • Patent number: 7915126
    Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Patent number: 7910419
    Abstract: A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: March 22, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Claire Fenouillet-Beranger, Philippe Coronel
  • Patent number: 7902027
    Abstract: A semiconductor device includes a recessed-channel-array MOSFET including a gate electrode having a portion received in a recess. The gate insulting film has a first portion made of silicon oxide in contact with the sidewall of the recess and a second portion made of silicon oxynitride in contact with the bottom of the recess. The first portion has an equivalent oxide thickness larger than the equivalent oxide thickness of the second portion to reduce the parasitic capacitance of the gate electrode.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: March 8, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Hirohisa Yamamoto
  • Patent number: 7902088
    Abstract: A method is provided for fabricating a high quantum efficiency silicon (Si) nanoparticle embedded SiOXNY film for luminescence (electroluminescence—EL and photoluminescence—PL) applications. The method provides a bottom electrode, and deposits a Si nanoparticle embedded non-stoichiometric SiOXNY film, where (X+Y<2 and Y>0), overlying the bottom electrode. The Si nanoparticle embedded SiOXNY film is annealed. The annealed Si nanoparticle embedded SiOXNY film has an extinction coefficient (k) of less than about 0.001 as measured at 632 nanometers (nm), and a PL quantum efficiency (PLQE) of greater than 20%.
    Type: Grant
    Filed: October 11, 2008
    Date of Patent: March 8, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, Jiandong Huang, Apostolos T. Voutsas
  • Patent number: 7892917
    Abstract: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor and/or the transistor are provided. The bismuth titanium silicon oxide has good dielectric properties and is thermally and chemically stable. The bismuth-titanium-silicon oxide thin film can be effectively used as a dielectric film of a capacitor or as a gate dielectric film of a transistor in a semiconductor device. Various electronic devices having good electrical properties can be manufactured using the capacitor and/or the transistor having the bismuth-titanium-silicon oxide film.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: February 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Cho, Yo-sep Min, Young-soo Park, Jung-hyun Lee, June-key Lee, Yong-kyun Lee
  • Patent number: 7888269
    Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: February 15, 2011
    Assignees: Spansion LLC, GlobalFoundries, Inc.
    Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher H. Raeder, Christopher Foster, Weidong Qian, Minh Van Ngo
  • Patent number: 7871942
    Abstract: Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: January 18, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Shreyas S. Kher, Pravin K. Narwankar, Khaled Z. Ahmed, Yi Ma
  • Publication number: 20100323531
    Abstract: A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface, a step of performing oxidizing to the silicon on the surface, and forming a silicon oxide thin film on the surface of the silicon, a step of performing first nitriding to the silicon oxide film and the base silicon thereof, and forming a silicon oxynitride film, and a step of performing first heat treatment to the silicon oxynitride film in N2O atmosphere. In such method, a step of performing second nitriding to the silicon oxynitride film may be further included after the first heat treatment, and furthermore, a step of performing second heat treatment to the silicon oxynitride film after the second nitriding may be included.
    Type: Application
    Filed: December 20, 2007
    Publication date: December 23, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
  • Patent number: 7855153
    Abstract: A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into a chamber to generate high-density plasma at a pressure higher than or equal to 10 Pa and lower than or equal to 30 Pa so that an insulating film is formed over a substrate having an insulating surface. After that, the supply of a monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas are introduced without exposure to the air to perform plasma treatment on a surface of the insulating film.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: December 21, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Kenichi Okazaki, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Shunpei Yamazaki
  • Patent number: 7842621
    Abstract: The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2?T2N)/(T2?T1N)}×100 (1).
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: November 30, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Jiro Katsuki, Tetsuro Takahashi, Shuuichi Ishizuka
  • Patent number: 7833914
    Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: November 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes, Arup Bhattacharyya
  • Patent number: 7824991
    Abstract: A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: November 2, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Shih-Chin Lee
  • Patent number: 7816283
    Abstract: A method of depositing a high permittivity dielectric film on a doped silicon or silicon compound layer of a wafer. The method includes a first step of nitriding a specific element (A) such as hafnium Hf to form a nitride film (AxNy) on the silicon layer, wherein the specific element (A) and nitrogen (N) in the nitride film (AxNy) have a predetermined fraction relationship between x and y; a second step of oxidizing the nitride film in a oxygen atmosphere to form the dielectric film (AON).
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 19, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Sunil Wickramanayaka, Naoki Yamada
  • Patent number: 7811947
    Abstract: The present invention relates to an optical substrate comprising a transparent substrate, a low refractive index layer, whose refractive index is lower than that of the transparent substrate, disposed over the transparent substrate, and a solgel film disposed over the low refractive index layer; a light emitting element having a first electrode, a light emitting layer and a second electrode over the solgel film of this optical substrate; and a display device provided with this light emitting element.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: October 12, 2010
    Assignee: NEC Corporation
    Inventors: Koji Shigemura, Tomohisa Gotoh, Hironori Imura
  • Publication number: 20100248497
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas comprising nitrogen while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer. In some embodiments, the process gas includes ammonia (NH3).
    Type: Application
    Filed: March 29, 2010
    Publication date: September 30, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Malcolm J. BEVAN, Johanes SWENBERG, Son T. NGUYEN, Wei LIU, Jose Antonio MARIN, Jian LI
  • Patent number: 7803678
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: September 28, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Kevin L. Beaman, John T. Moore