Organic Reactant Patents (Class 438/790)
  • Patent number: 11764149
    Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: September 19, 2023
    Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
  • Patent number: 11424182
    Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 23, 2022
    Inventors: Suhyun Bark, Kyeongbeom Park, Jongmin Baek, Jangho Lee, Wookyung You, Deokyoung Jung
  • Patent number: 11359283
    Abstract: A substrate processing apparatus includes a reaction tube defining a substrate processing chamber; a gas inlet provided at a lower portion of the reaction tube to supply a process gas; a first buffer unit for temporarily retaining the process gas, the first buffer unit at a first side of an inner surface of the reaction tube and includes a plurality of gas supply holes; and a gas outlet provided at a second side of the inner surface of the reaction tube opposite to the first side, to exhaust the process gas from the process chamber. The gas supply holes are provided from an upper end portion of the first buffer unit to a lower end portion of the first buffer unit, and the process gas is supplied through the plurality of gas supply holes into the process chamber, passes through the process chamber, and exhausted through the gas outlet.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 14, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Tetsuya Marubayashi, Satoru Murata, Kosuke Takagi, Atsushi Hirano, Kiyoaki Yamada, Haruo Morikawa
  • Patent number: 10790142
    Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Chi, Hsiao-Kuan Wei, Hung-Wen Su, Pei-Hsuan Lee, Hsin-Yun Hsu, Jui-Fen Chien
  • Patent number: 10732512
    Abstract: An image processor, a method for generating a pattern using self-organizing lithographic techniques, and a computer program are provided to achieve image processing suitable for addressing a sample generated by patterning using Directed Self-Assembly (DSA), and the processor, method, and computer program are characterized in that a template for addressing is prepared on the basis of guide pattern data used for patterning by DSA. The above configuration makes it possible to provide an addressing pattern suitable for visual field positioning in measuring or inspecting a pattern formed through the patterning process using DSA.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 4, 2020
    Assignee: Hitachi High-Tech Corporation
    Inventors: Takumichi Sutani, Miki Isawa, Shunsuke Koshihara, Akiyuki Sugiyama
  • Patent number: 10226821
    Abstract: An apparatus and a method for producing fine particles capable of increasing the production and producing fine particles at low costs by feeding a large quantity of material efficiently into the plasma. The apparatus includes a vacuum chamber, a material feeding device connected to the vacuum chamber and feeding material particles into the vacuum chamber from material feeing ports, a plurality of electrodes connected to the vacuum chamber, tip ends of which protrude into the vacuum chamber to generate plasma and a collecting device connected to the vacuum chamber and collecting fine particles, which generates discharge inside the vacuum chamber and produces the fine particles from the material, in which the material feeding ports of the material feeding device are arranged in a lower side than the plural electrodes in the vertical direction in the vacuum chamber.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: March 12, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hisao Nagai, Takafumi Okuma
  • Patent number: 9803281
    Abstract: Described herein is an apparatus and nozzle head for coating a surface of a substrate. The apparatus comprising a process chamber having inside a gas atmosphere, a nozzle head arranged inside the process chamber, precursor supply and discharge means. The nozzle head including one or more first precursor nozzles for subjecting the surface of the substrate to the first precursor, one or more second precursor nozzles for subjecting the surface of the substrate to the second precursor and one or more purge gas channels between the first and second precursor zones. In certain aspects, the purge gas channel is at least partly open to the gas atmosphere comprising purge gas for subjecting the surface of the substrate to purge gas.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: October 31, 2017
    Assignee: BENEQ Oy
    Inventors: Pekka Soininen, Olli Pekonen
  • Patent number: 9412582
    Abstract: A structure for constituting a process chamber in which a plurality of substrates is processed by reacting a predetermined precursor gas therein includes an outer tube having a cylindrical shape with an upper end portion closed and a lower end portion opened, and an inner tube, installed within the outer tube, including a first exhaust slit and a second exhaust slit through which the predetermined precursor gas is exhausted, the first exhaust slit located in a substrate arrangement region in which the plurality of substrates are arranged, and the second exhaust slit located in a region lower than the substrate arrangement region.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: August 9, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takafumi Sasaki, Kazuhiro Morimitsu, Eisuke Nishitani, Tetsuo Yamamoto, Masanao Fukuda
  • Patent number: 9165974
    Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: October 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-kwan Kim, Doo-won Kwon, Jeong-ki Kim, Wook-hwan Kim, Byung-jun Park, Seung-hun Shin, June-taeg Lee, Ha-kyu Choi, Tae-seok Oh
  • Publication number: 20150147871
    Abstract: Described herein are precursors and methods for forming silicon-containing films.
    Type: Application
    Filed: June 2, 2014
    Publication date: May 28, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Manchao Xiao, Xinjian Lei, Daniel P. Spence
  • Patent number: 9034675
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 9034760
    Abstract: Methods, apparatus, and systems for depositing tensile or compressive tungsten films are described. In one aspect, a method includes providing a substrate to a chamber. The substrate has a field region and a feature recessed from the field region. Then, the substrate is exposed to an organometallic tungsten precursor. The organometallic tungsten precursor not adsorbed onto the substrate is removed from the chamber. The substrate is treated with a first treatment including a heat treatment or a plasma treatment to form a tungsten layer on the substrate. After treating the substrate, residual gasses are removed from the chamber. The tungsten layer on the substrate is treated with a second treatment including a heat treatment or a plasma treatment.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Roey Shaviv, Raashina Humayun, Deqi Wang
  • Patent number: 9029273
    Abstract: A method for forming a silicon oxide film of a semiconductor device is disclosed. The method of forming the silicon oxide film of the semiconductor device includes performing surface processing using an amine-based compound, so that the uniformity and density of the silicon oxide film may be improved.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 12, 2015
    Assignees: SK Hynix Inc.
    Inventors: Hyung Soon Park, Kwon Hong, Jong Min Lee, Hyung Hwan Kim, Ji Hye Han, Geun Su Lee
  • Patent number: 9029171
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Publication number: 20150126044
    Abstract: A substrate processing apparatus includes a vacuum chamber including a top plate, a rotary table rotatably disposed in the vacuum chamber, a first process gas supply part that supplies a first process gas to be adsorbed on a surface of a substrate placed on the rotary table, a plasma processing gas supply part that is disposed apart from the first process gas supply part in a circumferential direction of the rotary table and supplies a second process gas to the surface of the substrate, a separation gas supply part that supplies a separation gas for separating the first process gas and the second process gas, a plasma generator that converts the second process gas into plasma, and an elevating mechanism that moves at least one of the plasma generator and the rotary table upward and downward.
    Type: Application
    Filed: October 24, 2014
    Publication date: May 7, 2015
    Inventors: Hitoshi KATO, Hiroyuki KIKUCHI, Masato YONEZAWA, Jun SATO, Shigehiro MIURA
  • Publication number: 20150087139
    Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, the precursor comprises a compound represented by one of following Formulae A through E below: In one particular embodiment, the organoaminosilane precursors are effective for a low temperature (e.g., 350° C. or less), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) of a silicon-containing film. In addition, described herein is a composition comprising an organoaminosilane described herein wherein the organoaminosilane is substantially free of at least one selected from the amines, halides (e.g., Cl, F, I, Br), higher molecular weight species, and trace metals.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 26, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Mark Leonard O'Neill, Manchao Xiao, Xinjian Lei, Richard Ho, Haripin Chandra, Matthew R. MacDonald, Meiliang Wang
  • Patent number: 8975196
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes providing a substrate, supplying a first liquid including a terpene to a surface of the substrate, supplying a second liquid including a silicon-containing compound to the surface of the substrate, and converting the silicon-containing compound to a silicon oxide compound.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 8969219
    Abstract: The present invention relates to a method for preparation of an ultraviolet (UV)-curable inorganic-organic hybrid resin containing about or less than 4% volatiles and less than 30% organic residues. The UV-curable inorganic-organic hybrid resin obtained according to this method can be UV-cured within a markedly very short time and enables, upon curing, the formation of a transparent shrink-and crack-free glass-like product having high optical quality, high thermal stability and good bonding properties. In view of these properties, this hybrid resin can be used in various applications such as electro-optic, microelectronic, stereolithography and biophotonic applications.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: March 3, 2015
    Assignee: Soreq Nuclear Research Center
    Inventor: Raz Gvishi
  • Publication number: 20150056822
    Abstract: Described herein are compositions or formulations for forming a film in a semiconductor deposition process, such as without limitation, a flowable chemical vapor deposition of silicon oxide. Also described herein is a method to improve the surface wetting by incorporating an acetylenic alcohol or diol surfactant such as without limitation 3,5-dimethyl-1-hexyn-3-ol, 2,4,7,9-tetramethyl-5-decyn-4,7-diol, 4-ethyl-1-octyn-3-ol, and 2,5-dimethylhexan-2,5-diol, and other related compounds.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 26, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Ronald Martin Pearlstein, Daniel P. Spence
  • Publication number: 20150044883
    Abstract: A composition for forming a silica-based insulation layer, a silica-based insulation layer, and a method of manufacturing the silica-based insulation layer, the composition including a solvent; and an organosilane-based condensation polymerization product that includes a structural unit represented by the following Chemical Formula 1:
    Type: Application
    Filed: April 23, 2014
    Publication date: February 12, 2015
    Inventors: Eun-Su PARK, Taek-Soo KWAK, Yoong-Hee NA, Hyun-Ji SONG, Han-Song LEE, Seung-Hee HONG
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20150024608
    Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, there is provided a precursor of Formula I: wherein R1 is selected from linear or branched C3 to C10 alkyl group, linear or branched C3 to C10 alkenyl group, linear or branched C3 to C10 alkynyl group, C1 to C6 dialkylamino group, electron withdrawing group, and C6 to C10 aryl group; R2 is selected from hydrogen, linear or branched C1 to C10 alkyl group, linear or branched C3 to C6 alkenyl group, linear or branched C3 to C6 alkynyl group, C1 to C6 dialkylamino group, C6 to C10 aryl group, linear or branched C1 to C6 fluorinated alkyl group, electron withdrawing group, and C4 to C10 aryl group; optionally wherein R1 and R2 are linked together to form ring selected from substituted or unsubstituted aromatic ring or substituted or unsubstituted aliphatic ring; and n=1 or 2.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 22, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Steven Gerard Mayorga, Heather Regina Bowen, Xinjian Lei, Manchao Xiao, Haripin Chandra, Anupama Mallikarjunan, Ronald Martin Pearlstein
  • Publication number: 20140363985
    Abstract: Provided are a novel amino-silyl amine compound, a method for preparing the same, and a silicon-containing thin-film using the same, wherein the amino-silyl amine compound has thermal stability and high volatility and is maintained in a liquid state at room temperature and under a pressure where handling is easy to thereby form a silicon-containing thin-film having high purity and excellent physical and electrical properties by various deposition methods.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Inventors: Se Jin Jang, Sang Do Lee, Sung Gi Kim, Jong Hyun Kim, Byeong IL Yang, Jang Hyeon Seok, Sang Ick Lee, Myong Woon Kim
  • Patent number: 8895322
    Abstract: A ferroelectric capacitor provided with a ferroelectric film (10a) is formed above a semiconductor substrate, and thereafter a wiring (17) directly connected to electrodes (9a, 11a) of a ferroelectric capacitor is formed. Then, a silicon oxide film (18) covering the wiring (17) is formed. As the silicon oxide film (18), a film which has processability higher than that of an aluminum oxide film is formed. Besides, a degree of damage that occurs in the ferroelectric capacitor when the insulating film is formed is equal to or less than that when an aluminum oxide film is formed.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • Patent number: 8846507
    Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: September 30, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Dmitry Karshtedt, Joerg Rockenberger, Fabio Zurcher, Brent Ridley, Erik Scher
  • Patent number: 8835332
    Abstract: A film deposition method, in which a film of a reaction product of a first reaction gas, which tends to be adsorbed onto hydroxyl radicals, and a second reaction gas capable of reacting with the first reaction gas is formed on a substrate provided with a concave portion, includes a step of controlling an adsorption distribution of the hydroxyl radicals in a depth direction in the concave portion of the substrate; a step of supplying the first reaction gas on the substrate onto which the hydroxyl radicals are adsorbed; and a step of supplying the second reaction gas on the substrate onto which the first reaction gas is adsorbed.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: September 16, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Tatsuya Tamura, Takeshi Kumagai
  • Patent number: 8822350
    Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 2, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Yuasa, Ryuji Yamamoto
  • Patent number: 8822301
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 2, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Arvind Kamath, Erik Scher, Patrick Smith, Aditi Chandra, Steven Molesa
  • Patent number: 8772172
    Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 8, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Patent number: 8772182
    Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshiyuki Ohkura
  • Patent number: 8759131
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 8716154
    Abstract: Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 6, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sidharth Bhatia, Paul Edward Gee, Shankar Venkataraman
  • Patent number: 8703624
    Abstract: Described herein are methods of forming dielectric films comprising silicon, such as, but not limited to, silicon oxide, silicon oxycarbide, silicon carbide, and combinations thereof, that exhibit at least one of the following characteristics: low wet etch resistance, a dielectric constant of 6.0 or below, and/or can withstand a high temperature rapid thermal anneal process. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: April 22, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Liu Yang, Manchao Xiao, Kirk Scott Cuthill, Bing Han, Mark Leonard O'Neill
  • Publication number: 20140087568
    Abstract: A method of cleaning an interior of a process chamber by supplying a cleaning gas into the process chamber after a process of forming a thin film on a substrate in the process chamber is performed, including alternately repeating changing a pressure in the process chamber from a first pressure range to a second pressure range, and changing the pressure in the process chamber from the second pressure range to the first pressure range. In this method, when the pressure in the process chamber is changed to the first pressure range, the pressure in the process chamber is changed to the first pressure range without being maintained at the second pressure range, and when the pressure in the process chamber is changed to the second pressure range, the pressure in the process chamber is changed to the second pressure range without being maintained at the first pressure range.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 27, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takaaki NODA, Masatoshi TAKADA
  • Publication number: 20140057458
    Abstract: A method for forming a silicon oxide film of a semiconductor device is disclosed. The method of forming the silicon oxide film of the semiconductor device includes performing surface processing using an amine-based compound, so that the uniformity and density of the silicon oxide film may be improved.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 27, 2014
    Applicant: SK HYNIX INC.
    Inventors: Hyung Soon PARK, Kwon HONG, Jong Min LEE, Hyung Hwan KIM, Ji Hye HAN, Geun Su LEE
  • Publication number: 20130330937
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2), chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 12, 2013
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Patent number: 8597429
    Abstract: Provided is a semiconductor manufacturing apparatus including: a reaction chamber including a gas supply inlet and a gas exhaust outlet, and into which a wafer is to be introduced; a process gas supply mechanism that supplies process gas into the reaction chamber from the gas supply inlet of the reaction chamber; a wafer retaining member that is arranged in the reaction chamber and that retains the wafer; a heater that heats the wafer retained by the wafer retaining member to a predetermined temperature; a rotation drive control mechanism that rotates the wafer retaining member together with the wafer; a gas exhaustion mechanism that exhausts gas in the reaction chamber from the gas exhaust outlet of the reaction chamber; and a drain that is disposed at a bottom portion near a wall surface in the reaction chamber and that collects and discharges oily silane that drips from the wall surface.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: December 3, 2013
    Assignee: NuFlare Technology, Inc.
    Inventors: Kunihiko Suzuki, Hironobu Hirata
  • Publication number: 20130299952
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 14, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Hironori YAMAMOTO, Fuminori ITO, Yoshihiro HAYASHI
  • Publication number: 20130295779
    Abstract: Composition(s) and atomic layer deposition (ALD) process(es) for the formation of a silicon oxide containing film at one or more deposition temperature of about 500° C. is disclosed. In one aspect, the composition and process use one or more silicon precursors selected from compounds having the following formulae I, II, described and combinations thereof R1R2mSi(NR3R4)nXp; and??I. R1R2mSi(OR3)n(OR4)qXp.
    Type: Application
    Filed: April 5, 2013
    Publication date: November 7, 2013
    Inventor: Air Products and Chemicals, Inc.
  • Publication number: 20130252407
    Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Inventors: Dmitry KARSHTEDT, Joerg ROCKENBERGER, Fabio ZURCHER, Brent RIDLEY, Erik SCHER
  • Patent number: 8501637
    Abstract: Methods are provided for depositing silicon dioxide containing thin films on a substrate by atomic layer deposition ALD. By using disilane compounds as the silicon source, good deposition rates and uniformity are obtained.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: August 6, 2013
    Assignee: ASM International N.V.
    Inventors: Raija H. Matero, Suvi P. Haukka
  • Patent number: 8491805
    Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: July 23, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Patent number: 8455374
    Abstract: Embodiments of the present invention generally provide a process and apparatus for increasing the absorption coefficient of a chamber component disposed in a thermal process chamber. In one embodiment, a method generally includes providing a substrate carrier having a first surface and a second surface, the first surface is configured to support a substrate and being parallel and opposite to the second surface, subjecting the second surface of the substrate carrier to a surface treatment process to roughen the second surface of the substrate carrier, wherein the substrate carrier contains a material comprising silicon carbide, and forming an oxide-containing layer on the roughened second surface of the substrate carrier. The formed oxide-containing layer has optical absorption properties at wavelengths close to the radiation delivered from one or more energy sources used to heat the chamber component.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: June 4, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Hiroji Hanawa, Kyawwin Jason Maung
  • Patent number: 8426905
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 23, 2013
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Erik Scher, Patrick Smith, Aditi Chandra, Steven Molesa
  • Patent number: 8357602
    Abstract: An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 22, 2013
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Toshihide Kikkawa
  • Patent number: 8338315
    Abstract: Processes for curing silicon based low k dielectric materials generally includes exposing the silicon based low k dielectric material to ultraviolet radiation in an inert atmosphere having an oxidant in an amount of about 10 to about 500 parts per million for a period of time and intensity effective to cure the silicon based low k dielectric material so to change a selected one of chemical, physical, mechanical, and electrical properties and combinations thereof relative to the silicon based low k dielectric material prior to the ultraviolet radiation exposure. Also disclosed herein are silicon base low k dielectric materials substantially free of sub-oxidized SiO species.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 25, 2012
    Assignee: Axcelis Technologies, Inc.
    Inventors: Darren L. Moore, Carlo Waldfried, Ganesh Rajagopalan
  • Patent number: 8334203
    Abstract: An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: December 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Dirk Pfeiffer, Ratnam Sooriyakumaran
  • Patent number: 8304353
    Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Gurtej S. Sandhu
  • Patent number: 8298965
    Abstract: Disclosed herein are precursors and methods for their use in the manufacture of semiconductor, photovoltaic, TFT-LCD, or flat panel type devices.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: October 30, 2012
    Assignee: American Air Liquide, Inc.
    Inventors: James J. F. McAndrew, Francois Doniat
  • Patent number: 8293662
    Abstract: A method of manufacturing a semiconductor device includes steps of: generating positively or negatively charged fine bubbles having substantially zero buoyancy in a coating solution as an insulating film forming material; coating the coating solution including the bubbles on a substrate to form a coating film; and baking the coating film by heating the substrate before the bubbles are removed to obtain a porous low dielectric constant insulating film.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: October 23, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Sumie Nagaseki