Organic Reactant Patents (Class 438/790)
-
Patent number: 7456116Abstract: A method to form a silicon oxide layer, where the method includes the step of providing a continuous flow of a silicon-containing precursor to a chamber housing a substrate, where the silicon-containing precursor is selected from TMOS, TEOS, OMTS, OMCTS, and TOMCATS. The method may also include the steps of providing a flow of an oxidizing precursor to the chamber, and causing a reaction between the silicon-containing precursor and the oxidizing precursor to form a silicon oxide layer. The method may further include varying over time a ratio of the silicon-containing precursor:oxidizing precursor flowed into the chamber to alter a rate of deposition of the silicon oxide on the substrate.Type: GrantFiled: December 20, 2004Date of Patent: November 25, 2008Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Shan Wong, Xinyun Xia, Vikash Banthia, Won B. Bang, Yen-Kun V. Wang, Zheng Yuan
-
Publication number: 20080242115Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.Type: ApplicationFiled: September 20, 2007Publication date: October 2, 2008Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
-
Patent number: 7410913Abstract: Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to form a silicon oxide layer, absorbing a second silicon source gas onto the substrate and reducing the second absorbed layer to form a silicon layer. The combination of the silicon oxide layer(s) and the silicon layer(s) comprise, in turn, a composite SRO layer. These manufacturing methods facilitate control of the oxygen concentration in the SRO, the relative thicknesses of the silicon oxide and silicon layers, and provides improved step coverage, thus allowing the manufacturing of high quality semiconductor devices.Type: GrantFiled: September 12, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyun Lee, Sang-Bong Bang
-
Patent number: 7404990Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same. In certain embodiments of the invention, there is provided a low-temperature process to remove at least a portion of at least one pore-forming phase within a multiphasic film thereby forming a porous film. The pore-forming phase may be removed via exposure to at least one energy source, preferably an ultraviolet light source, in a non-oxidizing atmosphere.Type: GrantFiled: November 14, 2002Date of Patent: July 29, 2008Assignee: Air Products and Chemicals, Inc.Inventors: Aaron Scott Lukas, Mark Leonard O'Neill, Mark Daniel Bitner, Jean Louise Vincent, Raymond Nicholas Vrtis, Eugene Joseph Karwacki, Jr.
-
Patent number: 7399715Abstract: A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to effect a curing treatment, wherein the composition includes organic silica sol having a carbon content of 11.8 to 16.7 mol %, and an organic solvent, the organic silica sol being a hydrolysis-condensation product produced by hydrolysis and condensation of a silane compound selected from compounds shown by the general formulae (1): R1Si(OR2)3, (2): Si(OR3)4, (3): (R4)2Si(OR5)2, and (4): R6b(R7O)3-bSi—(R10)d—Si(OR8)3-cR9c.Type: GrantFiled: July 8, 2005Date of Patent: July 15, 2008Assignee: JSR CorporationInventors: Hajime Tsuchiya, Hiromi Egawa, Terukazu Kokubo, Atsushi Shiota
-
Patent number: 7399697Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting a mixture comprising an oxidizable silicon component and an oxidizable component having thermally labile groups with an oxidizing gas in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.Type: GrantFiled: December 2, 2004Date of Patent: July 15, 2008Assignee: Applied Materials, Inc.Inventor: Robert P. Mandal
-
Patent number: 7387971Abstract: A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns over areas outside where thin film patterns are to be formed over the substrate. The fabricating method also includes depositing a hydrophobic nano powder thin film material over the substrate and between the hydrophilic resin patterns and removing the hydrophilic resin patterns to form hydrophobic nano powder thin film patterns over the substrate. Moreover, the fabricating method includes treating the hydrophobic nano powder thin film patterns to form the thin film pattern.Type: GrantFiled: October 28, 2005Date of Patent: June 17, 2008Assignee: LG.Philips LCD Co., Ltd.Inventors: Gee Sung Chae, Mi Kyung Park
-
Patent number: 7387943Abstract: A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin thermal oxide layer, creating a required thickness. The thin thermal oxide layer and the CVD material layer are formed in the same CVD apparatus. As a result, a process can be simplified and a particle-leading pollution can be prevented.Type: GrantFiled: February 25, 2002Date of Patent: June 17, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Hyung Kim, Sung-Eui Kim
-
Patent number: 7361614Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.Type: GrantFiled: April 14, 2006Date of Patent: April 22, 2008Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Chris W. Hill
-
Patent number: 7357977Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.Type: GrantFiled: January 13, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Christos Dimitrios Dimitrakopoulos, Stephen McConnell Gates, Alfred Grill, Michael Wayne Lane, Eric Gerhard Liniger, Xiao Hu Liu, Son Van Nguyen, Deborah Ann Neumayer, Thomas McCarroll Shaw
-
Publication number: 20080085612Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.Type: ApplicationFiled: October 5, 2006Publication date: April 10, 2008Inventors: John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
-
Patent number: 7354873Abstract: A method for forming an insulation film having filling property on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and forming an insulation film constituted by Si, O, H, and optionally C or N on a substrate by plasma reaction using a combination of low-frequency RF power and high-frequency RF power in the reaction space. The plasma reaction is activated while controlling the flow of the reaction gas to lengthen a residence time, Rt, of the reaction gas in the reaction space.Type: GrantFiled: August 18, 2006Date of Patent: April 8, 2008Assignee: ASM Japan K.K.Inventors: Atsuki Fukazawa, Nobuo Matsuki, Seijiro Umemoto
-
Patent number: 7354779Abstract: Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the variable depth is modulated based on the local topography of the wafer. The resultant topography of the applied film and wafer is substantially planar (e.g., within approximately 100 nm) across the wafer.Type: GrantFiled: March 10, 2006Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Colin J. Brodsky, Scott J. Bukofsky, Allen H. Gabor
-
Publication number: 20080070421Abstract: A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film.Type: ApplicationFiled: September 20, 2006Publication date: March 20, 2008Inventors: Ping Xu, Christopher Dennis Bencher
-
Patent number: 7341761Abstract: Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules with at least one carbon—carbon triple bond, or carbon—carbon double bond, or a combination of these groups and depositing the carbon doped oxide dielectric layer under conditions in which the resulting dielectric layer has a dielectric constant of not greater than about 2.7.Type: GrantFiled: March 11, 2004Date of Patent: March 11, 2008Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, Haiying Fu, Xingyuan Tang
-
Patent number: 7329612Abstract: A semiconductor device is manufactured by the steps of generating a film forming gas by setting a flow rate ratio of H2O to any one of a silicon-contained organic compound having a siloxane bond and a silicon-contained organic compound having a CH3 group to 4 or more and adjusting a gas pressure to 1.5 Torr or more, applying a power to the film forming gas to generate a plasma thereof so as to react it, and thus forming a low-dielectric insulating film (62) on a substrate (61), plasmanizing a process gas containing at least any one of He, Ar, H2 or deuterium, and bringing the low-dielectric insulating film (62) into contact with the plasma of the process gas.Type: GrantFiled: October 20, 2003Date of Patent: February 12, 2008Assignee: Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Yuhko Nishimoto, Kazuo Maeda
-
Patent number: 7326657Abstract: A method for providing a dielectric film having enhanced adhesion and stability. The method includes a post deposition treatment that densifies the film in a reducing atmosphere to enhance stability if the film is to be cured ex-situ. The densification generally takes place in a reducing environment while heating the substrate. The densification treatment is particularly suitable for silicon-oxygen-carbon low dielectric constant films that have been deposited at low temperature.Type: GrantFiled: November 15, 2004Date of Patent: February 5, 2008Assignee: Applied Materials, Inc.Inventors: Li-Qun Xia, Frederic Gaillard, Ellie Yieh, Tian H. Lim
-
Patent number: 7314837Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.Type: GrantFiled: December 29, 2005Date of Patent: January 1, 2008Assignee: Micron Technology, Inc.Inventors: Li Li, Weimin Li
-
Patent number: 7312165Abstract: Methods of film deposition using metals and metal oxides. A thin film of germanium oxide and an oxide of a non-germanium metal is deposited by ALD by alternating deposition of first and second precursor compounds, wherein the first precursor compound includes a metal other than germanium, and the second precursor compound includes germanium.Type: GrantFiled: May 5, 2005Date of Patent: December 25, 2007Inventors: Gregory M. Jursich, Ronald S. Inman
-
Patent number: 7285502Abstract: A method for forming a porous insulative structure on a semiconductor device structure includes forming a layer of unconsolidated electrically insulative, or dielectric, material with microcapsules dispersed therethrough on at least a portion of the surface of the semiconductor device structure. The microcapsules may be hollow or include a removable filler. Once the layer has been formed, the unconsolidated material is at least partially consolidated. Filler, if any, may be removed from the microcapsules to provide a porous insulative layer or structure. This layer or structure may be configured to support conductive elements or other features of the semiconductor device.Type: GrantFiled: September 1, 2004Date of Patent: October 23, 2007Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Tongbi Jiang
-
Patent number: 7282458Abstract: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.Type: GrantFiled: November 7, 2005Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Stephen M. Gates, Christos D. Dimitrakopoulos, Alfred Grill, Son Van Nguyen
-
Patent number: 7270886Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing polysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 3,300 to 3,700 to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.Type: GrantFiled: June 7, 2004Date of Patent: September 18, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Ho Lee, Jun-Hyun Cho, Jung-Sik Choi, Dong-Jun Lee
-
Patent number: 7271112Abstract: Methods of forming conformal films with increased density are described. The methods may be used to improve gap fill in semiconductor device manufacturing by eliminating seams and voids. The methods involve operating at high reactant partial pressure. Additionally, film properties may be further enhanced by optimizing the temperature of the substrate during exposure to the metal-containing and/or silicon-containing precursor gases commonly used in conformal film deposition techniques such as ALD and PDL.Type: GrantFiled: December 30, 2004Date of Patent: September 18, 2007Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Raihan M. Tarafdar, Adrianne K. Tipton, Ron Rulkens, Dennis M. Hausmann, Jeff Tobin
-
Patent number: 7270765Abstract: To provide a composition for forming a dielectric layer excellent in dielectric constant and withstand voltage properties, a MIM capacitor and a process for its production. A composition for forming a dielectric layer, which comprises fine particles of perovskite type dielectric crystal, glass frit, and a hydrolysable silicon compound or its oligomer, and a MIM capacitor comprising a substrate, and a bottom electrode layer, a dielectric layer having a structure such that fine particles of perovskite type dielectric crystal are dispersed in a silicon oxide matrix containing glass-forming ions and a top electrode, formed on the substrate in this order.Type: GrantFiled: June 13, 2005Date of Patent: September 18, 2007Assignee: Asahi Glass Company, LimitedInventors: Hiroyuki Tomonaga, Katsuaki Miyatani, Yoshihisa Beppu, Kumiko Takahashi, Kazuo Sunahara
-
Patent number: 7256146Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.Type: GrantFiled: May 13, 2005Date of Patent: August 14, 2007Assignee: International Business Machines CorporationInventors: Stephan A. Cohen, Stephen McConnell Gates, Jeffrey C. Hedrick, Elbert E. Huang, Dirk Pfeiffer
-
Patent number: 7241704Abstract: Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. In other cases, the structure former precursor has carbon-carbon double or triple bonds and one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. Once the precursor film is formed, the porogen is removed, leaving a porous low-k dielectric matrix with high mechanical strength. Different types of structure former precursors and porogen precursors are described. The resulting low stress low-k porous film may be used as a low-k dielectric film in integrated circuit manufacturing applications.Type: GrantFiled: August 27, 2004Date of Patent: July 10, 2007Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, Haiying Fu, David C. Smith, David Mordo
-
Patent number: 7241707Abstract: Multiple-layer films in integrated circuit processing may be formed by the phase segregation of a single composition formed above a semiconductor substrate. The composition is then induced to phase segregate into at least a first continuous phase and a second continuous phase. The composition may be formed of two or more components that phase segregate into different continuous layers. The composition may also be a single component that breaks down upon activation into two or more components that phase segregate into different continuous layers. Phase segregation may be used to form, for example, a sacrificial light absorbing material (SLAM) and a developer resistant skin, a dielectric layer and a hard mask, a photoresist and an anti-reflective coating (ARC), a stress buffer coating and a protective layer on a substrate package, and light interference layers.Type: GrantFiled: February 17, 2005Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Robert P. Meagley, Michael J. Leeson, Michael D. Goodner, Bob E. Leet, Michael L. McSwiney, Shan C. Clark
-
Patent number: 7239018Abstract: Provided is a composition formed by hydrolysis and condensation composition of the alkoxysilane, the composition comprising a reduced amount of metallic and halogen impurities and being applicable as electronic material. Also provided is an insulating film having low dielectric constant produced by applying the composition and sintering it. More specifically, a method for manufacturing a composition for forming a film, comprising a step of hydrolysis and condensation of alkoxysilane or a partial hydrolysis product of the alkoxysilane in an organic solvent in the presence of trialkylmethylammonium hydroxide as catalyst, wherein the alkoxysilane is selected from the groups consisting of compounds represented by formulae (1) to (4) below, and the trialkylmethylammonium hydroxide is represented by formula (5) below.Type: GrantFiled: March 9, 2004Date of Patent: July 3, 2007Assignees: Shin-Etsu Chemical Co., Ltd., Matsushita Electric Industrial Co., Ltd.Inventors: Yoshitaka Hamada, Fujio Yagihashi, Hideo Nakagawa, Masaru Sasago
-
Patent number: 7232750Abstract: Methods for improving memory retention properties of a polymer memory cell are disclosed. The methods include forming a first electrode, depositing a passive layer over the first electrode, forming a semiconducting polymer layer containing at least one semiconducting polymer with at least one charge carrier-binding group over the passive layer, and forming a second electrode. The charge carrier-binding groups can be incorporated into semiconducting polymers either as side groups or into the main chain of semiconducting polymers.Type: GrantFiled: January 12, 2005Date of Patent: June 19, 2007Assignee: Spansion LLCInventor: Richard P. Kingsborough
-
Patent number: 7229936Abstract: A method is provided for preparing a substrate for photolithographic patterning. The method includes providing a substrate having at least an exposed rough surface layer including a polymeric material. The rough surface layer has surface features characterized by feature step height varying between about two percent and twenty percent of the minimum photolithographic half-pitch. A layer of photoresist material is then provided over the exposed rough surface layer and patterned.Type: GrantFiled: May 3, 2004Date of Patent: June 12, 2007Assignee: International Business Machines CorporationInventors: Colin J. Brodsky, Scott J. Bukofsky, Dario L. Goldfarb, Scott D. Halle
-
Patent number: 7226876Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.Type: GrantFiled: May 11, 2005Date of Patent: June 5, 2007Assignee: Applied Materials, Inc.Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
-
Patent number: 7208425Abstract: Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.Type: GrantFiled: March 3, 2006Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Xinyua Xia, Zheng Yuan
-
Patent number: 7205249Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10–250 W. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH3SiH3, or dimethylsilane, (CH3)2SiH2, and nitrous oxide, N2O, at an RF power level from about 10 to 200 W or a pulsed RF power level from about 20 to 250 W during 10–30% of the duty cycle.Type: GrantFiled: October 5, 2004Date of Patent: April 17, 2007Assignee: Applied Materials, Inc.Inventors: David Cheung, Wai-Fan Yau, Robert R. Mandal
-
Patent number: 7192893Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.Type: GrantFiled: August 5, 2003Date of Patent: March 20, 2007Assignee: Micron Technology Inc.Inventors: William Budge, Gurtej S. Sandhu, Christopher W. Hill
-
Patent number: 7179537Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing perhydropolysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 4,000 to 8,000, and a molecular weight dispersion within the range of about 3.0 to 4.0, to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.Type: GrantFiled: October 24, 2002Date of Patent: February 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Ho Lee, Jung-Sik Choi, Hong-Ki Kim, Dong-Jun Lee, Dae-Won Kang, Sang-Mun Chon
-
Patent number: 7170089Abstract: A new compound derivative that can be used to form a unit molecular film as a rectifier in a molecular electronic device, a new rectifying compound (4,5,9,10-tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester and its derivative (4,5,9,10-Tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester, and methods of synthesizing the compounds are provided.Type: GrantFiled: February 23, 2006Date of Patent: January 30, 2007Assignee: Electronics and Telecommunications Research InstituteInventors: Hyoyoung Lee, Mun Seok Jeong, Do Hyun Kim, Taehyoung Zyung
-
Patent number: 7166519Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.Type: GrantFiled: June 12, 2004Date of Patent: January 23, 2007Assignee: Hynix Semiconductor Inc.Inventors: Sang-Tae Ahn, Dong-Sun Sheen, Seok-Pyo Song
-
Patent number: 7166542Abstract: A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and/or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and/or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.Type: GrantFiled: November 21, 2003Date of Patent: January 23, 2007Assignee: Nanya Technology CorporationInventors: Ming-Hung Lo, Liang-Pin Chou, Chun-Ming Wang, Li-Fu Chen
-
Patent number: 7160821Abstract: A silicon oxide layer is produced by plasma enhanced decomposition of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.Type: GrantFiled: January 27, 2004Date of Patent: January 9, 2007Assignee: Applied Materials, Inc.Inventors: Tzu-Fang Huang, Yung-Cheng Lu, Li-Qun Xia, Ellie Yieh, Wai-Fan Yau, David W. Cheung, Ralf B. Willecke, Kuowei Liu, Ju-Hyung Lee, Farhad K. Moghadam, Yeming Jim Ma
-
Patent number: 7153355Abstract: To provide a silica film-forming material having a low dielectric constant and giving a film of less undergoing change in aging, a coating solution for forming a silica film includes a hydrolysis product of a mixture comprising: a tetraalkoxysilane; and at least one of a monoalkyltrialkoxysilane and a dialkyldialkoxysilane, and an ammonium salt represented by formula (I): wherein R1 represents an alkyl group having from 6 to 30 carbon atoms, R2 represents an alkyl group having from 1 to 5 carbon atoms, and X represents CH3COO, SO3H or OH.Type: GrantFiled: October 13, 2004Date of Patent: December 26, 2006Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Yoshinori Sakamoto, Naoki Yamashita
-
Patent number: 7141492Abstract: The invention provides a method of forming a high-performance thin-film at low cost using a liquid material in safety, an apparatus to form a thin-film, a method of manufacturing a semiconductor device, an electro-optical unit, and an electronic apparatus. An apparatus to form a thin-film includes a coating unit to apply a liquid material containing a thin-film component onto a substrate and also includes heat-treating units to heat the substrate applied with the liquid material. The coating unit and the heat-treating units each include a control device to control the atmosphere in a treating chamber to treat the substrate.Type: GrantFiled: April 21, 2003Date of Patent: November 28, 2006Assignee: Seiko Epson CorporationInventor: Ichio Yudasaka
-
Patent number: 7135418Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.Type: GrantFiled: March 9, 2005Date of Patent: November 14, 2006Assignee: Novellus Systems, Inc.Inventor: George D. Papasouliotis
-
Patent number: 7132374Abstract: A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. The reagent feed stream comprises a mixture of codeposition reagents and a selective silicon removal reagent. RF power modulation is used to control the codeposition and the selective silicon removal steps with the later proceeds whenever the RF power is turned off or reduced to a low level. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The method is also advantageous for forming other porous films for other applications.Type: GrantFiled: August 17, 2004Date of Patent: November 7, 2006Inventors: Cecilia Y. Mak, Kam S. Law
-
Patent number: 7126208Abstract: Provided are a composition for forming porous film which can form a porous film having practical mechanical strength in a simple and low cost process; a porous film and a method for forming the film; and an inexpensive, high-performing and highly reliable semiconductor device comprising the porous film inside. More specifically, provided is a composition for forming porous film, comprising a polymer which is obtainable by hydrolyzing and condensing one or more silane compounds represented by Formula (1), or preferably by hydrolyzing and co-condensing one or more silane compounds represented by Formula (1) and one more silane compounds represented by Formula (2), Formulas (1) and (2) being: (R1)aSi(R2)4-a ??(1) (R3)bSi(R4)4-b ??(2) Also provided is a method for forming porous film comprising a step of applying said composition on a substrate to form film and a step of transforming the film into porous film.Type: GrantFiled: November 12, 2003Date of Patent: October 24, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Motoaki Iwabuchi, Fujio Yagihashi, Yoshitaka Hamada, Hideo Nakagawa, Masaru Sasago
-
Patent number: 7122484Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.Type: GrantFiled: April 28, 2004Date of Patent: October 17, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Baw-Ching Perng, Yi-Chen Huang, Jun-Lung Huang, Bor-Wen Chan, Peng-Fu Hsu, Hsin-Ching Shih, Lawrance Hsu, Hun-Jan Tao
-
Patent number: 7119016Abstract: A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.Type: GrantFiled: October 15, 2003Date of Patent: October 10, 2006Assignees: International Business Machines Corporation, Applied Materials, Inc.Inventors: Ashima B. Chakravarti, Anita Madan, Woo-Hyeong Lee, Gregory Wayne Dibello, Ramaseshan Suryanarayanan Iyer
-
Patent number: 7115534Abstract: Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.Type: GrantFiled: May 18, 2004Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Son Van Nguyen, Michael D. Armacost, Mehul Naik, Girish A. Dixit, Ellie Y. Yieh
-
Patent number: 7109129Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.Type: GrantFiled: March 9, 2005Date of Patent: September 19, 2006Assignee: Novellus Systems, Inc.Inventor: George D. Papasouliotis
-
Patent number: 7105460Abstract: Methods are provided for depositing a dielectric material. The dielectric material may be used for an anti-reflective coating or as a hardmask. In one aspect, a method is provided for processing a substrate including introducing a processing gas comprising a silane-based compound and an organosilicon compound to the processing chamber and reacting the processing gas to deposit a nitrogen-free dielectric material on the substrate. The dielectric material comprises silicon and oxygen.Type: GrantFiled: July 11, 2002Date of Patent: September 12, 2006Assignee: Applied MaterialsInventors: Bok Hoen Kim, Sudha Rathi, Sang H. Ahn, Christopher D. Bencher, Yuxiang May Wang, Hichem M'Saad, Mario D. Silvetti
-
Patent number: 7101815Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is provided, comprising placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.Type: GrantFiled: August 26, 2004Date of Patent: September 5, 2006Assignee: Micron Technology, Inc.Inventor: Ravi Iyer