Organic Reactant Patents (Class 438/794)
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Patent number: 7098061Abstract: A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localised region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.Type: GrantFiled: June 21, 2002Date of Patent: August 29, 2006Assignee: Plastic Logic LimitedInventors: Henning Sirringhaus, Richard Henry Friend, Takeo Kawase
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Patent number: 7094709Abstract: The present invention relates to metal oxide coating materials that can be used as thin film thin film coatings on various substrate surfaces. The invention also concerns a method of making metal oxide material which are stable in aqueous phase and that can be deposited on a substrate by liquid phase deposition, such as spin-on deposition. The new materials can be patterned lithographically or non-lithographically and are applicable for building up various electronic and opto-electronic device structures, such as anti-reflection layers, high-k interlayer and gate oxide structures for ICs, etch stop layer, CMP stop layer, solar cells, OLEDs packaging, optical thin film filters, optical diffractive grating applications and hybrid thin film diffractive grating structures.Type: GrantFiled: June 15, 2004Date of Patent: August 22, 2006Assignee: Braggone OyInventor: Ari Kärkkäinen
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Patent number: 7084080Abstract: A method of synthesizing an aminosilane source reagent composition, by reacting an aminosilane precursor compound with an amine source reagent compound in a solvent medium comprising at least one activating solvent component, to yield an aminosilane source reagent composition having less than 1000 ppm halogen.Type: GrantFiled: March 29, 2002Date of Patent: August 1, 2006Assignee: Advanced Technology Materials, Inc.Inventors: Alexander S. Borovik, Ziyun Wang, Chongying Xu, Thomas H. Baum, Brian L. Benac
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Patent number: 7067414Abstract: A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the dielectric layer, it is exposed to a plasma including oxygen effective to reduce the dielectric constant to below what it was prior to the exposing. A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least patially formed thereon. In a chamber, an inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is plasma-enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: March 27, 2000Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7067415Abstract: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: July 25, 2002Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7001844Abstract: Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.Type: GrantFiled: April 30, 2004Date of Patent: February 21, 2006Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Shreesh Narasimha, Victor Chan, Judson Holt, Satya N. Chakravarti
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Patent number: 6974781Abstract: A method is provided for obtaining stable and elevated deposition rates in a reaction chamber, following the cleaning of the chamber. The method involves cleaning of the chamber, pre-coating the interior surfaces of the reaction chamber with an inorganic composition, and then, using the pre-coated chamber to deposit an organic layer onto a workpiece.Type: GrantFiled: October 20, 2003Date of Patent: December 13, 2005Assignee: ASM International N.V.Inventors: Eric A. H. Timmermans, Maarten J. Teepen, Raffaele Mucciato, Rudi Wilhelm
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Patent number: 6955974Abstract: A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrate, thereby forming a trench; c) thermal-oxidizing the resultant substrate to form a sidewall oxide layer on a surface of the trench; d) nitrifying the sidewall oxide layer through the use of NH3 annealing; e) depositing a liner aluminum nitride layer on an entire surface of the silicon substrate inclusive of the nitrated sidewall oxide layer; f) depositing a buried oxide layer on the liner aluminum nitride layer to fill the trench; g) performing a chemical mechanical polishing process with respect to the buried oxide layer; and h) eliminating the pad nitride layer.Type: GrantFiled: June 25, 2004Date of Patent: October 18, 2005Assignee: Hynix Semiconductor Inc.Inventors: Tae Hyeok Lee, Cheol Hwan Park, Dong Su Park, Ho Jin Cho, Eun A Lee
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Patent number: 6890869Abstract: A method of forming a silicon nitride film includes a CVD process that uses an organic Si compound having an organic silazane bond as a gaseous source. The CVD process is conducted under a condition that the organic silazane bond in the organic Si source is preserved in the silicon nitride film.Type: GrantFiled: August 19, 2001Date of Patent: May 10, 2005Assignee: Tokyo Electron LimitedInventor: Gishi Chung
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Patent number: 6849562Abstract: A method for depositing a low k dielectric film comprising silicon, carbon, and nitrogen is provided. The low k dielectric film is formed by a gas mixture comprising a silicon source, a carbon source, and NR1R2R3, wherein R1, R2, and R3 are selected from the group consisting of alkyl and phenyl groups. The low k dielectric film may be used as a barrier layer, an etch stop, an anti-reflective coating, or a hard mask.Type: GrantFiled: March 4, 2002Date of Patent: February 1, 2005Assignee: Applied Materials, Inc.Inventors: Chi-I Lang, Li-Qun Xia, Ping Xu, Louis Yang
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Patent number: 6828256Abstract: A method of forming a film on a substrate using one or more complexes containing one or more chelating O- and/or N-donor ligands. The complexes and methods are particularly suitable for the preparation of semiconductor structures using chemical vapor deposition techniques and systems.Type: GrantFiled: January 13, 2004Date of Patent: December 7, 2004Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 6828683Abstract: In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive substrate and a second material is formed proximate the conductive material. A barrier layer is formed between the conductive material and the second material. The barrier layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material. In another aspect, the invention encompasses a composition of matter comprising silicon chemically bonded to both nitrogen and an organic material. The nitrogen is not bonded to carbon. In yet another aspect, the invention encompasses a semiconductor processing method. A semiconductive substrate is provided and a layer is formed over the semiconductive substrate. The layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material.Type: GrantFiled: December 23, 1998Date of Patent: December 7, 2004Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin
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Patent number: 6777351Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.Type: GrantFiled: April 3, 2003Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventor: Christopher W Hill
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Patent number: 6716773Abstract: A process for producing semiconductor substrates with a coating film having excellent chemical resistance with high yield and excellent production reliability without any development of cracks and any generation or collection of foreign matter resulting from a projected portion of the coating film, which includes the steps of: (a) forming a coating film by coating an insulating film-forming coating liquid on a substrate mounted on a rotating disc of a spin coater according to a spin coating method; and (b) removing the projected portion of the coating film formed at a periphery of the substrate by ejecting a solvent through a nozzle moving from any point on a line drawn between the periphery edge and a center of the substrate toward the periphery edge while rotating the substrate.Type: GrantFiled: September 19, 2002Date of Patent: April 6, 2004Assignee: Catalysts & Chemicals Industries Co., Ltd.Inventors: Miki Egami, Ryo Muraguchi
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Patent number: 6716772Abstract: A semiconductor device manufacturing apparatus which forms silicon nitride films on a plurality of substrates by thermal chemical vapor deposition. The semiconductor device manufacturing apparatus includes a vertical reaction tube, a substrate holder, and gas supplies. The vertical reaction tube has an inner wall. The substrate holder is for holding the plurality of substrates in the vertical reaction tube with the plurality of substrates being vertically stacked with a distance “a” between adjacent substrates of the plurality of substrates and a distance “b” between edges of the plurality of substrates and the inner wall of the vertical reaction tube being maintained substantially equal to each other.Type: GrantFiled: August 20, 2002Date of Patent: April 6, 2004Assignee: Kokusai Electric Co., Ltd.Inventors: Norikazu Mizuno, Kiyohiko Maeda
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Patent number: 6673709Abstract: The reactive element is introduced to the surface of the metal substrate in the form of an oxide powder and the aluminide-type coating is then formed.Type: GrantFiled: August 27, 2001Date of Patent: January 6, 2004Assignee: SNECMA MoteursInventors: Yann Jaslier, Alain Martinez, Marie-Christine Ntsama Etoundi, Guillaume Oberlaender
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Patent number: 6673725Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plasma of a film-forming gas containing an oxygen-containing gas of N2O, H2O, or CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3).Type: GrantFiled: April 30, 2001Date of Patent: January 6, 2004Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Kouichi Ohira, Kazuo Maeda
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Patent number: 6664201Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.Type: GrantFiled: December 5, 2001Date of Patent: December 16, 2003Assignee: United Microelectronics Corp.Inventors: Jing-Horng Gau, Shuenn-Jeng Chen
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Patent number: 6645835Abstract: A method for forming a semiconductor film capable allowing easy cleaning of the processing equipment and capable of forming an epitaxial film at low temperatures as well as a manufacturing method for semiconductor devices utilizing this forming method is needed for achieving selective crystalline growth on semiconductor film. The forming method comprises a process for forming a mask having an aperture exposing a substrate surface on substrate, and a process for forming a semiconductor film by selective crystalline growth on a semiconductor piece by means of catalytic chemical vapor deposition on a substrate surface exposed by an aperture on a mask; as well as a manufacturing method for semiconductor devices utilizing the semiconductor film forming method.Type: GrantFiled: March 16, 2000Date of Patent: November 11, 2003Assignee: Sony CorporationInventors: Hisayoshi Yamoto, Hideo Yamanaka, Hajime Yagi, Yuuichi Sato
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Publication number: 20030190821Abstract: The present invention discloses a method for forming a layer of nitrogen and silicon containing material on a substrate by first providing a heated substrate and then flowing a gas which has silicon and nitrogen atoms but no carbon atoms in the same molecule over said heated substrate at a pressure of not higher than 500 Torr, such that a layer of nitrogen and silicon containing material is formed on the surface. The present invention is further directed to a composite structure that includes a substrate and a layer of material containing nitrogen and silicon but not carbon overlying the substrate for stopping chemical species from reaching the substrate. The present invention is further directed to a structure that includes a semiconducting substrate, a gate insulator on the substrate, a nitrogen-rich layer on top of the gate insulator, and a gate electrode on the nitrogen-rich layer, wherein the nitrogen-rich layer blocks diffusion of contaminating species from the gate electrode to the gate insulator.Type: ApplicationFiled: May 2, 2003Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Douglas Andrew Buchanan, Matthew Warren Copel, Fenton Read McFeely, Patrick Ronald Varekamp, Mark Monroe Banaszak Holl, Kyle Erik Litz
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Patent number: 6624088Abstract: A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is controlled to provide a wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom.Type: GrantFiled: April 10, 2002Date of Patent: September 23, 2003Assignee: Micron Technology, Inc.Inventor: John T. Moore
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Patent number: 6620741Abstract: A method for controlling etch bias of carbon doped oxide films comprising performing the etch in a cyclic two step process i.e., a carbon doped oxide (CDO) removal process, said CDO removal process comprises a first gas to etch a trench in the CDO layer. The CDO removal process is followed by a polymer deposition process. The polymer deposition process comprises introducing a second gas in the reactor to deposit a polymer in the trench of the CDO layer. The first gas comprises a first molecule having a first ratio of carbon atoms to fluorine atoms, and the second gas comprises a second molecule having a second ratio of carbon atoms to fluorine atoms, such that the second ratio of carbon atoms to fluorine atoms is greater than the first ratio of carbon atoms to fluorine atoms. The above process may be repeated to etch the final structure.Type: GrantFiled: June 10, 2002Date of Patent: September 16, 2003Assignee: Intel CorporationInventors: David H. Gracias, Hyun-Mog Park, Vijayakumar S. Ramachandrarao
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Publication number: 20030162412Abstract: A method of forming a silicon nitride film includes a CVD process that uses an organic Si compound having an organic silazane bond as a gaseous source. The CVD process is conducted under a condition that the organic silazane bond in the organic Si source is preserved in the silicon nitride film.Type: ApplicationFiled: January 23, 2003Publication date: August 28, 2003Inventor: Gishi Chung
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Patent number: 6573196Abstract: A method of forming an organosilicate layer is disclosed. The organosilicate layer is formed by applying an electric field to a gas mixture comprising a phenyl-based silane compound. The gas mixture may optionally include an oxidizing gas. The organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the organosilicate layer is used as an anti-reflective coating (ARC). In another integrated circuit fabrication process, the organosilicate layer is incorporated into a damascene structure.Type: GrantFiled: August 12, 2000Date of Patent: June 3, 2003Assignee: Applied Materials Inc.Inventors: Frederick Gaillard, Li-Qun Xia, Tian-Hoe Lim, Ellie Yieh
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Patent number: 6534424Abstract: In a method of forming silicon nitride on a substrate, a substrate is provided in a reaction chamber and a nitrogen-containing gas is introduced into the chamber so that a portion of the nitrogen-containing gas is chemically adsorbed on the substrate surface. Thereafter, the reaction chamber is pumped down to remove the nitrogen-containing gas. A silicon-containing gas is introduced into the reaction chamber to react with the adsorbed nitrogen-containing gas to form a silicon nitride layer on the substrate. Thereafter, the silicon-containing gas may be removed and the cycle repeated to deposit additional silicon nitride layers on the substrate.Type: GrantFiled: August 21, 2001Date of Patent: March 18, 2003Assignee: Applied Materials, Inc.Inventors: Tzy-Tzan Fu, Hung-Chuan Chen, Chao-Ming Hung
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Patent number: 6531415Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a silicon nitride dielectric layer with attenuated defects and inhomogeneities. There is provided one or more substrates. There is then provided a reactor tube which is part of an apparatus suitable for providing various gases at elevated temperatures. There is then purged the reactor tube with an inert gas in a low temperature cycle purge (LTCP) step at a temperature below deposition temperature. There is then placed the substrate(s) within a reactor tube. There is then deposited a silicon nitride dielectric layer upon the substrate(s), employing silane and ammonia gases employing a low pressure chemical vapor deposition (LPCVD) method. There is then purged the reaction tube at a temperature below the deposition temperature, followed by removal of the substrate carrier with attenuated formation of particulates and inhomogeneities within and about the silicon nitride layer and reaction tube.Type: GrantFiled: January 30, 2002Date of Patent: March 11, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wan-Cheng Yang, Ren-Dou Lee
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Patent number: 6500772Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.Type: GrantFiled: January 8, 2001Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Richard A. Conti, Chester Dziobkowski, Thomas Ivers, Paul Jamison, Frank Liucci
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Publication number: 20020197890Abstract: A semiconductor device manufacturing method comprises a step of forming, by thermal chemical vapor deposition method, silicon nitride films on a plurality of substrates stacked in a reaction tube, with bis tertiary butyl amino silane and NH3 flowing into the reaction tube accommodating the stacked substrates, wherein the silicon nitride films are formed on the substrates in a state in which a distance “a” between adjacent the substrates and a distance “b” between edges of the substrates and an inner wall of the reaction tube are maintained substantially equal to each other.Type: ApplicationFiled: August 20, 2002Publication date: December 26, 2002Applicant: KOKUSAI ELECTRIC CO., LTD.Inventors: Norikazu Mizuno, Kiyohiko Maeda
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Patent number: 6495447Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer; decreasing the hydrophilic properties of a first portion of the dielectric layer, forming an opening through the dielectric layer, and filling the opening with metal to form a first metal feature. The hydrophilic properties of the first portion are lesser than a second portion of the dielectric layer. The hydrophilic properties of the first portion can be decreased by doping the first portion with hydrogen using ion implantation or plasma etching. An upper surface of the dielectric layer can also be roughened during the process of hydrogen doping. A semiconductor device produced by the method of manufacturing is also disclosed.Type: GrantFiled: June 26, 2001Date of Patent: December 17, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Lynne A. Okada, Calvin T. Gabriel
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Patent number: 6486083Abstract: A semiconductor device manufacturing method including a step of forming, by thermal chemical vapor deposition, silicon nitride films on a plurality of substrates vertically stacked in a vertical reaction tube having an inner wall. Bis tertiary butyl amino silane and NH3 flows into the vertical reaction tube and flows vertically from one end of the plurality of substrates to an opposing end of the plurality of substrates without flowing into the vertical reaction tube through the inner wall at a height between the one end and the opposing end of the plurality of substrates. The silicon nitride films are formed on the plurality of substrates in a state in which a distance “a” between adjacent substrates of the plurality of substrates and a distance “b” between edges of the plurality of substrates and the inner wall of the vertical reaction tube are maintained substantially equal to each other.Type: GrantFiled: September 29, 2000Date of Patent: November 26, 2002Assignee: Kokusai Electric Co., Ltd.Inventors: Norikazu Mizuno, Kiyohiko Maeda
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Publication number: 20020173172Abstract: A method for producing fluorinated hydrogenated silicon oxycarbide (H:F:SiOC) and amorphous fluorinated hydrogenated silicon carbide (H:F:SiC) films having low dielectric permittivity. The method comprises reacting a silicon containing compound with a fluorocarbon or fluorohydrocarbon compound having an unsaturated carbon bonded to F or H. The resulting films are useful in the formation of semiconductor devices.Type: ApplicationFiled: March 20, 2002Publication date: November 21, 2002Inventors: Mark Jon Loboda, Byung Keun Hwang
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Patent number: 6465373Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.Type: GrantFiled: August 31, 2000Date of Patent: October 15, 2002Assignee: Micron Technology, Inc.Inventors: Lingyi A. Zheng, Er-Xuan Ping
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Publication number: 20020142623Abstract: Disclosed is a method for forming an insulating layer, comprising coating a substrate with an insulating film material to form a coated film, the insulating film material containing at least first and second polymers differing from each other in average molecular weight, and heating the coated film while irradiating the coated film with an electron beam.Type: ApplicationFiled: March 26, 2002Publication date: October 3, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Hideshi Miyajima, Miyoko Shimada, Rempei Nakata
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Publication number: 20020111039Abstract: A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is controlled to provide a wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom.Type: ApplicationFiled: April 10, 2002Publication date: August 15, 2002Inventor: John T. Moore
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Publication number: 20020090835Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.Type: ApplicationFiled: January 8, 2001Publication date: July 11, 2002Inventors: Ashima B. Chakravarti, Richard A. Conti, Chester Dziobkowski, Thomas Ivers, Paul Jamison, Frank Liucci
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Publication number: 20020081864Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.Type: ApplicationFiled: August 6, 2001Publication date: June 27, 2002Inventors: Lingyi A. Zheng, Er-Xuan Ping
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Patent number: 6391803Abstract: An atomic layer deposition method of forming a solid thin film layer containing silicon. A substrate is loaded into a chamber. A first portion of a first reactant is chemisorbed onto the substrate, and a second portion of the first reactant is physisorbed onto the substrate. The physisorbed portion is purged from the substrate and the chamber. A second reactant is injected into the chamber. A first portion is chemically reacted with the chemisorbed first reactant to form a silicon-containing solid on the substrate. The first reactant is preferably Si[N(CH3)2]4, SiH[N(CH3)2]3, SiH2[N(CH3)2]2 or SiH3[N(CH3)2]. The second reactant is preferably activated NH3.Type: GrantFiled: June 20, 2001Date of Patent: May 21, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong-Kwan Kim, Young-Wook Park, Seung-Hwan Lee
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Publication number: 20020055273Abstract: In a semiconductor device including a semiconductor substrate and a gate electrode layer, a single silicon oxide nitride (SiON) layer is sandwiched by the semiconductor substrate and the gate electrode layer.Type: ApplicationFiled: November 7, 2001Publication date: May 9, 2002Applicant: NEC CorporationInventor: Eiji Hasegawa
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Publication number: 20010055891Abstract: The present invention relates to low dielectric materials essential for a semiconductor having high density and high performance of the next generation, particularly to a process for preparing a porous interlayer insulating film having low dielectric constant containing pores with a size of a few nanometers or less.Type: ApplicationFiled: April 27, 2001Publication date: December 27, 2001Inventors: Min-Jin Ko, Hye-Yeong Nam, Dong-Seok Shin, Myung-Sun Moon, Jung-Won Kang
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Patent number: 6333278Abstract: An interlayer insulating film of a semiconductor device is made of a material in which silicon atoms are main elements, and each of the silicon atoms has an oxygen bond and a carbon bond, and further at least some of the silicon atoms have a hydrogen bond. The interlayer insulating film is formed by chemical vapor deposition employing a mixed gas of hydrogen peroxide and a reactive gas having a gas molecular structure in which silicon atoms have a hydrogen bond and a carbon bond.Type: GrantFiled: March 15, 2000Date of Patent: December 25, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masazumi Matsuura
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Patent number: 6303520Abstract: An oxynitride film on the surface of a silicon or silicon germanium substrate is described where film is substantially an oxide film at the film oxide interface, and the nitrogen content of the film increases with the distance away from the substrate. The film is made by a process of rapidly processing a clean silicon wafer in an atmosphere of a nitrogen containing gas containing a very small percentage of oxygen containing gas.Type: GrantFiled: December 15, 1998Date of Patent: October 16, 2001Assignee: Mattson Technology, Inc.Inventors: Dim-Lee Kwong, Steven D. Marcus, Jeff Gelpey
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Publication number: 20010029114Abstract: A method of deposits polymeric layers of silicon oxynitride onto a surface of a semiconductor material substrate by a Chemical Vapor Deposition technique using at least one organosilane chemical precursor. In some embodiments, the organosilane comprises a combination of silicon, nitrogen, carbon and hydrogen, a specific example of which can be hexamethyldisiloxane. This technique can be used for all standard types of deposition, LPCVD, APCVD, SACVD and PECVD. Using HMDSN provides more uniform layers to be formed on the substrate, with increased quality. Specifically, step-coverage is better than in prior techniques, there is more uniformity of the layers, parameters of the deposition are easier to control, there is improved stoichiometry in the formed layers, and the production process uses materials that are more environmentally healthy than those used previously.Type: ApplicationFiled: February 27, 2001Publication date: October 11, 2001Inventors: Michele Vulpio, Cosimo Gerardi
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Patent number: 6261974Abstract: A DVS-BCB polymer film is grown by heating a divinyl siloxane bisbenzocyclobutene (DVS-BCB) monomer in a vaporization controller with continuously supplying; supplying a carrier gas and maintaining a partial pressure of the DVS-BCB monomer at a state lower than a saturated vapor pressure, thereby to vaporize the monomer; transporting the carrier gas containing the DVS-BCB monomer from the vaporization controller to an evacuated reaction chamber; and spraying the gas on the heated surface of a substrate in the reaction chamber.Type: GrantFiled: June 14, 1999Date of Patent: July 17, 2001Assignee: NEC CorporationInventors: Jun Kawahara, Yoshihiro Hayashi, Akinori Nakano, Mikio Shimizu, Tomohisa Nishikawa
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Patent number: 6255230Abstract: Disclosed is a method for modifying a film-forming surface of a substrate, which is capable removing a base surface dependency in forming a film on the film-forming surface of the substrate prior to formation of a film by a thermal CVD method using a reactant gas containing an ozone-containing gas containing ozone (O3) in oxygen (O2) and Tetra-Ethyl-Ortho-Silicate. The method comprises the step of modifying the film-forming surface 12a of the substrate 102 by allowing any one of ammonia, hydrazine, an amine, gases thereof and aqueous solutions thereof to contact with the surface of the substrate before forming an insulating film 13 on the surface 12a of the substrate 102.Type: GrantFiled: November 23, 1999Date of Patent: July 3, 2001Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Hiroshi Ikakura, Syunji Nishikawa, Noboru Tokumasu, Takayoshi Azumi
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Patent number: 6225241Abstract: To provide a fabrication method of compound semiconductor devices which can improve the problems of conventional MESFETs, such as the breakdown voltage degradation owing to increase of the gate leak current or the electron traps in the passivation film, the drain current decrease because of the gate-lag, or the threshold voltage dispersion caused by the interfacial tension, and easily restrain the emitter-size effect of conventional mesa type HBT without revising or complicating its epitaxial layer structure, a fabrication method according to the invention of a semiconductor device having a high-resistance film (9) covering a part of a surface other than electrodes (5, 6, and 7) of the semiconductor device comprises a step of depositing the high-resistance film (9) by way of catalytic CVD.Type: GrantFiled: January 15, 1998Date of Patent: May 1, 2001Assignee: NEC CorporationInventor: Yosuke Miyoshi
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Patent number: 6221734Abstract: A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.Type: GrantFiled: July 15, 1999Date of Patent: April 24, 2001Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chingfu Lin
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Patent number: 6156673Abstract: A ceramic layer, in particular having ferroelectric, dielectric or superconducting properties, uses compounds with a simple structure as precursors and only methanoic acid, acetic acid or propionic acid and, where appropriate, water as solvent.Type: GrantFiled: September 30, 1998Date of Patent: December 5, 2000Assignee: Infineon Technologies AGInventors: Frank Hintermaier, Carlos Mazure-Espejo
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Patent number: 6136703Abstract: A method of forming a phosphorus- and/or boron-containing silica layer, such as a PSG, BSG, or BPSG layer, on a substrate, such as a semiconductor substrate or substrate assembly.Type: GrantFiled: September 3, 1998Date of Patent: October 24, 2000Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 5976991Abstract: A process for the chemical vapor deposition of silicon dioxide and silicon oxynitride from reactant gases O.sub.2, O.sub.3, N.sub.2 O, NO, NO.sub.2, NH.sub.3 and a silane of the formula: (t-C.sub.4 H.sub.9 NH).sub.2 SiH.sub.2. A process whereby a stack of silicon containing dielectrics ranging from silicon nitride to silicon oxide may be deposited successively (at the same pressure and temperature) by changing the reactants O.sub.2, O.sub.3, N.sub.2 O, NO, NO.sub.2, NH.sub.3 while maintaing a constant flow of (t-C.sub.4 H.sub.9 NH).sub.2 SiH.sub.2. The films are suitable for use in the semiconductor and related industries.Type: GrantFiled: June 11, 1998Date of Patent: November 2, 1999Assignee: Air Products and Chemicals, Inc.Inventors: Ravi Kumar Laxman, David Allen Roberts, Arthur Kenneth Hochberg
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Patent number: 5968611Abstract: A method for chemical vapor deposition of a silicon-nitrogen based film onto a substrate includes introducing into a deposition chamber: (i) a substrate; (ii) a haloethylsilane precursor in the vapor state; and (iii) at least one nitrogen-containing reactant gas; and maintaining the deposition temperature within the chamber as from about 200.degree. C. to about 1000.degree. C. for a period of time sufficient to deposit a silicon-nitrogen based film on the substrate. Silicon-nitrogen based films are also included which are formed by chemical vapor deposition using a haloethylsilane precursor in a vapor state and at least one reactant gas comprising nitrogen.Type: GrantFiled: November 26, 1997Date of Patent: October 19, 1999Assignees: The Research Foundation of State University of New York, Gelest, Inc.Inventors: Alain E. Kaloyeros, Barry C. Arkles