Abstract: A method for moving resist stripper across the surface of a semiconductor substrate. The method includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.

Abstract: One aspect of the present invention relates to a system and method for mitigating surface abnormalities on a semiconductor structure. The method involves exposing the layer to a first plasma treatment in order to mitigate surface interactions between the layer and a subsequently formed photoresist without substantially etching the layer, the first plasma comprising oxygen and nitrogen; forming a patterned photoresist over the treated layer, the patterned photoresist being formed using 193 nm or lower radiation; and etching the treated layer through openings of the patterned photoresist. The system and method also includes a monitor processor for determining whether the plasma treatment has been administered and for adjusting the plasma treatment components. The monitor processor transmits a pulse, receives a reflected pulse response and analyzes the response.

Abstract: A method of forming a thin film transistor and its associated driver. A polysilicon layer, a gate oxide layer and a gate layer are formed on a substrate. A photoresist layer comprising of a top section and a base section is formed over the gate layer. The top section of the photoresist layer patterns out a thin film transistor gate while the base section outside the top section patterns out a lightly doped region or undoped region on each side of the gate. Complementary metal-oxide-semiconductor drivers are formed on each side of the thin film transistor.

Abstract: Three-dimensional structures of arbitrary shape are fabricated on the surface of a substrate through a series of processing steps wherein a monolithic structure is fabricated in successive layers. A first layer of photoresist material is spun onto a substrate surface and is exposed in a desired pattern corresponding to the shape of a final structure, at a corresponding cross-sectional level in the structure. The layer is not developed after exposure; instead, a second layer of photoresist material is deposited and is also exposed in a desired pattern. Subsequent layers are spun onto the top surface of prior layers and exposed, and upon completion of the succession of layers each defining corresponding levels of the desired structure, the layers are all developed at the same time leaving the three-dimensional structure.

Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the step of providing a semiconductor device having a contact pad and an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A first photoresist layer is deposited in a liquid state so that the first photoresist layer covers the under bump metallurgy. A second photoresist layer is deposited and the second photoresist layer is a dry film photoresist. The unexposed portions of the first photoresist layer are removed. The remaining portions of the first photoresist layers are removed. The electrically conductive material is reflown to provide a bump on the semiconductor device.

Abstract: A method of forming a thin film transistor and its associated driver. A polysilicon layer, a gate oxide layer and a gate layer are formed on a substrate. A photoresist layer comprising of a top section and a base section is formed over the gate layer. The top section of the photoresist layer patterns out a thin film transistor gate while the base section outside the top section patterns out a lightly doped region or undoped region on each side of the gate. Complementary metal-oxide-semiconductor drivers are formed on each side of the thin film transistor.

Abstract: A thin film transistor. The thin film transistor comprises a substrate, a dielectric layer and a polysilicon layer. A gate electrode is located on the substrate. A dielectric layer is located on the substrate and the gate electrode. A polysilicon layer is located on the dielectric layer. The polysilicon layer comprises a channel region and a doped region, wherein the channel region is located above the gate electrode and the doped region is adjacent to the channel region.

Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness.

Abstract: Disclosed is a method for fabricating a gate of semiconductor device. The disclosed comprises the steps of: sequentially forming a gate oxide layer, a gate material layer and a mask oxide layer on a semiconductor substrate; coating photopolymer having compound accelerator including polar functional group which absorbs HF vapor and ionize at a predetermined high temperature on the mask oxide layer; exposing the photopolymer and cross-linking the portion of exposed photopolymer; performing DFVP process by passing over HF vapor on the resultant substrate at a predetermined high temperature, thereby developing the portion of exposed photopolymer and etching the portion of mask oxide layer exposed by development of photopolymer simultaneously; removing the residual photopolymer; and etching the gate material layer and the gate oxide layer using the etched mask oxide layer.

Abstract: An integrated circuit fabrication process to pattern reduced feature size is disclosed herein. The process includes reducing the width of a patterned area of a patterned photoresist layer provided over a substrate before patterning the substrate. The patterned area is representative of a feature to be formed in the substrate. The width of the feature is reduced by an electron beam mediated heating and flowing of select areas of the patterned photoresist layer.

Abstract: A method is provided herein for trim etching a resist line in a plasma etch apparatus. The method provides a reduced rate of vertical direction etching of the resist, and an increased rate of horizontal direction etching of the resist, by applying a lower biasing power to the plasma etch apparatus that is conventionally used. The resulting resist has an increased height in relation to its width which adds to the structural integrity of the resist line and significantly reduces problems of discontinuity in the resist line.

Abstract: A process, and structure, used to monitor and control the level of photoresist removed at the periphery of a photoresist coated, semiconductor substrate, has been developed. A monitoring structure comprised of a group of graduated scribe marks, laser formed near the periphery of the semiconductor, monitoring substrate, is included with product semiconductor substrates, during the application of a photoresist layer, and during the photoresist edge bead removal procedure. The width of the photoresist edge bead, removed from product semiconductor substrates is determined via examination of the monitoring semiconductor substrate, in terms of measuring the level of graduated scribe marks, now exposed. This measurement determines the status of the product semiconductor substrates, in regards to continued processing, or rework.

Abstract: A method for forming a thin film transistor (TFT) is disclosed. A gate electrode, insulating layer, semiconductor layer, doped silicon layer and metal layer are formed on a substrate. A first photoresist layer with a first absorptivity is formed on the metal layer. A second photoresist layer with a second absorptivity is formed on the first photoresist layer. The second absorptivity is higher than the first absorptivity. An exposure process and a development process are performed to form a first pattern on the first photoresist layer and a second pattern on the second photoresist layer at the same time. An etching process is then performed to transfer the first pattern into the semiconductor layer, the doped silicon layer and the metal layer and transfer the second pattern into the doped silicon layer and the metal layer. After performing the etching process, the first photoresist layer and the second photoresist layer are removed.

Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

Abstract: The invention provides a method of manufacturing an electronic device including a vertical thin film transistor. A layer (8) of semiconductor material is provided over an insulated gate electrode (2). A negative resist (14) is used to define source and drain electrodes (26,28) which extend over the insulating layer (8) up to the step formed therein adjacent an edge (16A) of the gate electrode (2).

Abstract: A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least one region of the oxide layer. The substrate is then heated and descummed to remove any residue resulting from developing the photoresist. Alternatively, the photoresist layer may be cured prior to heating and descumming the substrate. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

Abstract: A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride includes, a) providing a substrate; b) providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface; c) covering the outer Si3N4 surface with a discrete photoresist adhesion layer; and d) depositing a layer of photoresist over the outer Si3N4 surface having the intermediate discrete adhesion layer thereover, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the intermediate discrete adhesion layer were not present.

Abstract: A method for moving resist stripper across the surface of a semiconductor substrate. The method includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.

Abstract: There is provided a laminated type photoelectric converter whose sensitivity is enhanced uniformly. In the photoelectric converter in which a photoelectric conversion device is laminated above a signal transfer device, the sensitivity is enhanced by providing bends on a lower electrode of the photoelectric conversion device and by confining light uniformly.

Abstract: By adopting an electrolytic plating method in forming the bump 6, the drawbacks of the conventional electrolytic plating method should be avoided. For example, the necessity of adopting a lead wiring for each wiring or the like should be eliminated. On the surface of a metal base (1), a resist film (first resist film) (4) having a negative pattern for forming a wiring film and a resist film (second resist film) (5) having a negative pattern for forming the bump or the pad is formed. By using these films as masks, electrolytic plating of a bump material film is conducted to form the bump (6). Subsequently, after only the second film (5) is removed. By using the first resist film (4) as a mask, electrolytic plating is then conducted to form a wiring film (7).

Abstract: Annealing technology is capable of heating a wafer on which a copper film is formed at a desired temperature within a short period of time. A light-shielding plate 106 of SiC (silicon carbide) exhibiting a flat emissivity irrespective of the wavelengths and emitting light over a wide band of wavelengths is interposed between the wafer 1 on which is formed a copper film having a high light reflection factor and lamps 102. The lamps 102 are turned on in this state so that the light-shielding plate 106 is heated, first, and, then, the wafer 1 is heated by light radiated from the light-shielding plate 106 that is heated, thereby to anneal the copper film.

Abstract: A method of forming a semiconductor device, includes forming at least one conductive island having a predetermined sidewall angle in a conductive substrate, forming a dielectric material over the at least one island, forming a conductive material over the dielectric material, and forming a contact to the conductive material and the at least one island.

Abstract: A process for the formation of a wiring pattern, which includes the steps of: exposing a resist through a photomask, the photomask having a pattern whose line width is equal to or less than a resolution limit; and developing the exposed resist to form a resist pattern having groove depressions on the surface thereof, the depressions not reaching the back of the resist pattern. The resist may be a positive resist in which case the resist pattern is formed on an underplate feed film; a plating metal is precipitated on the feed film in a region not covered by the resist pattern; the resist pattern is stripped after the precipitation; and the feed film is selectively removed in a region not covered by the plating metal. Alternatively, the resist may be a negative resist in which case the resist pattern is formed on a substrate; a metallic material is deposited on the resist pattern and the substrate; and the resist is stripped from the substrate to remove the overlying metallic material.

Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Abstract: A method for patterning a layer on a substrate can include projecting coherent radiation toward a reflector surface so that the coherent radiation is reflected off the reflector surface to provide a holographic projection of a desired image wherein the reflector surface includes information that corresponds to an inverse of the holographic projection of the desired image. The substrate including the layer can be maintained in the path of the reflected radiation so that the holographic projection is projected onto the layer. Related systems are also discussed.

Abstract: In one aspect, the invention provides a method of exposing a material from which photoresist cannot be substantially selectively removed utilizing photoresist. In one preferred implementation, a first material from which photoresist cannot be substantially selectively removed is formed over a substrate. At least two different material layers are formed over the first material. Photoresist is deposited over the two layers and an opening formed within the photoresist over an outermost of the two layers. First etching is conducted through the outermost of the two layers within the photoresist opening to outwardly expose an innermost of the two layers and form an exposure opening thereto. After the first etching, photoresist is stripped from the substrate. After the stripping, a second etching is conducted of the innermost of the two layers within the exposure opening.

Abstract: In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench.

Abstract: A method of fabricating a salicide gate is provided, wherein a logic region and a memory cell region are formed on a substrate. A plurality of polysilicon gates and adjoining source/drain regions are also formed in both regions. A protection layer is formed to cover the polysilicon gates and the source/drain regions, followed by forming a photoresist layer on the substrate. A blanket defocus exposure is then conducted, whereby a part of the protection layer on the top surface of the polysilicon gates in both regions is eventually removed. Another photoresist layer is formed in the memory cell region, while the protection layer in the logic region is removed. A self-aligned silicide process is then conducted to form the salicide gates in both regions, and to selectively forming salicide layers on the source/drain regions in the logic region only.

Abstract: A method for enhancing adhesion of photo-resist to silicon nitride surfaces is disclosed. An oxidation process is first performed on the surface of the semiconductor wafer using ozone-dissolved deionized water to transform most of the dangle bonds and Si-N bonds on the surface of the silicon nitride layer into Si-O bonds or Si-ON bonds. An HMDS layer is then formed on the surface of the silicon nitride layer. A photo-resist layer is next formed on the surface of the HMDS layer. Finally, a soft bake process is performed to remove solvents from the photo-resist layer and an exposure process is performed on the photo-resist layer to define a predetermined pattern in the photo-resist layer.

Abstract: An alternative to conventional SOI and dielectric filled trenches for electrical isolation of integrated circuits is disclosed. This has been achieved by using proton bombardment to form semi-insulating regions. For all embodiments, the process of the invention begins only after the integrated circuit has been fully formed. In a first embodiment, protons bombard the entire back surface of the wafer thereby forming a substrate of semi-insulating material (resistivity greater than 105 ohm cm) on which the active and passive components rest. In the second embodiment, isolation trenches are formed by bombarding from the top surface through a contact mask formed by means of LIGA or similar technology. The third embodiment is a combination of the first two wherein both isolation regions and the semi-insulating substrate are formed.

Abstract: A method for preventing gate oxide damage caused by post poly definition implantation is disclosed. It is shown that the antenna ratio that is correlatable to oxide damage can be reduced and made to approach zero by implementing a mask layout during ion implantation. This involves covering all of the polysilicon electrodes with a photoresist mask, and reducing the effective antenna ratio to zero, and performing ion implantation to form source/drain regions thereafter. In this manner, the dependency of ion implantation to pattern sensitivity is also removed.

Abstract: For instance, when a washing-free yet low-residue type of flux is coated on a solder resist film, soldering can be carried out while no solder balls remain on a circuit substrate.A photosensitive resin composition comprises a photopolymerizable and photosensitive resin having at least one of a carboxyl group and an onium group, a photopolymerizable reactive diluent, a photopolymerization initiator, a thermosetting component, and an inorganic powder having an average particle size of 2 .mu.m to 20 .mu.m. A cured film thereof is used as a solder resist film for circuit substrate fabrication.A washing-free yet low-residue type of flux is so uniformly coated on the solder resist film that soldering can be carried out in the absence of any solder ball.

Abstract: A method for stripping positive photoresist from a keyhole 17 in a passivation layer 18 before a heating process using NMP solvent strips after a photoresist strip. The process is summarized by the 5 steps as follows: (1) Photoresist strip 1 (e.g., EKC 830), (2) Photoresist strip 2 (e.g., EKC 830 photoresist stripper), (3) N-methly-2-pyrolidone (NMP) solvent strip-agitated (solvent is preferably the same solvent in the photoresist stripper (1 &2) (4) NMP solvent strip-agitated and (5) H.sub.2 O rinse. The NMP solvent strip steps (3) and (4) remove photoresist residue (16, FIG. 1) in the key hole 17. This prevents the formation of photoresist extrusions 24 while annealing the metal lines 14.

Abstract: A self-aligned contact process for fabricating semiconductor devices on a semiconductor substrate is described. The present process comprises providing two gates structure on a semiconductor substrate, wherein the gate structure comprises a gate and a passivation layer on the top surface thereof. A buffer layer is conformally overlaid on the gate structure, passivation layer and the semiconductor substrate. A photoresist material is formed on the semiconductor substrate to a level between the top surface of the passivation layer and interface between the passivation layer and gate. The buffer layer is removed to the level of the photoresist layer. Next, the photoresist material is removed. A spacer is formed on the sidewall of the buffer layer and the passivation layer of the gate structure. An insulating layer is formed on the semiconductor substrate and then, a contact opening is formed therein to expose the semiconductor substrate.

Abstract: The present invention discloses a method for fabricating a MOSFET device supported on a substrate.

Abstract: Dielectric planarization is achieved by Defocus and under exposure of photoresist. The photoresist may be etched at the same rate as the dielectric, thereby yielding a smooth or planarized dielectric.

Abstract: A method for forming dual damascene metallic structure that utilizes the formation of a protective photoresist layer at the bottom of a vertical window to prevent damages to a device region in the substrate when subsequent etching operation is carried out to form a horizontal trench pattern. The protective photoresist layer at the bottom of the vertical window is formed by irradiating the photoresist layer with a dose of radiation having energy level insufficient to chemically dissociate the photoactive molecules of the photoresist layer near the bottom of the vertical window.

Abstract: A method of forming a resin film pattern, comprising the steps of (A) producing a resin film layer soluble in an organic solvent, on a substrate such as silicon wafer, even engineering plastics being usable as a resin of the resin film layer; (B) forming a resist image of desired pattern on the organic solvent-soluble resin film layer; (C) etching each of those parts of the organic solvent-soluble resin film layer which are not covered with the resist image, using the organic solvent; and (D) removing the resist image from the resulting, organic solvent-soluble resin film layer using a resist image remover which contains 0.01-10.0 parts-by-weight of arylsulfonic acid with respect to 100 parts-by-weight of solvent having a solubility parameter of 5.0-11.0. The step (D) may well be followed by the step (E) of processing the substrate which includes the resin film layer, with alcohol.

Abstract: A method for manufacturing phase-shifting masks utilizing a photolithographic process and sidewall spacers to fabricate a phase-shifting layer. The method provides precise control over the shape and size of the resulting phase-shifting layer, and thus, simplifies photomask production.

Abstract: A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride includes, a) providing a substrate; b) providing an outer layer of Si.sub.3 N.sub.4 outwardly of the substrate, the outer Si.sub.3 N.sub.4 layer having an outer surface; c) covering the outer Si.sub.3 N.sub.4 surface with a discrete photoresist adhesion layer; and d) depositing a layer of photoresist over the outer Si.sub.3 N.sub.4 surface having the intermediate discrete adhesion layer thereover, the photoresist adhering to the Si.sub.3 N.sub.4 layer with a greater degree of adhesion than would otherwise occur if the intermediate discrete adhesion layer were not present. Further, a method in accordance with the invention includes, i) providing an outer layer of Si.sub.3 N.sub.4 outwardly of the substrate, the outer Si.sub.3 N.sub.4 layer having an outer surface; ii) transforming the outer Si.sub.3 N.sub.

Abstract: A method of manufacturing a buried contact is disclosed, wherein a thin silicon oxide layer is formed on the silicon substrate. The thin oxide functions as a gate dielectric. Subsequently, a thin first polysilicon layer is formed on the thin silicon oxide layer. Then, a buried contact opening is defined by a first photoresist mask. The portion of the thin polysilicon layer exposed through the first photoresist mask and the thin silicon oxide layer underneath the exposed thin polysilicon are anisotropically etched to forma buried contact hole. An ion implantation is performed into the substrate throughout the buried contact hole to form an N+region. The first photoresist mask is removed and a layer of undoped silicon oxide is deposited on the entire surface. An anisotropic etching is used to etch the undoped silicon oxide. The etching depth can be controlled by this process. Residual amounts of undoped silicon oxide are retained on the vertical edges of the buried contact hole to act as spacers.

Abstract: A method of removing a resist layer formed on a substrate wherein the resist layer includes an ion-implanted upper region. The method includes hydrogenating the ion implanted upper region of the resist layer resulting in the hydrogenated ion-implanted upper region. The resist layer, including the hydrogenated ion-implanted upper region is then removed. A hydrogenation of the ion-implanted upper region may be performed by immersing the resist layer, including the ion-implanted upper region, into pressurized boiling water, and/or treating the ion-implanted upper region with pressurized water vapor.

Abstract: A process for separating electronic devices connected with one another in a body, the process including thinning the side of the body remote from the electronic devices, separating the electronic devices, and testing electrical parameters of the electronic devices after the thinning of the body. The handling of the body is improved by applying to the side of the body containing the electronic devices, prior to the thinning process, an electrically nonconductive auxiliary layer in which respective contact openings are formed above the electronic devices to expose the contact(s) of the respective electronic device.

Abstract: A method is provided for manufacturing a polysilicon with a relatively small line width. The method includes steps of: a) forming a first layer of photoresist with a line pattern having a first line interval and a first line width over the polysilicon; b) etching a portion of the polysilicon for forming the polysilicon with a second line interval x and a second line width y respectively equal to the first line interval and the first line width; c) forming a second layer of photoresist with a third line interval and a third line width over the polysilicon; d) etching another portion of the polysilicon for forming the polysilicon with a fourth line interval x`, equal to the third line interval, and a fourth line width y`; e) depositing a polysilicon film over the polysilicon with the relatively small line width; and f) etching a portion of the polysilicon film to form sidewalls of the polysilicon with the relatively small line width for adjusting the relatively small line width of the polysilicon.

Abstract: A fourth impurity region having a smaller junction depth than that of the second impurity region, and having a third impurity concentration which is lower than that of the second impurity region is formed between the first impurity region and second impurity region. A fifth impurity region whose junction depth is smaller than that of the second impurity region, and having a third impurity concentration is formed between the first impurity region and second impurity region. Since the intensity of the electric field applied to the drain region is reduced, transistor characteristics are improved. Also, the integration of a semiconductor device is increased by reducing the layout space.

Abstract: The subject invention is directed to a method for producing semiconductor wafers using a simplified hole interconnect process. These wafers include at least one interconnect layer located on a contact or via layer. As contrasted with the semiconductor wafers produced according to the prior art method described above, the contact or via layer of this invention includes a plurality of patterned openings formed therein which are in substantial alignment without offset with each other.

Abstract: A method for dividing a plural number of semiconductor devices into individual semiconductor devices to increase the number of chips manufactured per wafer by forming scribing lines in narrow width. Isotropic etching, such as plasma etching in CF.sub.4, O.sub.2 gas, is carried out by utilizing resist layer 31c to 35a as a mask. Then by carrying out heat treatment the resist layer 31 to 35a loosens, and as a result, side walls of the passivation layer 15 are covered with the resist layer. N type epitaxial layer 4 of the openings 24 and 25 for the scribing line is etched by carrying out isotropic plasma etching once again. Since the side walls of the passivation layer 15 of the openings 24 and 25 for the scribing line are covered with the resist layer, the openings 24 and 25 are not etched in the horizontal direction.

Abstract: A method for manufacturing an array of stacked capacitors with increased capacitance for DRAM devices was achieved. The invention utilizes two photoresist masking steps and a series of self-aligning etch back steps to form a very high density array of bottom capacitor (node) electrodes. The method involves depositing and planarizing an insulating layer over the DRAM cell areas in which node contact openings (first photoresist mask) are etched to the node contact areas of the FETs. A polysilicon layer is deposited, filling the node contact openings, and patterned (second photoresist mask) to define the outer perimeters of bottom electrodes and the polysilicon layer is recessed by partially plasma etching. The second patterned photoresist mask is then laterally recessed by ashing in O.sub.2 to expose the polysilicon. A second anisotropic etch is used to form a bottom electrode having a vertical center portion and a wider base area.

Abstract: An improved method and apparatus for applying a primer to a wafer surface prior to coating the wafer with photoresist is provided. The method comprises priming a wafer with HMDS, removing the wafer from the priming chamber, and closing the chamber. Next, the chamber, piping and primer source are evacuated. The bubbler canister, piping and wafer chamber are held at a pressure of about 15 inches H.sub.2 O while the priming tool is idle between wafer priming operations. By maintaining the vaporizer, piping and wafer chamber at a partial vacuum, the primer will be prevented from condensing and forming harmful droplets on the wafer surface. The invention prevents primer condensation from forming on the wafer, thus improving photolithographic yields and device yields.

Abstract: A method for fabricating an InP diffraction grating for a distributed feedback semiconductor laser includes the steps of applying an electron beam resist on a semiconductor substrate, giving electron beam exposure to the electron beam resist and controlling heights of resist patterns by using fixed electron beam diameters but by varying incident electron doses. The semiconductor substrate is dry-etched. The electron beam exposure is such that the incident electron doses are made larger at a center portion than at portions towards two sides of the diffraction grating. Due to the proximity effect, the resist patterns after development will have a lower height and a narrower width at portions at which the incident electron doses are increased and, conversely, a higher height and a wider width at portions at which the incident electron doses are decreased.