Abstract: The present invention provides methods for producing TPPA having low level of metal ions, utilizing treated ion exchange resins. A method is also provided for producing photoresist composition having a very low level of metal ions from such TPPA for producing semiconductor devices using such photoresist compositions.
Abstract: In a method for manufacturing a semiconductor device, layer including a first portion having a first height and a second portion having a second height different from the first height is formed on a substrate. Then, an image formation beam is irradiated onto the layer to form first and second patterns on the first and second portions, respectively. A minimum feature size of the first pattern is different from that of the second pattern.
Abstract: A structure of openings is produced in two or more layers of silylated, polyimide photoresist. Openings in subsequent layers, which overlap previous openings, are of larger size. Then the structure is transferred to an organic substrate using oxygen plasma etching with up to 3% CF.sub.4. The smallest opening transferred to the substrate extends through the substrate.
Type:
Grant
Filed:
May 5, 1993
Date of Patent:
June 3, 1997
Assignee:
International Business Machines
Inventors:
Johann Bartha, Johann Greschner, Karl H. Probst, Gerhard Schmid
Abstract: A class of silicon-containing materials display excellent sensitively in the ultraviolet and deep ultraviolet for the formation of patterns by radiation induced conversion into glassy compounds. Materials are depositable from the vapor phase and show excellent promise for use such as resists in the fabrication of electronic and optical devices.
Abstract: A heat-treating method of heating and cooling a substrate comprising the steps of carrying the wafer into a heat-treating section by a main arm and mounting the wafer on a heating stage, heating the wafer mounted on the heating stage, lifting the wafer thus heated from the heating stage, approaching a cooling holder to the wafer thus lifted to cool the wafer above the heating stage, and carrying the cooled wafer from above the heating stage.
Type:
Grant
Filed:
October 3, 1995
Date of Patent:
April 15, 1997
Assignees:
Tokyo Electron Limited, Tokyo Electron Kyushu Limited
Abstract: A method for forming a residue free patterned conductor layer upon a high step height integrated circuit substrate. First, there is provided a semiconductor substrate having formed thereon a high step height patterned integrated circuit layer. Formed upon the high step height patterned integrated circuit layer is a blanket conductor layer, and formed upon the blanket conductor layer is a patterned photoresist layer. The portions of the blanket conductor layer exposed through the patterned photoresist layer are etched through an anisotropic etch process to leave remaining a patterned conductor layer upon the surface of the high step height patterned integrated circuit layer and conductor layer residues at a lower step level of the high step height patterned integrated circuit layer. The patterned photoresist layer is then reflowed to cover exposed edges of the patterned conductor layer.