Abstract: Dispersing directions of oscillation frequency variable ranges of all voltage controlled oscillators provided in an integrated circuit are uniformed, and not only a range covering a frequency regardless of whether a dispersion occurs or not, but also a range covering the frequency only in a case where the dispersion occurs is used as the frequency variable range of the voltage controlled oscillator, and the frequency variable ranges of the voltage controlled oscillators are set so as to be successive with respect to each other, so that a small number of voltage controlled oscillators can cover a wide frequency variable range. Thus, the integrated circuit having voltage controlled oscillators therein is miniaturized.

Abstract: The present invention helps to mitigate and reduce the amount of interfering signals (e.g. RF leakage) that enter the phase detector of a phase locked loop by acting as a less than perfect sampler. This is accomplished by introducing a time jitter to the signal edges that enter the phase detector input. A phase detector can also be made to act as a less than perfect sampler by intentionally introducing an interfering signal. For example, a small interfering analog signal can be introduced with a different frequency from the reference frequency already present in the PLL. The interfering signal will cause the stable internal signal to vary slightly in time at the rate of the interfering signal frequency. It is this signal variation and jitter introduced on the signal edges entering the phase detector input that induces the phase detector to act as a less than perfect sampler.

Abstract: When a cellular phone terminal is powered on, it immediately receives a reference signal (non-modulated reference frequency signal for correcting a crystal oscillation circuit) for correcting the reception frequency of a radio signal transmitted from a base station at all times, and corrects the error of the reception frequency on the basis of the reference signal received. After the error of the reception frequency is corrected, the cellular phone terminal makes normal communications with the base station.

Abstract: The frequency error of an oscillator is minimized by characterizing the operating environment of the oscillator. An electronic device monitors parameters that are determined to have an effect on the frequency accuracy of the internal frequency source. Temperature is one parameter known to have an effect on the frequency of the internal frequency source and a primary contributor to device temperature is the RF Power Amplifier (PA). The electronic device collects and stores the activity level of the PA. The effective PA duty cycle over a predetermined period of time is calculated. The LO operating environment is stabilized by operating the PA at the calculated duty cycle when the LO is required to operate in a high stability mode.

Abstract: A dual-mode wireless telephone which is capable of operating on two different bands of frequencies. The dual-mode telephone having a single phase lock loop combined with a single local oscillator that can select between two frequencies in two widely spread output frequency bands such as the bands in the GSM and DCS standards. A switch in the phase lock loop selectively swaps an UP signal and a DOWN signal to achieve either a high side lock or a low side lock. When the phase lock loop is high side locked, a target frequency in a higher band of output frequencies is generated. When the phase lock loop is low side locked, a target frequency in a lower band of output frequencies is generated.

Abstract: An electronic tuning system includes an electronic tuner for adjusting the predetermined control voltage of a voltage controlled oscillator (VCO) to tune the local frequency signal to radio waves on an arbitrary channel in accordance with channel selection information. A booster circuit boosts a source voltage to generate a boosted voltage in order to ensure the predetermined control voltage. A non-volatile memory stores the channel selection information in response to a predetermined write voltage. The boosted voltage of the booster circuit is utilized as the predetermined write voltage.

Abstract: A radio FM receiver is provided with a voltage-controlled oscillator which can be connected via a frequency 2-divider to a quadrature combination circuit for transforming down the frequencies of received radio signals and for supplying quadrature output signals. The receiver is further provided with detection and sound reproduction means connected to this combination circuit. A frequency 3-divider is also present, by means of which the oscillator can be connected to the combination circuit, as well as switching means for connecting the mixer element to the oscillator either through the 2-divider or through the 3-divider.

Abstract: A radio-frequency receiver mixes a received radio-frequency signal with a local signal in a mixer to convert the radio-frequency signal into an intermediate-frequency signal or baseband signal. In this radio-frequency receiver, a frequency multiplier circuit multiplies the frequency of the output signal of a VCO and feeds the resulting signal as the local signal to the mixer. The output level of the frequency multiplier circuit is switched by a level switcher circuit, which is controlled by a tuning controller according to the received frequency. The controller also controls a PLL circuit for tuning.

Abstract: A tuner including an oscillator, a divider means for dividing the oscillator signal and a mixer, suitable for global tuner applications, i.e. U.S.A./Europe/Japan without any hardware change, the divider is switchable between at least two values.

Abstract: A frequency synthesizer device comprising a PLL circuit (9) and a frequency-division ratio control circuit (5). The PLL circuit (9) includes a phase comparator (1), a low-pass filter (2), a voltage-controlled oscillator (3), and a variable frequency divider (4). The frequency-division ratio control circuit (5) controls the variable frequency divider (4) such that a frequency division ratio of the variable frequency divider (4) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider (4) and an output fdiv2 obtained via a delay element (10) are used as clocks of an accumulator portion (81) in the frequency-division ratio control circuit (5).

Abstract: A frequency synthesizer type receiver requiring small power consumption and maintaining excellent receiving performance. In the frequency synthesizer type receiver, a reception frequency thereof is set based on an oscillatory output of a PLL circuit. When the oscillation frequency of the PLL circuit is stabilized, a control voltage can be supplied to a voltage-controlled oscillator in the PLL circuit from a controller situated outside of the PLL circuit. The tuned state of a reception unit is measured at this time. If a shift in the reception frequency is detected based on the measured value, the control voltage to be supplied to the voltage-controlled oscillator is corrected.

Abstract: In a television receiver having a tuner 2 for converting a received signal from an antenna 1 to an intermediate frequency signal and supplying the intermediate frequency signal to a homodyne detector circuit through a filter device to extract a video signal, a variable frequency oscillator is provided for changing the frequency of the intermediate frequency signal such that the frequency of beat components between a local oscillating signal of the tuner and a harmonic signal of the intermediate frequency signal is coincident with a trap frequency of the filter device. The occurrence of interference due to the intermediate frequency signal introducing into the antenna can be prevented by a simple configuration.

Abstract: Methods and systems are provided for frequency generation suitable for use in wireless devices capable of operating at multiple frequencies. Such systems may change the loop gain of an automatic frequency control loop based on the operating frequency of the wireless device. Furthermore, such a frequency dependent loop gain may be carried out by the selection of subroutines with differing loop gains associated with the subroutines. Furthermore, the loop gain may also be temperature compensated based on the temperature of the wireless device and/or the operating frequency of the device.

Abstract: A signal generator 5 which generates one of two input signals to a frequency mixing circuit 1 for outputting a signal having a frequency which is a difference between frequencies of the two signals or a sum thereof. In the present invention, an attenuating circuit 6 for attenuating an output signal from a voltage-controlled oscillator 2 for generating one of the input signals as well as a filter circuit 7 for limiting a frequency band of an output signal from the attenuating circuit are interposed between the frequency mixing circuit and a voltage-controlled oscillator 2.

Abstract: A mobile communication terminal device of the present invention includes: a voltage detector for detecting a battery voltage at the time of a voltage drop; a correction phase storage section for storing pieces of correction phase information each having a characteristic opposite to that of a phase error in a carrier wave produced due to a drop in the battery voltage; a correction phase outputting section for selecting correction phase information based on the battery voltage at the time of the voltage drop and outputting the selected correction phase information to a baseband modulator to change phase information in a baseband signal; and a modulator for modulating a carrier wave according to the baseband signal output from the correction phase outputting section so as to cancel the phase error included in the carrier wave.

Abstract: Radio terminal equipment is provided with an oscillator connected to a receiving circuit, a DPLL 16 for detecting and correcting the phase difference between the received frequency and the oscillation frequency of the oscillator, a switch for connecting a capacitor to or disconnecting from the oscillator, and control means 17 for effecting ON-OFF control of the switch based on the output signal from the DPLL 16.

Abstract: A digital receiver has a local oscillator that provides a local oscillator signal, a frequency offset detector that provides a frequency offset signal that is representative of a difference between the local oscillator signal and a desired tuning frequency of the digital receiver, and a frequency controller that controls the frequency of the local oscillator on the basis of a stored control value. The frequency controller separately derives a short term drift compensation signal and a long term drift compensation signal from the frequency offset signal, at a first interval updates the stored control value on the basis of the derived short term drift compensation signal, and at a second interval updates the stored control value on the basis of the long term drift compensation signal. The first interval is substantially shorter than the second interval.

Abstract: A homodyne receiver according to the present invention includes a signal input and first and second mixers coupled to the signal input. A local oscillator provides a reference signal at the frequency of modulation of the input signal. The reference signal output by the local oscillator is passed through a switchable phase change element, the output of which is coupled directly to the first mixer and indirectly to the second mixer through a second phase change element. The switchable phase change element changes the phase of an input signal by a predetermined phase based on the state of a control input, such that the output of the phase change element in one state is &pgr; radians out of phase with the output of the phase change element in the other state. The second phase change element changes the phase of an input signal by &pgr;/2 radians. The outputs of the mixers are coupled to a pair of switchable inverters and low pass filters.

Abstract: The present invention relates to the automatic frequency control circuit and the method of automatic frequency control. The automatic frequency control circuit for processing frequency control of a received signal frequency based on an incoming received signal comprises a first control circuit for processing frequency control based on a precision counter by using the incoming received signal and a second control circuit for processing frequency control based on a coarse counter by using the incoming received signal, wherein the first control circuit and the second control circuit are configured to be used interchangeably in response to the incoming received signal. By employing the circuit which directly counts the received signal and the circuit which counts the regenerative carrier signal in combination, the follow up range of the automatic frequency control circuit is thus expanded.

Abstract: When attempting to reduce the number of battery cells in cellular telephones, a frequency synthesizer or phase locked loop located within the cellular telephone will output an increasing amount of noise. In order to reduce the amount of noise output when reducing the number of battery cells in such systems, the present invention employs a voltage step up device which effectively increases the voltage range of a voltage controlled oscillator within the frequency synthesizer. To further reduce the noise, the voltage step-up unit is employed with passive elements thus reducing the noise further and optimizing the output of the phase locked loop. Several different designs are discussed to further reduce space requirements and increase programmability of the system.

Abstract: A method and system for receiving a signal in a received frequency and shifting the received frequency to become a desired frequency is provided. The system includes a controllable oscillator for generating a first internal frequency, a frequency estimating unit connected to the controllable oscillator, a first frequency shift unit, connected to the controllable oscillator and to the frequency estimating unit, for shifting the received frequency according to the first internal frequency, thereby obtaining an initially shifted frequency and a second frequency shift unit connected to the first frequency shift unit and the frequency estimating unit for shifting the initially shifted frequency. The frequency estimating unit determines a total frequency shift value from the desired frequency, the received frequency and the first internal frequency and it also determines a first frequency shift value and a second frequency shift value from the total frequency shift value.

Abstract: A radio pager having a frequency correcting function of the present invention includes an arithmetic section for determining, during an interval between the start and the end of a particular signal, a center amplitude based on the maximum and minimum values of the signal, producing a difference between the center amplitude and a reference voltage, and feeding back the resulting center voltage data to a quartz oscillation section or reference oscillation section. As a result, the oscillation frequency of the oscillation section is automatically corrected. This insures an accurate voltage amplitude and therefore accurate decision on a multilevel digital signal.

Abstract: A new architecture for such a type of synthesizer is proposed not having the drawbacks of such known synthesizers and having the same phase noise properties as ordinary integer divide by N synthesizers. The novel architecture has a main PLL with a first integer frequency divider in its feedback loop and further an auxiliary PLL having a second integer frequency divider in its feedback loop.

Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an x.sup.th harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.

Abstract: The invention concerns a method and apparatus for providing frequency control of an oscillator circuit. The apparatus includes an oscillator (9), an error estimator (10) f.sub.r producing a set of error estimates and a median filter (11) for producing a median value from the set of estimates. The median filter (11) is connected to the oscillator (9) which is responsive to the median value to vary its frequency thereby reducing the error.

Abstract: A receiver has a crystal oscillator (10) whose frequency can be adjusted in response to temperature compensation (TC) and automatic frequency control (afc) signals. The TC and afc signals are summed and applied to an op-amp (70) having a fixed gain functioning as a current to voltage converter. An output of the op-amp (70) is applied to the crystal oscillator (10). If the receiver is switched--on and--off in accordance with say a time division protocol, the output of the op-amp (70) is applied by way of a switch (72) to a storage circuit (30,C) which when the switch is open applies a bias voltage on the crystal oscillator (10) to maintain its output frequency.

Abstract: A high frequency apparatus for receiving digital modulated high frequency signal which withstands vibration and is easy to adjust for tuning, yet presents clear oscillation signal. The invented apparatus has an input terminal(101), a mixer(104) which receives at one input the signals supplied to input terminal(101) and at the other input an output signal of local oscillator(103), and output terminals(107,108) to which the output signal of mixer(104) is delivered. A voltage controlled oscillator constituting said local oscillator(103) has an oscillating section and a tuning section; the tuning section has a movable conductive member(119) and a gluing agent(120) for maintaining a state after adjustment. Control loop has a high loop band width which is large enough so as the noise of local oscillator(103) is not dominated by noise of the above mentioned voltage controlled oscillator.

Abstract: A high frequency apparatus for receiving digitally modulated high frequency signals withstands vibration and has a simple tuning adjustment. The apparatus has an input terminal, a mixer which mixes the input signals and an output signal from a local oscillator, a voltage controlled oscillator which includes the local oscillator, an oscillating section, a movable conductive member and, a gluing agent for maintaining an adjusted state, and a control loop having a high loop band width which is large enough so that noise of the local oscillator is not dominated by noise of the voltage controlled oscillator.

Abstract: The present invention relates to a frequency control apparatus for a television and a video cassette tape recorder, and more particularly to an automatic frequency control method wherein a frequency value of a voltage controlled oscillator is increased or decreased and stored by determining whether an oscillator is in a range capable of operating a phase locked loop when an oscillation frequency of the voltage controlled oscillator of the phase locked loop is not synchronized with the intermediate frequency when a frequency is automatically controlled by comparing phases and frequencies of the phase locked loop and the intermediate frequency.

Abstract: A receiver has an oscillator for generating an oscillating signal at an oscillating frequency in accordance with an oscillation control signal, and receives a radio signal at a tuning frequency corresponding to the oscillating signal to demodulate the received radio signal. The receiver further includes a first frequency control loop system for generating a first control signal indicative of the difference in phase between a comparison signal generated by dividing the oscillating signal on the basis of the information on a channel selection frequency and a reference signal, and a second frequency control loop system for generating a second control signal indicative of a frequency difference between the oscillating frequency of the oscillating signal and the channel selection frequency. Either the first control signal or the second control signal is selectively supplied to the oscillator as an oscillation control signal.

Abstract: The invention relates to an oscillator OSC intended to provide an output signal having a frequency which is variable as a function of a tuning voltage Vtun. The oscillator OSC includes a passive part having two series-arranged variable capacitances Cs, biased by the tuning voltage Vtun, and connected to a power supply VCC via two inductances Lext, and an active part having a first transistor T1 and a second transistor T2 whose collectors are connected to the output terminals C1 and C2 of the passive part, the base of one transistor being connected to the collector of the other transistor via a coupling capacitor Cfb. According to the invention, the passive part includes two high-pass filters, each being inserted between one of the output terminals S1 or S2 and one of the variable capacitances Cs, which allows a reduction of the active part's sensitivity to low-frequency noise.

Abstract: A voltage controlled oscillator (1) comprising a voltage controllable variable resonant circuit (2) having a control input (Vctrl), a positive feedback input (6) and a controllable variable frequency output (7). There is an amplifier (3) having an amplifier input coupled to the controllable variable frequency output (7). A positive feedback path (4) couples the amplifier (3) to the positive feedback input (6) and there is selectable load (5) in parallel with the positive feedback path (4) for selectively reducing the SideBand Noise Ratio.

Abstract: A high-performance voltage controlled oscillator without use of variable capacitance (varicap) diodes which is easy in fabrication in an semiconductor IC form. The voltage controlled oscillator includes:a differential amplifier having a differential pair of transistors (Q.sub.1, Q.sub.2); an LC resonance circuit having a coil (L.sub.0) and a capacitor (C.sub.0); a phase shift circuit for receiving a differential output of the differential amplifier via a buffer of transistors (Q.sub.3, Q.sub.4) and for providing its output for the differential amplifier in a positive feedback mode; and a current control circuit for variably controlling an operating current (Ie) of the phase shift circuit according to a controlled voltage applied from a circuit other than those in the voltage controlled oscillator.

Abstract: A telecommunications unit has an oscillating crystal as frequency standard, in which the temperature response of the oscillating crystal is counteracted by a compensation mode inserted into the unit's microprocessor prior to execution of the operating program.

Abstract: The invention relates to a transceiver for generating complex I/Q-signals on a transmission frequency (f.sub.TX) and for receiving them on a reception frequency (f.sub.RX). The device comprises a first frequency synthesizer (41) for forming a first mixer signal (f.sub.LI) for the mixer (42) of the first branch that mixes the I-component of the received signal into a lower-frequency I-signal, and a second frequency synthesizer (411, 49, 46) for forming a second mixer signal (f.sub.LQ) for the mixer (421) of the second branch that mixes the Q-component of the received signal into a lower-frequency Q-signal. The device further comprises control means (45) first for directing the phase of the first (f.sub.LI) and the second (f.sub.LQ) mixer signals into the same phase in the mixing effects thereof and, thereafter, into a 90 degree mutual phase shift in the mixing effects thereof when receiving signals for bringing the lower-frequency I- and Q-signals into a 90 degree mutual phase shift.

Abstract: Frequency mismatch between the carrier oscillator (18) of a radio transmitter (10) and a local oscillator (44) of a radio receiver is eliminated. The transmitter generates a mismatch correction signal (54), modulates it with the carrier, and transmits to the receiver. The receiver demodulates the received signal and generates a pulse train (52) having a duty cycle indicative of the frequency deviation. A digital logic unit (42) calculates the magnitude and direction of the frequency deviation, and adjusts the local oscillator to match the carrier frequency.

Abstract: In a receiver of the present invention, a local oscillator frequency, used as a basis for a reception unit to demodulate a received signal, is generated by a local oscillator based on a reference frequency, which is generated by a voltage-controlled oscillator whose oscillation frequency is adjusted by a control voltage applied thereto. The control voltage is prescribed by a decoding unit which monitors a reception electric field intensity (RSSi) or an error rate in the reception unit. The control voltage is adjusted in a manner to increase the reception electric field intensity (RSSi) or reduce the error rate. When the local oscillator frequency experiences a large deviation and the signal cannot be received with good reception sensitivity, the decoding unit generates a control voltage in a manner so as to eliminate the deviation and applies the generated control voltage to the voltage-controlled oscillator for automatically adjusting the local oscillator frequency to a level having a reduced deviation.

Abstract: The present invention relates to circuitry for a receiver having a low cost filter using automatic alignment of the center frequency of signals input to the filter to suppress noise and out-of-band signals from the filter output over a narrow bandwidth. An RF input signal to the receiver is downconverted to an IF frequency using a VCO, and the IF signal is provided to the low cost filter. The output of the filter is input to a frequency correction circuit and a distortion detection circuit. The distortion detection circuit provides an error signal including positive frequency shift errors determined from digital ones identified from the filter output signal, and negative frequency shift error signals determined from digital zeros in the filter output signal.

Abstract: A transmitting and receiving apparatus configured in superheterodyne form, includes a receiving circuit for receiving a signal on one channel of a predetermined pair of channels and a transmitting circuit for transmitting a signal on the other channel of the predetermined pair of channels. The receiving circuit has a first voltage-controlled oscillator including a first oscillating transistor and generating a local oscillated signal used for receiving the signal on one of the channels, and a first current control means for controlling a collector current of the first oscillating transistor. The transmitting circuit has a second voltage-controlled oscillator including a second oscillating transistor and generating a signal of the frequency of the other channel, and a second current control means for controlling a collector current of the second oscillating transistor.

Abstract: The device includes a first frequency synthesizer loop with fractional division to a apply a first wide frequency band transposition signal to an input of the first mixing stage of the receiver, a second phase-lock frequency synthesizer loop to apply a second narrow frequency band transposition signal to an input of the second mixer stage of the receiver and a common frequency source coupled to the first loop and to the second loop for the application, to their reference inputs, of a frequency reference signal. Application to wideband (20 MHz to GHz) V/UHF receivers.

Abstract: A reference oscillator (118) in a communication device (100) such as a radiotelephone is controlled by temperature compensating the reference oscillator (118). At the time of manufacture, characterizing data are stored in non-volatile memory (128) in the communication device (100). When the communication device (100) is powered up, the characterizing data are read and used to provide an initial correction (206) to the output frequency of the reference oscillator (118). Subsequently, an automatic frequency control operation is performed using the RF signal received from a remote transmitter as a reference signal. A frequency correction is determined (214) in the form of a frequency step size and step direction. The output frequency of the reference oscillator is repeatedly stepped until frequency error is minimized.

Abstract: A frequency synthesizer loop includes a first voltage controlled oscillator and a first divider circuit for dividing a frequency of an output signal generated by the first voltage controlled oscillator by a factor of N. The synthesizer loop further includes a phase/frequency detector circuit, a loop filter circuit, a summing circuit, a feedforward amplifier, a second voltage controlled oscillator, and a second divider circuit, wherein the second divider circuit divides a frequency of a second output signal generated by the second voltage controlled oscillator by a factor of M. The synthesizer loop also includes a microprocessor for varying the value M in response to a voltage input, such that the microprocessor varies the value of M to keep the first voltage in the middle of a range of the second voltage controlled oscillator.

Abstract: A temperature compensation circuit (10) for a crystal oscillator programmed by a single component (12), such as a resistor. The component (12) provides a voltage to an A/D converter (26). The digital signals (28) from the A/D converter (26) are divided and directed to separate signal generators (44,46,48,50,56) which control different aspects of the temperature compensation circuit (10). These aspects include a hot, cold, linear, balance and warp adjustment. The temperature compensation circuit (10) drives a varactor (18) which reactively loads a crystal oscillator (14) to compensate frequency over temperature. By using a single component (12) to program the circuit (10), an EEPROM is no longer needed which saves IC space and reduces IC processing steps, and the use of multiple external components to perform a compensation is avoided which further saves physical space.

Abstract: A reception clock signal used for a data sampling unit to sample received data is generated by a reception clock generator based on a reference clock signal, which is generated by a reference clock generator based on a reference bit rate frequency. The reference bit rate frequency is produced by a reference oscillator which is controlled by a control voltage. The control voltage is generated by a phase difference-to-voltage converter depending on the phase difference, detected by the reception clock generator, between the timing of a change in the received data and the reference clock signal. If good reception sensitivity is not available due to a phase difference, then the phase difference-to-voltage converter generates a control voltage in a manner to eliminate the phase difference, and applies the generated control voltage to a variable capacitor connected to the reference oscillator for automatically adjusting the reference bit rate frequency.

Abstract: A demodulation correcting circuit for an FSK signal receiver which include an AFC for correcting a reception frequency error to provide stabilized demodulation, said demodulation correcting circuit comprising subtracting circuit followed to a loop filter for eliminating or correcting a variation of the center frequency of the FSK modulation signal, which is caused by the fact that the AFC responds to low frequency components including DC of the FSK modulation signal and which brings about a decrease of noise margin.

Abstract: A voltage-controlled crystal oscillator circuit with an extended range is presented. The circuit has a crystal oscillator circuit, a phase-locked loop (PLL), and a look-up table. The crystal oscillator circuit generates a signal having a frequency f.sub.ref at its output node responsive to a voltage at its input terminal. The PLL has its input node connected to the crystal oscillator output node and generates a signal at the PLL output node having a frequency f.sub.o. A first divider circuit of the PLL divides the f.sub.ref frequency by a first variable integer M and a second PLL divider circuit divides the f.sub.o frequency by a second variable integer N. The look-up table, which has comparators connected to the input terminal, a counter connected to the comparators and a memory responsive to the counter and storing M and N values, varies M and N responsive to the input terminal voltage so that the voltage-controlled crystal oscillator circuit has an increased frequency range.

Abstract: A frequency control apparatus for compensating frequency fluctuation in an input received signal from a satellite station of a satellite communication system, comprises a PLL arrangement for generating a frequency converting signal in response to the frequency fluctuation in the input received signal, a mixer for mixing the input received signal and the frequency converting signal to deliver a resultant output signal, and a control circuit for designating a predetermined signal as the frequency converting signal when the PLL arrangement becomes a phase-unlocked state.

Abstract: An apparatus and a method for selecting a station are disclosed in which a count section or a comparison section compares/decides a local oscillation frequency, and a digital/analog converter controls the local oscillation frequency according to the decided result, in order to perform an accurate and stable station selection. The apparatus includes a local oscillator means, a dividing means, a count section or comparison section, a control section, and a digital analog converter. The method includes the steps of controlling the digital/analog converter, dividing, the signal output from the local oscillator outputting correction data, and controlling increase/decrease of the oscillation frequency of the local oscillator according to the correction data.

Abstract: In a structure adopted for an FM-CW radar, a corner waveguide for connecting each of transmission and reception antennas to a sensor unit is integrated with a sensor unit case. In a waveguide/strip line converter for converting the transmission mode between the waveguide and the strip lines in the circuits of the sensor unit, a ditch is dug in the inner wall of an opening of the waveguide in order to prevent oozing of conductive adhesive. The strip line board is abutted on the inner wall of the waveguide in order to restrict a length of a projecting portion of a line conductor on the strip line board. By employing an oscillator mixer or a multiplier mixer, the circuitry in the sensor unit can be simplified without using lots of expensive millimeter wave devices. Furthermore, power can be utilized effectively even when a switching radar is off, which enables measurement of an absolute speed. Moreover, cost reduction can be achieved.

Abstract: A phase locked loop (PLL) circuit for use as a demodulator and other applications. The PLL circuit (200) comprises a phase detector (210), a transconductance amplifier (212) and a current controlled oscillator (ICO) (214). The phase detector has two signal inputs and two outputs, and detects a phase difference between signals at its inputs. A capacitor C1 is connected to the output of phase detector (210) and develops an output voltage signal vo(t). A transconductance amplifier (212) is coupled to the capacitor C1 and converts the output voltage signal vo(t) to an output current signal. The ICO (214) is coupled to the transconductance amplifier (212) and the second output of the phase detector (210) and generates an output signal having a frequency which is proportional to an input current signal. The output signal of the ICO (214) is coupled to the second signal input of the phase detector (212).