Abstract: A pulsar based timing synchronization method and system are disclosed. In one example, a method includes receiving, by a pulsar signal receiver device, a pulse signal emitted from one or more celestial objects and processing, by the pulsar signal receiver device, the pulse signal to discipline a local clock to determine an accurate time output. The method also includes generating, by the pulsar signal receiver device, a timing synchronization signal based on the determined accurate time output. The method further includes providing, by the pulsar signal receiver device, the timing synchronization signal to at least one of a local power system device and a timing distribution network server.

Abstract: A technique, to keep alive one or more radio connections over a cellular network in order to carry downloaded data packets sent in a burst mode, is disclosed. In burst mode the flow of the data packets has a pattern with repeating two types of periods, an active period and a silent period. During an active period a plurality of data packets are sent and during a silent period almost no data packets are sent. The technique is implemented by an intermediate network element (NE) that is configured to send, during the silent period, a keep-alive signal (KAS) toward a relevant CD. The KAS can be a TCP acknowledgement, for example.

Abstract: A wireless charging system includes a transmitter with tunable reactive components (such as capacitance or inductance). A metric related to power transfer from the transmitter through a coil is used to determine an amount to modify a Parameter. One metric is equal to |Vs|·|Is|·cos(?)·(Vcoil_ref/Vcoil), where |Vs| is magnitude of the power source voltage, |Is| is magnitude of the power source current, ? is phase difference between the power source voltage and power source current, Vcoil_ref is a normalization value, and Vcoil is voltage across the coil. The transmitter can further include a phase tracking and adjustment loop (such as a phase-locked loop).

Abstract: A method of determining at a receiver whether a received signal comprises a pure tone signal component. The method comprises: measuring a received signal over a measurement period; calculating, using maximum likelihood hypothesis testing, a likelihood ratio value for the measured signal and, determining, based on said likelihood ratio value, whether the measured signal comprises a pure tone signal component. The likelihood ratio value is a value indicative of the ratio of a likelihood LFSC that the measured signal comprises a pure tone signal component, and a likelihood LnoFSC that the measured signal does not comprise the pure tone signal component.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: A circuit for a single differential-inductor oscillator with common-mode resonance may include a tank circuit formed by coupling a first inductor with a pair of first capacitors; a cross-coupled transistor pair coupled to the tank circuit; and one or more second capacitors coupled to the tank circuit and the cross-coupled transistors. The single differential-inductor oscillator may be configured such that a common mode (CM) resonance frequency (FCM) associated with the single differential-inductor oscillator is at twice a differential resonance frequency (FD) associated with the single differential-inductor oscillator.

Abstract: In a wireless network, a base station (BS) may send a primary synchronization signal (PSS) and a secondary synchronization signal (SSS). The synchronization signals may be used by user equipments (UEs) for cell detection and acquisition. A typical searching operation may involve first locating the PSS sequences transmitted by neighboring BSs, followed by SSS detection. Described further herein are algorithms that result in the detection of the PSS and the SSS from a BS. A method for detecting a BS generally includes sampling a received signal from receiver antennas to obtain a sampled sequence, analyzing the sampled sequence to detect a PSS in a current half-frame (HF), calculating signal-to-noise ratio (SNR) metrics based on the detected PSS, combining the calculated SNR metrics with SNR metrics from previous HFs, analyzing the combined SNR metrics to obtain timing information, and analyzing the sampled sequence using the timing information to detect a SSS.

Abstract: Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.

Abstract: A method for operating an automation system with a plurality of communication users linked for communication purposes via a serial connection, of which at least one functions as sender and at least one as a receiver, includes determining at a sender an offset value between an occurrence of a synchronous signal and a communication clock cycle, transmitting the determined offset value in a data transmission to the at least one receiver, waiting at the at least one receiver until a time period commensurate with the offset value has elapsed, and generating at the at least one receiver an output signal after the time period has elapsed.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).

Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).

Abstract: Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.

Abstract: A frequency synthesizer and a frequency synthesis method thereof are provided. The frequency synthesizer includes a phase-locked loop unit, a voltage-controlled oscillating unit, and a frequency mixing unit. The phase-locked loop unit receives a reference signal and a feedback injection signal and generates a first oscillating signal according to the reference signal and the feedback injection signal. The voltage-controlled oscillating unit receives the feedback injection signal and generates a second oscillating signal according to the feedback injection signal. The frequency mixing unit is coupled to the phase-locked loop unit and the voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal, and mixes the first oscillating signal and the second oscillating signal to generate the feedback injection signal and an output signal.

Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.

Abstract: Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.

Abstract: A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Abstract: A wireless communication unit has two or more communication modes including one or more mobile phone mode, in which mobile phone mode the wireless communication unit is able to transmit or receive wireless signals via an antenna from and/or to a mobile phone network in accordance with a communication protocol. The unit includes a baseband module and a radiofrequency module. A radiofrequency interface of the baseband module is connected to the radiofrequency module, for receiving and/or transmitting baseband signals from and/or to the radiofrequency module. The radiofrequency module includes a baseband interface, for receiving and/or transmitting the baseband signals to the baseband module and an antenna interface (AI) connectable to an antenna for receiving and/or transmitting radiofrequency signals from and/or to the antenna. A clock system is connected to the radiofrequency interface and the baseband interface.

Abstract: A method for generating phase signals includes triggering a phase register to output a binary number stored in the phase register, wherein the phase register is triggered based at least in part on a voltage signal provided by a voltage controlled oscillator. The method also includes providing an input signal to a decoder, wherein the input signal is based at least in part on the binary number output by the phase register and the decoder is operable to generate phase signals in response to the input signals. The method further includes incrementing the binary number stored in the phase register and repeating the triggering and providing steps after the binary number is incremented.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: A method and apparatus for compensating an oscillator in a location-enabled wireless device is described. In an example, a mobile device includes a wireless receiver for receiving wireless signals and a GPS receiver for receiving GPS signals. The mobile device also includes an oscillator having an associated temperature model. A frequency error is derived from a wireless signal. The temperature model is adjusted in response to the frequency error and a temperature proximate the oscillator. Frequency error of the oscillator is compensated using the adjusted temperature model. In another example, a frequency error is derived using a second oscillator within the wireless receiver.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to generate a synthesized frequency signal from the reference signal. The synthesized frequency generation logic comprises programmable divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period substantially equal to N times that of the reference signal, where N comprises a programmable integer value. The synthesizer frequency generation logic is arranged to generate the synthesized frequency signal comprising a frequency with a period substantially equal to 1/M that of the divided signal, where M comprises a further programmable integer value.

Abstract: In an ADPLL circuit, on the basis of a gain of a digitally controlled oscillator estimated when a loop gain of a certain value is set in the loop filter and on the basis of a device parameter of the digitally controlled oscillator, the DCO gain estimation unit estimates a gain of the digitally controlled oscillator when a loop gain of another value is set in the loop filter.

Abstract: A polar receiver using injection-locking technique includes an antenna, a first filter, a first voltage-controlled oscillator, a first mixer, a frequency discriminator, a second filter, a third filter, a first analog-digital converter, a second analog-digital converter and a digital signal processing unit. Mentioned polar receiver enables to separate an envelope signal and a frequency-modulated signal from a radio frequency signal received from the antenna via the injection locking technique of the first voltage-controlled oscillator and the frequency discriminator. The envelope component and the frequency-modulated component can be digitally processed by the digital signal processing unit to accomplish polar demodulation.

Abstract: In an oscillating apparatus, a detection unit detects a frequency offset between an input signal and a reference signal. A code generation unit specifies a relationship among a code having a predetermined number of bits, the frequency offset, and a voltage to be applied to a voltage-controlled oscillator by a DAC, in accordance with a frequency offset detection state of the detection unit. The code generation unit also generates a frequency offset correction code having a predetermined number of bits in accordance with the specified relationship. The DAC applies the voltage to the voltage-controlled oscillator, in accordance with the relationship described above and the code generated by the code generation unit. The voltage controlled oscillator outputs an oscillator signal having an oscillation frequency corresponding to the voltage applied by the DAC.

Abstract: A method and device for managing a reference oscillator within a wireless device is presented. The method includes selecting reference oscillator parameters associated with the lowest reference oscillator error, where the selection is based upon reference oscillator parameters derived using different technologies within a wireless device, acquiring a satellite based upon the selected reference parameters, determining the quality of the satellite-based position fix, and updating the reference oscillator parameters based upon the quality of the satellite-based position fix.

Abstract: According to one embodiment, an RSSI signal error-detection protection circuit configured with respect to an RSSI circuit outputting an RSSI signal on a basis of an output level of an amplifier amplifying intermediate frequency signal outputted from a mixer circuit includes an RSSI operation control unit configured to switch between operation and non-operation of the RSSI circuit by controlling the lock detection signal outputted from the PLL circuit configured to control a local oscillation frequency signal inputted from the mixer circuit.

Abstract: A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit.

Abstract: A mobile wireless communications device includes a circuit board carried by a housing. A microprocessor, RF transceiver and circuitry are carried by the circuit board and operative with each other. Clock buffer circuitry is carried by the circuit board and connected to the RF transceiver and circuitry and microprocessor for isolating a clock signal from the noise of the microprocessor and allowing greater isolation for the RF transceiver from RF circuitry.

Abstract: There are provided a sampling mixer, quadrature demodulator, and a wireless device capable of suppressing receiving sensitivity degradation caused by alias components or second-order distortion components. In the sampling mixer (101), a sampling switch (5) and another sampling switch (36) sample a reception signal based on a local signal with a predetermined frequency. A control signal generator (15) generates a control signal for controlling a filter operation. An in-phase mixer (2) and a reverse-phase mixer (3) perform, based on the control signal, filter processing on the sample signal obtained by the sampling switch (5). A delay controller (117) controls the phase difference between the local signal and the control signal according to a reception-desired frequency.

Abstract: Various embodiments facilitate data communication between a client device and a remote device over a voice channel of a telephone system. In one embodiment, the data communication over the voice channel is synchronized to align with voice frames utilized by the telephone system to transmit communicated data between the devices. In some embodiments, the synchronization is performed by determining an offset between a received synchronization audio signal and the voice frames used by the telephone system to process the synchronization audio signal, such as based on an amount of energy present in the received synchronization audio signal.

Abstract: A system for managing the simultaneous operation of a plurality of radio modems in a single wireless communication device (WCD). The multiradio control may be integrated into the WCD as a subsystem responsible for scheduling wireless communications by temporarily enabling or disabling the plurality of radio modems within the device. The multiradio control system may comprise a multiradio controller (MRC) and a plurality dedicated radio interfaces. Further, clock synchronization protection between the multiradio system controller, other modems and wireless communication devices with whom the wireless device is communicating may further be implemented as a protective measure to ensure a valid clock synchronization between all devices internal and external to the primary wireless device.

Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.

Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.

Abstract: An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices.

Abstract: An RF transmitter that, during a transmission session, transmits multiple data slices, which are synchronized to each other by a transmit counter. Typically, the time between transmission of consecutive data slices is constant; however, to synchronize the transmission session with a base station, the time between transmission of consecutive data slices may be occasionally adjusted. By using the transmit counter to synchronize data transmissions, effects of uncompensated latencies or variances in latencies may be reduced or eliminated.

Abstract: A method and system for GPS (Geographical Positioning System) synchronization of a femtocell, as defined in the application, in a wireless telecommunications network, the system including a Base Transceiver Station (a “sync-BTS”) for transmitting synchronization signals, a module for GPS synchronization coupled to the sync-BTS, at least one femtocell, and a processor in each femtocell for performing time and frequency synchronization on the sync-BTS over an air interface.

Abstract: A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a transmission electrode of the reference capacitor; receiving a coupling signal on a reception electrode of the reference capacitor; amplifying the coupling signal, generating a reception reference signal; generating a reception control signal as a function of the reception reference signal; transmitting a communication signal on an electrode of the coupling capacitor; receiving a reception signal on an electrode of the coupling capacitor; amplifying the reception signal, generating a first compensated signal; controlling a level of amplification of amplifying the coupling signal and the reception signal as a function of the reception control signal; and detecting a possible misalignment between the first and second devices based on an amplitude of the communication signal and an amplitude of the compensated signal.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.

Abstract: Aspects of a method and system for clock synchronization in a GNSS receiver are provided. In this regard, generation of a clock signal in a GNSS receiver may be disabled during a first time interval and enabled during a second time interval, wherein a counter utilized to generate the clock signal may be initialized to a known value during the first time interval via a reset signal synchronized to a reference signal. The reference signal may be generated by a temperature compensated crystal oscillator. Additionally, a counter may be incremented on each active edge of the reference signal that occurs during the first time interval and the value stored in the timer may be utilized to correct time in the GNSS receiver after the first time interval. In this regard, the value stored in the timer may be added to the time at which the first interval began.

Abstract: A mobile wireless communications device includes a circuit board carried by a housing. A microprocessor, RF transceiver and circuitry are carried by the circuit board and operative with each other. Clock buffer circuitry is carried by the circuit board and connected to the RF transceiver and circuitry and microprocessor for isolating a clock signal from the noise of the microprocessor and allowing greater isolation for the RF transceiver from RF circuitry.

Abstract: Provided is a modulating apparatus and method of an on-channel repeater. An object of the present invention is to provide a modulating apparatus of an on-channel repeater for reducing time delay by configuring and up-sampling a baseband signal, filtering the up-sampled baseband signal with an Equi-Ripple (ER) filter or in a window method, and converting the filtered baseband signal into an RF signal. The modulating apparatus includes: a baseband signal configuring unit for configuring a baseband. signal by combining an input field and a segment sync signal; a pilot adding unit for adding a pilot signal to the baseband signal; a filtering unit for filtering the baseband signal with the pilot signal; and an RF up-converting unit for up-converting the filtered signal into an RF signal. The present invention is used to form an on-channel repeating network in a transmitting system including a digital TV broadcasting system.

Abstract: A radio receiver including a reception processing system that uses discrete-time frequency conversion to acquire a signal having a sampling rate corresponding to a local frequency, wherein the reception characteristic is improved when the reception processing system is applied to a system having a wide reception channel band. The radio receiver comprises an A/D converting part that quantizes a discrete-time analog signal to a digital value to output a received digital signal; a channel selection filtering part that uses a tap coefficient value to perform a digital filtering process of the received digital signal; and a frequency response characteristic correcting part that generates the tap coefficient in accordance with the sampling rate.

Abstract: A communication system comprising one or more transceiver units of a first type and one or more transceiver units of a second type capable of communicating with the transceiver units of the first type; each transceiver unit of the first type comprising: a frequency comparison unit for comparing the frequency of a signal received from a transceiver unit of the second type with a reference frequency; a feedback signal generator for generating a feedback signal dependent on the result of that comparison; and a transmitter for transmitting that signal to the transceiver unit of the second type; and each transceiver unit of the second type comprising: a local frequency reference unit on which the frequency of signals transmitted by it are dependent; and a frequency adjustment unit for receiving the feedback signal and adjusting the local frequency reference unit in dependence on the feedback signal.

Abstract: An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices.

Abstract: A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. The DLL is configured to avoid a perceived phase shift when the control voltage to a delay line is reset upon reaching a predetermined amount. Embodiments disclosed include a DLL, a radio receiver using the DLL, a circuit for resetting the DLL, a method for recovering a modulated radio signal, and a method of synchronizing a reference clock to a radio signal. The approach can allow for improved synchronization of the reference clock to a received radio signal during baseband frequency recovery.

Abstract: Disclosed is an oscillator circuit (10) for use in a local oscillator of an RF communications device (100) that communicates over an RF channel. The oscillator circuit includes an oscillator transistor coupled to a power supply voltage (Vcc) through a buffer transistor, and a biasing network having bias voltage outputs coupled to a control input of the oscillator transistor and to a control input of the buffer transistor. In one embodiment the bias voltage network is coupled to Vcc, while in another embodiment the bias voltage network is coupled to a separate voltage (Vbias). Circuitry is provided for setting a magnitude of Vcc and/or Vbias as a function of at least one of RF channel conditions, such as channels conditions determined from a calculation of the (SNR), or an operational mode of the RF communications device.

Abstract: A radio receiver for diversity has a first receiving unit and a second receiving unit for diversity-receiving a signal of a radio frequency. The first receiving unit has a first mixer for converting the received signal of the radio frequency into an IF signal of a first intermediate frequency by an upper local method, and a first filter coupled to the output side of the first mixer. The second receiving unit has a second mixer for converting the received signal of the radio frequency into an IF signal of a second intermediate frequency by a lower local method, and a second filter coupled to the output side of the second mixer. The radio receiver can improve receiving sensitivity.

Abstract: An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband.