Abstract: A selective call receiver (100) for receiving and transmitting paging signals has a transceiver (104) having an integer divide synthesizer (105) for achieving a fast lock time. The transceiver (104) has a reference oscillator (202) that generates a reference signal in a direct injection path and a modulator (206) coupled in the direct injection path modulates the reference signal to generate a modulated reference signal. A phase locked offset loop (220) coupled to the direct injection path generates a low frequency signal derived from the reference signal, a multiplier (210) coupled to the modulator (206) multiplies the modulated reference signal, and a mixer (214) coupled to the multiplier (210) receives the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop (220) to generate a first local oscillator output signal and a modulated transmit carrier.

Abstract: An automatic frequency control loop structure utilizes a dual selection automatic frequency control unit which is coupled to a differential phase unit and a coherent phase unit to provide a frequency corrected received signal output for efficient tracking of frequency offset drift; and a much lower probability of loss of automatic frequency control loop lock. Thus, a signal from a coherent carrier recovery process provides additional benefit by utilization in adjusting frequency offset tracking performance.

Abstract: In a method and a device for correcting a frequency offset between a receive signal and a reference signal, the receive signal, being fed to a frequency converter which also receives a conversion signal in order to produce a transposed signal, the conversion signal is produced by a local oscillator in response to a control signal. The device initializes the control signal according to the reference signal. An estimator receives the transposed signal and the control signal and produces repetitively an estimate of the frequency offset comprising the sum of a correction value and an adjustment value respectively greater than and less than a predetermined correction threshold. The control signal is modified in response to the correction value. The transposed signal is connected using at least one of the successive estimates.

Abstract: A fixed system receiver (107) operates in a synchronization mode which is one of a synchronous mode and an asynchronous mode. A system controller (102) transmits a response command which includes a preamble indicator corresponding to the synchronization mode of the fixed system receiver (107). A selective call radio (106) receives and decodes the preamble indicator and generates a response message data unit (312). The synchronous header data packet (660) is preceded by a synchronizing packet (650) when the preamble indicator indicates the asynchronous mode and is not preceded by the synchronizing packet (650) when the preamble indicator indicates the synchronous mode. The selective call radio (106) transmits the response message data unit (312). The fixed system receiver (107) acquires symbol recovery timing and synchronizes to data packet boundaries of the response message data unit (312), using the synchronizing packet (650) when included.

Abstract: A frequency control apparatus for compensating frequency fluctuation in an input received signal from a satellite station of a satellite communication system, comprises a PLL arrangement for generating a frequency converting signal in response to the frequency fluctuation in the input received signal, a mixer for mixing the input received signal and the frequency converting signal to deliver a resultant output signal, and a control circuit for designating a predetermined signal as the frequency converting signal when the PLL arrangement becomes a phase-unlocked state.

Abstract: A radio receiver (700) uses automatic frequency control for locking a controlled reference signal (108) to a pilot reference signal (114) that has been distorted by multipath fading. The radio receiver (700) is programmed to sample the pilot reference signal (114) over a predetermined time interval to determine an average pilot frequency, and applies a first weighting function to the average pilot frequency to generate a weighted pilot frequency and a second weighting function to a controlled frequency of the controlled reference signal (108) to generate a weighted controlled frequency. The radio receiver (700) sums the weighted pilot frequency with the weighted controlled frequency to provide an update frequency, and modifies the controlled reference signal (108) such that its frequency matches the update frequency. The radio receiver (700) continues these programmed steps so as to lock the controlled reference signal (108) to the pilot reference signal (114).

Abstract: A controllable crystal oscillator of a receiver having a mixer producing an IF signal is controlled by a feedback loop that includes a phase detector. The IF signal is delayed by an odd multiple of .pi./2 and fed to one input of an exclusive-OR circuit, with the other input receiving the IF signal directly. The phase detection signal from the exclusive-OR circuit can be counted and converted to an analog voltage when the oscillator is a voltage controlled oscillator or it can be counted and used as a digital control signal when the oscillator is a data controlled oscillator.

Abstract: A radio (100) has a combined phase locked loop (PLL) (207) and an automatic frequency control (AFC) loop (215, 109, 111) and a method of operating the same. A mixer (201) converts the received RF signal (117) to an intermediate frequency (IF) signal (219) responsive to an injection signal (217). The PLL (207) locks the injection signal (217) to the received RF signal (117) responsive to a difference between the IF signal (219) and a reference signal (119). The AFC loop (215, 109, 111) locks the reference signal (119) to the received RF signal (117) responsive to a difference between the injection signal (217) and the reference signal (119).

Abstract: A frequency synthesizer (100) is used for generating a plurality of signals operating at a plurality of frequencies that are integer multiples of a reference frequency. The frequency synthesizer (100) includes a plurality of phase lock loops coupled to a single phase error detector. The phase error detector (103) is connected to a reference signal (104), a first generated signal (116) and a sampler signal (136) derived from a second generated signal (132). The phase error detector (103) includes a shared counter (118), and first and second registers (106, 122) connected to the output of the shared counter (118). First and second phase lock loops (101, 105) are used for phase locking to the reference signal (104). The first and second phase lock loops (101, 105) derive phase error signals from the first and second registers (106, 122), thereby adjusting the first and second generated signals (116, 132).

Abstract: A high frequency television signal receiving apparatus providing excellent linear detection of output characteristics by improving the phase characteristic of the picture synchronous detector. A variable capacitive element is equivalently connected in parallel to a reference solid-state oscillation element. The reference solid-state oscillation element controls the frequency of a local oscillation device including a PLL circuit for feeding a local oscillation signal to a mixer for converting a high frequency signal into an intermediate frequency signal. A first low pass filter is connected between a phase comparator for detecting a phase difference of the intermediate frequency signal and the output of a detection oscillator for generating a detection oscillation signal with a specific phase difference. A second low pass filter having a larger time constant than the first low pass filter is connected to the variable capacitive element.

Abstract: A method of controlling a digital carrier recovery apparatus designed to be integrated in a demodulation stage of a receiver for receiving a digital signal. The demodulation stage includes a carrier recovery detection apparatus. The carrier recovery detection apparatus includes a loop filter including a summing circuit followed by a bistable circuit operating in time with the symbol time, and a switching device disposed between the summing circuit and the bistable circuit. The switching device is driven to alternately apply to the bistable circuit a control word, whose variation between two successive applications to the bistable circuit is less than the acquisition band of the carrier recovery apparatus, and the output signal of the summing circuit. By alternately applying the control word and the output signal, the acquisition band is displaced relative to the tracking range of the carrier recovery apparatus.

Abstract: A receiver has a channel scan mode of operation and a communication mode of operation. In the channel mode of operation, the passband of a filter is narrowed relative to the passband of the filter in the communication mode. According to another aspect of the circuit, a local oscillator is selectively phase locked to an internal clock during channel scanning and locked to the incoming signal during a communication mode operation.

Abstract: A communication system which includes a receiving section having a frequency convertor for converting a received signal into an intermediate frequency signal by mixing with a local oscillation signal, and a demodulator for demodulating the received signal converted into the intermediate frequency signal, a transmission section for modulating a transmission signal received thereby, to transmit the so modulated signal, and an input/output section for receiving the demodulated signal from the receiving section and outputting it externally and receiving the transmission signal externally and outputting it to the transmission section.

Abstract: A voltage track and hold circuit operates to track a tuning voltage and holding the tuning voltage (404) as a reference voltage (408). In the track mode, the track and hold circuit includes a first operational transconductance amplifier (401) and a first charge storage device (402) coupled to a first input (403) of the first operational transconductance amplifier (401). The first charge storage device (402) accumulates a charge that corresponds with the tuning voltage (404). A second charge storage device (405) is coupled to a second input (406) and an output (407) of the first operational transconductance amplifier (401). The second charge storage device (405) accumulates a reference charge such that the reference voltage (408) present at the second charge storage device (405) is substantially equivalent to the tuning voltage (404).

Abstract: This invention relates to an abnormal synchronization preventing device used in a multiple value quadrature modulation type radio device and the abnormal synchronization preventing device includes a monitoring circuit for monitoring the carrier pull-out based on demodulated base band signals to output a carrier pull-out alarm signal, an abnormal synchronization detection circuit for sampling the reception signal level at a speed twice the transmission speed of reception data according to identification data and detecting abnormal synchronization according to whether or not the detection area of sampled data lies in a specified area, an abnormal synchronization preventing circuit for generating a signal for a preset period of time when abnormal synchronization is detected in a case where the carrier pull-out alarm signal is not output, and a selection circuit for receiving a reference signal used for generating a reference carrier frequency signal having a frequency close to the frequency of the carrier wave a

Abstract: Digital tuning of a locally generated frequency supplied to a frequency converting mixer, a mobile radio receiver is provided with great economy of components by utilizing the sampling rate oscillator for an analog-to-digital converter provided at the output of an analog intermediate frequency amplifier of the receiver as the source of the difference frequency for a phase locked loop (PLL) for control of the phase of a local oscillator for the mixer or mixers. All frequencies used to supply local oscillations to mixers, as well as the operating frequency of the phase locked loop are integer number multiples of the sampling rate pulse generator. Some division stages have fixed dividers and others have divisors selectable by a tuning processor and in some of the divisor connections it is useful to interpose a fixed or selectable-factor multiplier. A sampling rate of 42.75 MHz is recommended and an intermediate frequency amplifier frequency which is a rational number multiple of 57 kHZ, preferably 10.

Abstract: In a receiver for use in demodulating a modulated wave modulated by a digital data signal arranged within a preselected channel to produce a reproduced data signal by the use of a local frequency signal of a local frequency, a VCO and a PLL circuit are intermittently put into active states with reference to an offset frequency between a channel frequency and the local frequency. The PLL circuit is put into the active state for a time interval determined by the offset frequency before reception of the preselected channel while the VCO is put into the active state during the active state of the PLL circuit and during reception of the preselected channel. A duration of the active state in the PLL circuit becomes long when the offset frequency does not fall within a predetermined range determined by predetermined offset frequencies and, otherwise, the duration of the active state in the PLL circuit becomes short.

Abstract: A synchronous AM detector and processor requiring a reduced number of external components and fewer integrated circuit pins comprises an audio processor having a first filter operation controlled by a control voltage and an AM stereo decoder including a lock detector and a phase locked loop having a second filter operation controlled by the control voltage. A single control node is coupled to the audio processor and the phase locked loop, the control node providing the control voltage for the audio processor and the phase locked loop. The voltage at the control node is biased normally high, capable of being pulled low by the audio processing circuit and capable of being pulled low by the lock detector. An RC circuit decays the rise time of the control voltage at the control node after the control voltage has been pulled low. Circuitry is added to control the first filter operation of the audio processing circuitry responsive to the control voltage at the control node.

Abstract: A frequency synthesizer circuit, having first and second modes of operation, comprises a voltage-controlled oscillator (VCO) (64), a low-pass filter (74), a phase-locked loop (PLL) (67), an analog-to-digital converter (50), a digital-to-analog converter (56), a controller (48), and a VCO input switch. During the first mode, the VCO input switch couples the control input of the VCO to a control signal produced by the PLL, and the analog-to-digital converter measures the control signal and provides it to the controller which stores the control voltage measured by the analog-to-digital converter. During the second mode, the VCO input switch couples the control input of the VCO to the digital-to-analog converter which applies the stored control to the control input of the VCO.

Abstract: A demodulation circuit having an automatic frequency control (AFC) function in which a received input high frequency signal is mixed with a first reference signal to once form an intermediate frequency signal, the intermediate frequency signal is then mixed with a second reference signal having an adjustable frequency through such a frequency correction unit as a matched filter unit to obtain a demodulation signal having a maximum power value kept as a base band signal. For the purpose of preventing the failure of maintaining the AFC function caused by the limited correctable range of the frequency correction unit such as the matched filter unit, when the correctable range of the frequency correction unit reaches its limit, the frequency of the first reference signal is separately adjusted to thereby keep the frequency of the intermediate frequency signal always within the correctable range of the frequency correction unit.

Abstract: The present invention relates to a circuit arrangement by which a voltage-controlled temperature-compensated oscillator (VCTCXO) (10) serving as the frequency reference in a radio telephone is controlled. In the circuit arrangement there is used a phase-locked loop which locks the frequency of the VCTCXO (10) to the frequency of the intermediate-frequency signal (2.IF) of the receiver of the telephone. When the telephone is started up, a constant setting voltage (30) is coupled as the control signal (V.sub.con) for the VCTXCO (10) for controlling the reference frequency. In the call state the control signal (V.sub.con) is provided by by the phase-locked loop in which the locking is to the frequency of the intermediate frequency signal. When the call is cut off the control voltage (V.sub.con) is supplied from a memory (26) coupled to the phase-locked loop in which the value of the control signal (V.sub.con) is substantially equal to the control signal (V.sub.

Abstract: A wideband transceiver using contiguous overlapping frequency range local oscillators (32, 34) for a high side or a low side local oscillator and an intermediate frequency approaching, within commercialy practical limits, but not exceeding one half of the total limited oscillator frequency range (71).

Abstract: An indication of stability of a tuning system after changing, the local oscillator frequency to a predetermined frequency, such as a frequency corresponding to a new channel during a channel changing operation or to a new search frequency during a search, is provided by monitoring an AFT signal during the frequency changing operation and determining when it remains consistent for a predetermined time.

Abstract: An AFC circuit stabilizes the frequency of an intermediate frequency signal to be applied to a demodulation circuit. A frequency conversion circuit responds to a local oscillation signal generated from a voltage-controlled oscillation circuit to convert the frequency of a digital modulation signal and applies the converted frequency to the demodulation circuit. A carrier reproduction circuit in the demodulation circuit reproduces the carrier of the intermediate frequency signal to output a synchronizing detection signal. The frequency of the reproduced carrier is frequency-divided by a frequency dividing circuit. A frequency division output thereof is counted by a counter for a definite period. Data is outputted from a microprocessor in response to a count output of the counter and the synchronizing detection signal, and the data is then converted into an AFC voltage by a D/A converter. The converted voltage is supplied as a control voltage to the voltage-controlled oscillation circuit.

Abstract: A frequency control circuit, and associated method, for a receiver operative to receive a TDMA signal transmitted by a transmitter in a TDMA communication system. A first frequency detector generates a first frequency control signal. A second frequency detector, comprised of a portion of a decision-directed demodulator, generates a second frequency control signal. The first frequency control signal is utilized to effectuate frequency control when a signal is continuously received by the receiver, such as times immediately subsequent to initial powering of the receiver as the receiver becomes synchronized with the TDMA signal transmitted thereto. Onces a receiver becomes synchronized to the transmitter, the receiver need only be powered during intermittent time periods when the TDMA signal is transmitted to the receiver.

Abstract: A phase-locked-loop circuit for a radio transceiver operative to transmit and to receive modulated signals during nonconcurrent time periods. During time periods in which the radio transceiver is to generate and to transmit a modulated signal, the phase-locked-loop circuit is connected to the transmitter portion of the transceiver. During time periods in which the radio transceiver is to receive a modulated signal, the phase-locked-loop circuit is connected to the receiver portion of the transceiver. A switch, preferably comprised of a multiplexer, alternately connects the phase-locked-loop with the transmitter portion and the receiver portion of the transceiver.

Abstract: TV receiver including an RF section, a mixer stage to which a tuning frequency is applied from a tuning oscillator, an IF section, a synchronous detection device and a frequency and phase-locked loop circuit having a PLL and a FLL, the IF section being coupled to a phase detector of the PLL and to a frequency detection device of the FLL, the phase detector and frequency detection device being commonly coupled to a loop branch having the two loops in common and incorporating a loop filter and a controllable oscillator, the controllable oscillator applying a local in-phase carrier to the synchronous detection device and a local phase quadrature carrier to the phase detector.

Abstract: This disclosure discusses a programmable frequency synthesizer arrangement having programming feedback capability used to avoid undesirable operation due to random hard and soft faults. The arrangement operates by supplying appropriate programming information, receiving the same, subject to random hard or soft faults, and, in response, directing the operation of a frequency synthesizer (10). The feedback capability is accomplished by generating a feedback signal (35, 36) indicative of the programming information as applied to the frequency synthesizer, generating a reference signal representative of the appropriate programming information, comparing the two signals, and blocking undesirable operation of the frequency synthesizer if the comparison indicates the occurrence of a random hard or soft fault. Further disclosed is a wireless communications transceiver with the programmable frequency synthesizer arrangement.

Abstract: Apparatus for demodulating information signals frequency-modulated on an RF carrier signal carrying spectral components within the audio frequency range, a pilot carrier signal having an imparted phase shift from the phase of the transmitted pilot carrier signal, and amplitude-modulated spectral components having another imparted phase shift in a subcarrier channel frequency range above the audio frequency range. The apparatus includes a demodulator for demodulating the frequency-modulated information signals to provide a detected composite signal which includes a detected pilot carrier characterized by an imparted phase shift due to the effects of multipath reception, and detected amplitude modulated spectral components exhibiting another multipath induced phase shift.

Abstract: The synchronization process of the present invention filters the received signal with an adaptive band-pass filter (101) while buffering the received signal in memory (108). The energies of the input signal and the filtered signal are estimated (103 and 104) and the gain of the filter is adapted (105) based on the difference between the energies. The pole of the filter is adapted (102) to center the frequency of the input signal in the filter's pass-band. If a tone is detected (106), the length of the tone is determined (107) to ascertain if it is a frequency correction burst (FCB). If the tone detected is an FCB, the signal in the memory is also the FCB that is then filtered in the band-pass filter (101) and the difference between the frequency of this signal and 67.5 kHz is determined (109). This difference represents the frequency offset between the base station carrier frequency and that of the mobile radiotelephone, and can be fed into the local oscillating means to compensate for the frequency offset.

Abstract: In a clock recovery circuit, a received APSK signal is sampled at a frequency N times higher than the transmitted clock in response to a first clock from a local clock source, and quantized into orthogonal digital APSK samples. An envelope of the orthogonal APSK digital samples is detected (3) and phase correlations are detected (5) between the envelope and locally generated orthogonal sinusoidal signals and averaged by a low-pass filter (6). The arctangent between the low-pass filtered orthogonal signals is detected (7) and applied to a subtracter (8). A threshold comparator (9) compares the subtracter output with N successive values. A digital V.C.O. (10) is supplied with an output signal from the comparator (9) to generate a sample clock f.sub.c at a frequency 1/N of the frequency of the first clock f.sub.s for sampling the digital samples from the A/D converter (1). A phase difference is detected by a phase comparator (12) between the second clock f.sub.c and the sample clock f.sub.

Abstract: An apparatus for obtaining carrier synchronization acquisition in a digital burst mode communication system is provided. An accurate estimate of the carrier phase of the unmodulated preamble, .theta., is obtained by determining which of 256 intervals X.sub.o.sup.2 +X.sub.e.sup.2 fall into, and by evaluating which of 256 intervals Y.sub.o.sup.2 +Y.sub.e.sup.2 fall into. A quantized value is assigned to the generated output code for both X and Y inputs. The square root and arc tangent are evaluated to determine the value .theta..

Abstract: A high speed scanning radio has conventional RF amplifier, a mixer, a frequency synthesizer for the generation of local oscillator signals, an IF amplifier, a demodulator, and an audio output stage. The receiver includes a memory for storing a plurality of frequency codes corresponding to respective radio channels and a scan control for reading those codes, two for each channel, into the frequency synthesizer. A linear combination of each pair of distinct frequency codes is utilized to generate a local oscillator signal.

Abstract: A satellite transmission capturing method for the GPS receiver whereby PLL operation is stopped until the demodulation intensity of a demodulator reaches a predetermined level. The frequency of the reproduced carrier of the demodulator is consecutively changed in increments of a frequency range wider than the PLL capture range in search for satellite transmissions. This allows the demodulation intensity to reach the predetermined level in fewer frequency changing steps than ever before. Thus the time required to capture the desired satellite transmission is reduced. Where the integral time constant of a low pass filter in the demodulator is set to a value smaller than that in effect during PLL operation until the demodulation intensity of the demodulator reaches the predetermined level, a wide band demodulation intensity curve is used in search for satellite transmissions until that level is exceeded.

Abstract: A tuner station apparatus includes a first mixer for combining an input signal and a first local oscillation signal, and a second mixer for combining an output of the first mixer and a second local oscillation signal. The first and second local oscillation signals are generated by first and second PLL circuits, respectively. Each of the first and second PLL circuits include a frequency divider, a variable frequency divider, a phase comparator, a low pass filter, and a voltage controlled oscillator. The frequency divider of the first PLL circuit has a higher frequency division ratio than that of the second PLL circuit.

Abstract: A unique cellular telephone (100) digitally frequency locks to the received base station transmitter signal. The cellular telephone (100) includes a radio transceiver (106), a reference oscillator (104), and microcomputer (102) with memory therein for controlling the operation thereof. The radio transceiver (106) includes a phase-locked loop (PLL) synthesizer 120, a receiver mixer (122) followed by one or more gain stages (124), a phase detector (126), and a divider (128). The PLL synthesizer (120) generates a signal locked to the reference oscillator (104) that is mixed with the incoming base station transmitter signal in the receive mixer (122) to generate an intermediate frequency signal. The output of the reference oscillator (104) also feeds the divider (128), which divides the reference oscillator signal by an amount so as to generate the divided signal having a frequency substantially the same as the frequency of the intermediate frequency signal from the mixer (122).

Abstract: A satellite transponder has the local oscillator in the receiver slaved to a quartz crystal oscillator by a narrowband phase-locked loop during a standby period or in the absence of received signal and by a wideband phase-locked loop immediately the signal is received, at which time the narrowband phase-locked loop is switched out automatically.

Abstract: An AFC circuit stabilizes the frequency of an intermediate frequency signal to be applied to a demodulation circuit. A frequency conversion circuit responds to a local oscillation signal generated from a voltage-controlled oscillation circuit to convert the frequency of a digital modulation signal and applies the converted frequency to the demodulation circuit. A carrier reproduction circuit in the demodulation circuit reproduces the carrier of the intermediate frequency signal to output a synchronizing detection signal. The frequency of the reproduced carrier is frequency-divided by a frequency dividing circuit. A frequency division output thereof is counted by a counter for a definite period. Data is outputted from a microprocessor in response to a count output of the counter and the synchronizing detection signal, and the data is then converted into an AFC voltage by a D/A converter. The converted voltage is supplied as a control voltage to the voltage-controlled oscillation circuit.

Abstract: A frequency modulated radio frequency broadcast network in which re-transmitting stations employ a synchronous frequency modulated booster system. Included in the frequency modulated booster system is a synchronous frequency modulated exciter for converting a frequency modulated intermediate frequency into a frequency modulated broadcast signal. The synchronous frequency modulated exciter includes phase locked loop circuits for synchronizing the re-transmitted frequency modulated broadcast signal with the frequency modulated intermediate frequency signal by detecting reference signals in the composite baseband of the intermediate frequency signal and in the composite signal frequency modulated broadcast signal.

Abstract: A paging receiver has a synthesizer for governing the receive frequency. The paging receiving further has characteristics which are varied in response to the receive frequency. These characteristics include varying the bandwidth of a loop filter within a phase lock loop within the synthesizer as well as varying the time in which a detector circuit used to extract a DC level from a recovered audio signal is disabled. Furthermore, the bandwidth of the loop filter is varied in response to switching from a first receive frequency to a second receive frequency in order to provide for either a uniform frequency lock time or for a rapid frequency lock time. Furthermore, the time in which the detector circuit is disabled is correspondingly changed.

Abstract: A frequency modulated radio frequency broadcast network in which re-transmitting stations employ a synchronous frequency modulated booster system. Included in the frequency modulated booster system is a synchronous frequency modualted exciter for converting a frequency modulated intermediate frequency into a frequency modulated broadcast signal. The synchronous frequency modulated exicter includes phase locked loop circuits for synchronizing the re-transmitted frequency modulated broadcast signal with the frequency modulated intermediate frequency signal by detecting reference signals in the composite baseband of the intermediate frequency signal and in the composite signal frequency modulated broadcast signal.

Abstract: The converter has two mixer stages each including a phase locked loop with an oscillator controlled by a phase comparator. The frequency reference to both stages is provided by a single master reference. The frequency of the oscillator in the first stage is offset to accommodate the three different broadcast frequency conventions. A high frequency reference permits the second stage to compensate for noise kilohertz away from the carrier. A local oscillator output which is also phase locked to the master reference is provided for an external video modulator.

Abstract: A frequency stabilization circuit for a PSK data packet receiver includes a reference oscillator for supplying a continuous reference signal to a limiter that supplies feeds received data packets to a phase locked loop detection circuit including a voltage controlled oscillator. The frequency of the continuous reference signal is close to the carrier frequency of the data packets and maintains the frequency of the voltage controlled oscillator close to the data packet carrier frequency between data packets. During data packets, the reference oscillator signal is "swamped out" by the limiter.

Abstract: The present invention describes a phase shift key receiver or demodulator having an A.C. couple base band automatic gain control. A pair of detectors for the automatic gain control are A.C. coupled to the output of a pair of linear analog multipliers for the purpose of eliminating DC offset signals and for minimizing thermal noise at the input of the automatic gain control circuit. The outputs of the pair of detectors connected in the data detecting branch and the carrier tracking branch of the PLL are connected to a input of the summing circuit whose output is connected to the automatic gain control loop filter. The output of the filter supplies the scaling signal employed as the scaling input to the linear analog multipliers.

Abstract: Directly mixing synchronous receiver having an RF input (1) and a first signal path (S1) which is coupled thereto and which incorporates a first synchronous demodulator (3) and a first low-pass filter (4), and having a carrier regeneration circuit including a first phase-locked loop (Q) incorporating in a loop configuration a first phase detector (5) which is coupled to the RF input (1), a first loop filter (6) and a first voltage-controlled tuning oscillator (8) an output of which is coupled to the first phase detector (5), on the one hand, and to the first synchronous demodulator (3) via a phase shift circuit, on the other hand, for a direct demodulation of an RF reception signal to the frequency baseband. The local mixing carrier required for the direct synchronous demodulation should be accurately in phase or in antiphase with the carrier of a desired RF reception signal to be demodulated.

Abstract: In a circuit that detects from a received RF signal the digital signal modulated on the IF carrier signal by recovering the unmodulated IF carrier signal and comparing the recovered IF carrier with the downconverted RF signal, improvements are presented which minimize errors due to rapid and large phase changes in the RF signal. The circuit includes a downconverter (104) for downconverting the received RF signal to the IF level and a phase-locked loop (115, 118, 116, 119, 117) for both providing correction for relatively slow variations in the RF signal and for deriving the recovered IF carrier signal to which the downconverted IF signal is compared (108). Large and rapid phase changes in the RF signal are detected in a separate loop in the phase locked loop by monitoring (122) the sign and phase of the phase locked loop error signal for signals exceeding a predetermined threshold and rapidly advancing (123) or retarding (124) the phase of the recovered IF carrier whenever the threshold is exceeded.

Abstract: A frequency converter circuit for television signals is disclosed which contains a tuner and a low-IF converter which converts the television signal to a low IF signal to obtain adjacent-channel selectivity with low-pass filters. The low-IF converter further includes a phase-correcting stage and an amplitude-correcting stage for the two quadrature-signal paths. By digitizing the two signal paths after the first quadrature mixing process, their amplitude and phase stability is further improved.

Abstract: A receiver and transmitter are provided for a distress incident locating telecommunications system. The receiver is a superheterodyne AM receiver which applies the received distress transmissions to a normally unlocked phaselock loop which locks onto the unmodulated carrier signal portion of the distress transmission. The duration of the phaselock loop being locked, and unlocked immediately after being locked, are measured and compared to predetermined values to find a match. Each of the predetermined values corresponds to an item of information, and if a match is found, the receiver indicates it. The receiver is also capable of extracting audio information present in the distress transmission. The transmitter generates three signals which can be applied to a transmitting antenna. These signals are a radio frequency carrier signal, and a carrier signal modulated by a distress waveform or by an audio signal.

Abstract: A frequency modulated radio frequency broadcast network in which re-transmitting stations employ a synchronous frequency modulated booster system. Included in the frequency modulated booster system is a synchronous frequency .[.modualted.]. .Iadd.modulated .Iaddend.exciter for converting a frequency modulated intermediate frequency into a frequency modulated broadcast signal. The synchronous frequency modulated .[.exicter.]. .Iadd.exciter .Iaddend.includes phase locked loop circuits for synchronizing the re-transmitted frequency modulated broadcast signal with the frequency modulated intermediate frequency signal by detecting reference signals in the composite baseband of the intermediate frequency signal and in the composite signal frequency modulated broadcast signal.

Abstract: A frequency modulated ratio frequency broadcast network in which re-transmitting stations employ a synchronous frequency modulated booster system. Included in the frequency modulated booster system is a synchronous frequency modulated exciter for converting a frequency modulated intermediate frequency into a frequency modulated broadcast signal. The synchronous frequency modulated exciter includes phase locked loop circuits for synchronizing the re-transmitted frequency modulated broadcast signal with the frequency modulated intermediate frequency signal by detecting reference signals in the composite baseband of the intermediate frequency signal and in the composite signal frequency modulated broadcast signal.