Abstract: An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.

Abstract: Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit operation level before using optimizing with data flow algorithm and mapping the design onto hardware. In an aspect, the present invention discloses circuit operation level optimization for data flow graph representations with optimizing zero inputs caused by the upsamplers, or with optimizing unused outputs caused by the downsamplers. In at least one embodiment of the present invention, multirate data graph is converted to a single rate data graph before data flow optimizing. In an aspect, converting a multirate data graph to a single rate data graph comprises unfolding the multirate data graph with minimum unfolding factors that are inversely proportional to the clock values.

Abstract: A circuit board analyzing method and a circuit board analyzer are provided which can greatly reduce analyzing time. The circuit board analyzer includes a computing unit 110, a memory unit 140 connected to the computing unit 110, and an input unit 160 connected to the computing unit 110. The computing unit 110 includes a wiring data acquiring section 310 acquiring data of wirings formed on a circuit board, a basic circuit diagram forming section 320 dividing the wirings into meshes and setting cells and branches connecting the adjacent cells, and an interference analysis setting section 330 setting an element ignoring range of elements set in the cells and the branches.

Abstract: In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.

Abstract: A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

Abstract: A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.

Abstract: Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Abstract: A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.

Abstract: A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the event engine to monitor for the events. The device may have an external pin coupled to the event engine. The event engine may monitor a signal on the external pin to detect events external to the device. Alternatively, the device may output a signal on an external pin in response to detecting one of the events.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. In particular, the techniques and systems relate to design instrumentation circuitry that facilitates the analysis, diagnosis and debugging of the hardware designs. A HDL design instrumentation circuitry embedded within an electronic system comprises one or more probe circuits to allow storage of signal values of the electronic system upon predetermined events, one or more breakpoint registers to specify the predetermined events, and one or more trigger processing units to control the storage of signal values upon the detection of the predetermined events by the breaking registers. The present design instrumentation circuitry permits monitoring the electronic system at speed, facilitating the analysis diagnosis and debugging by giving detailed and accurate information about the operation of the electronic system.

Abstract: In one embodiment, a system model models characteristics of a real-world system. The system model includes a plurality of sub-portions that each correspond to a component of the real-world system. A plurality of test vectors are applied to the system model and coverage achieved by the test vectors on the sub-portions of the system model is measured. In response to a failure of the real world system, a suspected failed component of the real-world system is matched to a particular sub-portion of the system model. A test vector to be applied to the real-world system to test the suspected failed component is selected in response to coverage achieved on the particular sub-portion of the system model.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: Methods are provided for compactly representing behaviors of a processor of packets. A declarative description of the processor is input. The declarative description specifies rules for manipulating the packets. A dependency graph is generated from the declarative description. The dependency graph specifies each rule that depends upon another one or more of the rules. The declarative description and the dependency graph are transformed into a Petri net representing the behaviors of the processor. The Petri net includes respective transitions for the rules and places for enabling the transitions to fire. A specification of the Petri net is output. The Petri net represents the behaviors of the processor.

Abstract: Optical regeneration is expensive to implement and maintain. A method or corresponding apparatus in an example embodiment of the present invention enables a user to plan an optical regeneration in a network with a reduction of optical regeneration compared to unplanned deployment. An optical regeneration planning tool according to an example embodiment of the present invention can graphically display a representation of a network topology with optical regeneration sites and enable the user to plan optical regenerations at a subset of the sites as a function of characteristics of models of optical network elements and paths within the network topology. Through use of the optical regeneration planning tool, a service provider can save on network deployment and future servicing of optical regeneration equipment.

Abstract: One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.

Abstract: The circuit volume of a system under design is reduced by a circuit conversion involving consolidation (sharing) of common parts in the system by a representative part. The design data of the system post-conversion is used to verify operation of the system. However, the verification results for the system post-conversion express signals (e.g., signal X) of plural modules (e.g., modules a to c) as one signal waveform thereby making debugging difficult when a bug is found. Given this situation, from the verification results of the system post-conversion, signal-generation-use data is generated for generating the signal waveforms (here, respective signal waveforms for the modules a to c) of the system before conversion. After verification is complete, a signal waveform for each of the modules a to c is generated using the verification results for the system under design and the signal-generation-use data.

Abstract: A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.

Abstract: A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design optimization to reduce the optimizer execution time. Compaction helps readability, usability and reduces synthesis and static timing analyzer (STA) runtime. The aim of path compaction is to reduce the number of constraints the optimizer has to go through during the optimization process. Path compaction has three dimensions. The first is to reduce number of “-through” elements in the constraint, thereby reducing the complexity of constraints developed The second is to combine the paths to reduce the number of constraints. The third is to combine the constraints to reduce the number of constraints to be checked and optimized. Path compaction is used when generating timing exception using timing exception tools.

Abstract: The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel.

Abstract: Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed as an integral part of the early chip floor planning and chip power build processes providing efficient solutions requiring no extra wiring resource to be implemented and reducing the runtime of required final full-chip physical design checks, and the overall design cycle.

Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

Abstract: An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.

Abstract: Apparatus and method for transaction-based abstraction process can, in an embodiment, include three main phases: first, selecting a set of transaction-processing finite state machines (FSMs) that determine transaction boundaries. Second, extracting the transaction-processing FSMs, composing them, and computing an abstracted FSM corresponding to the composed FSM after abstraction, step 115. Third, abstracting all signals in the design based on the computed abstract FSM.

Abstract: The present invention provides a method for simulating processor power consumption, the method comprises: simulating a simulated processor; utilizing a power analysis model to analyze the simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of the at least one fragment; computing at least one power correction factor between the plurality of basic block; utilizing a processing apparatus to generate a simulation model with power annotation based on the power analysis and the at least one power correction factor; and predicting power consumption of the simulated processor based on the simulation model with power annotation.

Abstract: A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.

Abstract: A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.

Abstract: The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized random variables while taking correlations into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form.

Abstract: Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation.

Abstract: A method and device for performing a characterization of a description of the composition of an electronic system in terms of components used are disclosed. Performances of the components are described by at least two statistical parameters and one deterministic parameter. In one aspect, the method includes selecting a plurality of design of experiments (DoE) points, performing simulations on the selected DoE points, thus obtaining system responses, and determining a response model using the selected DoE points and the system responses. Selecting the DoE points includes making a first selection of a reduced set of chosen DoE points for the statistical parameters representing the statistical properties of the many possible statistical parameter realizations, and making a second selection of DoE points for the deterministic parameter representing the possible limited set of values that such parameter can take.

Abstract: An incontinence management system for monitoring wetness in one or more absorbent articles, includes input for receiving one or more sensor signals indicative of a presence of wetness in an absorbent article, processor for processing the one or more sensor signals and for performing an analysis of the signals to characterise wetness events occurring in an absorbent article and user interface for communicating with a user of the system. A mathematical model is used to characterise wetness events, receiving as inputs variables derived from sensor signals and optionally, patient and demographic data. The mathematical model can be configured and/or re-configured utilising observation data obtained while monitoring a patient for wetness. A diaper for use with such as system is also disclosed.

Abstract: Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more timing points of an optimized netlist, where one or more of the two or more timing points are received from one or more of a user, a memory medium, and/or a network. For example, a timing point is a primary input, a primary output, or a latch point. After receiving the two or more timing points of the optimized netlist, the MTR utility determines two or more minterms of the optimized netlist. In determining the minterms, from one timing point to a next timing point: a polarity at the timing point may be determined, and a forward trace from the timing point to the next timing point is performed to determine the two or more minterms of the optimized netlist.

Abstract: In a graphical modeling environment supporting a model having at least two different analysis frameworks operating therein, a system and corresponding method of processing the graphical model modify the model to group model portions together for processing in the same analysis framework. Model parts are identified and associated with the analysis framework in which they operate. Model parts are then grouped based on their association with their analysis framework to form model portions that operate in one of the different analysis frameworks. In instances where topological separation of model portions operating in the same analysis framework occurs, the system and method reconfigure intervening model portions to be amenable with operation in the analysis framework of the surrounding model portions to improve processing efficiency.

Abstract: An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation timing verifying apparatus and program sets an unreal corner condition that all delay elements present a maximum delay as an operating condition, performs operation timing analysis in the operating condition, thereby extracting an operation-violating circuit path, if any, from a circuit layout, sets a real corner condition that at least one element type of delay elements from among the delay elements present a maximum delay as the operating condition and performs the operation timing analysis on only the operation-violating circuit path to determine again whether an operation violation exists therein.

Abstract: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.

Abstract: An authoring, execution, and participation software system and corresponding method for the capture and execution of real-world events (e.g., crises) involving individuals such as senior private and/or public sector leaders is presented. The authoring system and method are used to model a scenario, incorporating knowledge from domain experts, relevant media, and external computation/simulation engines. The execution system and method execute scenarios created by the authoring system and method and provide a communication hub for the participation system and method. The participation system and method provide individuals, such as senior leaders and their staff, with appropriate views into the unfolding scenario and appropriate decisions to be made. The system and method also include features that allow for research and analysis with respect to, for example, efficient crisis response tactics.

Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

Abstract: A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be ground rule correct, the system and method provide a legalized layout which meets the multiple grid constraints while maintaining LVS correctness and fixing the ground rule errors as much as possible with minimum layout perturbation from the input design. The system and method support multiple grid pitch constraints for hierarchical design, and provide for LVS correctness to be maintained while an on-grid solution possibly with some spacing violations.

Abstract: A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with the state of the at least one storage unit; and the system including a memory for describing storage units of a circuit, maintaining states of the storage units, and identifying distributed segments comprising combinational logic separated by the storage units, and processing units, each for simultaneously simulating at least one of the segments in accordance with the maintained states.

Abstract: Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a circuit including a computer system, a design verification tool and an output device. The design verification tool, executable on the computer system, includes a simulator and a partial timing model generator. The partial timing model generator is operable to generate a representation of the circuit for simulation by cutting a first portion of a circuit out of a full gate level netlist for the circuit and leaving a second portion of the circuit represented by the full gate level netlist, and to overlay a simplified representation of the first portion of the circuit over the representation of the circuit. The first portion of the circuit is cut out at timing paths.

Abstract: A method for modeling a system as a finite state machine in a modeling environment is discussed. Embodiments receive a representation of a finite state machine model and provide an interface for incorporating a temporal operator into the finite state machine model. The temporal operator may be a Boolean function that includes at least one event parameter and defines a temporal logic condition. Embodiments may also receive a definition of a first temporal operator that defines a logic condition related to a number of occurrences of two or more different base events.

Abstract: A method includes generating at least one matrix representing a two-port, generating gain, noise, and stability functions of a system comprising the two-port, a generator connected to one port of the two-port, the generator having a generator reflectance, and a load connected to the other port of the two-port, the load having a load reflectance, and optimizing the gain, noise, and stability functions. The two-port comprises a non-reactive multi-port modeled by an orthogonal matrix, and at least one amplifier connected to the non-reactive multi-port. The orthogonal matrix is parameterized using an exponential map of skew-symmetric matrices having components restricted to an interval from ?? to ?. The gain, noise, and stability functions are generated using the generated matrix, the generator reflectance, and the load reflectance, The gain, noise, and stability functions are parameterized by the skew-symmetric matrices.

Abstract: Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

Abstract: Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.

Abstract: A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state.

Abstract: In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented.

Abstract: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.

Abstract: Methods are described herein which consider both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, based on first developing closed-form models of chip level FPGA leakage and timing variations. Execution times are significantly reduced using these methods in comparison to performing detailed evaluation. The teachings provide mean and standard deviation which were found to be within 3% from those computed by Monte Carlo simulation, while leakage and delay variations can be up to 3× and 1.9×, respectively. Analytical yield models are derived which consider both leakage and timing variations, and use such models to evaluate FPGA device and architecture in response to process variations. The teachings allow improved modeling of leakage and timing yields and thus co-optimization to improve yield rates.

Abstract: A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description, a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation, an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description, and an RTL description generating unit configured to generate the logic circuit based on the allocation of ci

Abstract: A logic cell configuration processing method for a CMOS semiconductor is configured in which leak current per unit width equal for P-channel and N-channel MOS transistors, by calculating a probable average leak current, which is an expected value of leak current of the P-channel MOS transistor and the N-channel MOS transistor in the logic cell based on an input signal to be input to the logic cell; comparing a contribution of the P-channel MOS transistor with a contribution of the N-channel MOS transistor to the calculated probable average leak current; deciding the P-channel MOS transistor or the N-channel MOS transistor, whichever has a greater contribution, to be a low leak type MOS transistor; and adjusting ON current of the low leak type MOS transistor to be equal to ON current of the other MOS transistor.

Abstract: According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a plurality of print events within the plurality of hierarchically arranged design entities, where each print event has an associated message and at least one associated signal in the digital design. The one or more HDL source files are processed to obtain a simulation executable model including a data structure describing the plurality of print events defined for the simulation executable model and associating each of the plurality of print events with its respective associated signal.