Abstract: The present invention is a method and apparatus for creating a reduced-order IC interconnect model, which incorporates variations in interconnect process parameters, and models both on-chip and off-chip interconnects. The method is based on mathematically representing an IC interconnect system, including mathematical interconnect process parameter terms, which are manipulated to facilitate simplification of an IC interconnect model. The IC interconnect model is then simplified by using a mathematical technique called state-space projection. Specifically, an IC interconnect system is represented with at least one modified nodal analysis equation (MNA) that is based on frequency, interconnect process parameters are added and substituted back into the MNA(s), terms with interconnect process parameters are explicitly matched. A state-space projection is created, which implicitly matches frequency terms. The state-space projection is used to create the reduced-order IC interconnect model.

Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Abstract: A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.

Abstract: A method of communicating data among a plurality of software modules of a heterogeneous software system can include constructing an XTable object in a first software module of the plurality of software modules and providing the XTable object to a second software module of the plurality of software modules. The method further can include extracting data from the XTable object within the second software module.

Abstract: A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.

Abstract: One embodiment of the present invention is a method for producing a system for describing an electrical network. An output signal of the electrical network is sampled at a frequency that corresponds to the Nyquist criterion for the input signal to the electrical network. A model with a memory is developed for the output signal, which is sampled at a low sampling rate, with this model approximating the output signal. The model is then transformed by suitable interpolation to an interpolated model with a memory. The interpolation results in the model created in this way providing a good approximation to an output signal which is sampled at a high frequency. The resultant system can be used for predistortion.

Abstract: A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria. The method selects a number of datapath clusters to avoid too many input/output ports in data registers.

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: A discrete event system (DES) modeling environment models the occurrence of events independent of continuous model time. In a DES modeling environment, state transitions depend not on time, but rather asynchronous discrete incidents known as events. A user may customize selected parameters of a block or other component able to support at least one entity passing therethrough holding a value of arbitrary data type in a DES modeling environment. For example, a user can enable and disable ports a discrete event execution block in a discrete event execution model using a graphical user interface, such as a dialog box. Based on user-selected dialog inputs, a discrete event execution program can automatically update a specification for a block, for example, by adding ports to the graphical representation of the block.

Abstract: The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.

Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction can be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

Abstract: A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.

Abstract: Method, system, and computer program product for analyzing circuit structures for parasitic effects are provided. Data from a previous parasitic effect analysis of a circuit structure is used to perform parasitic effect analysis on another circuit structure even when the circuit structures are not identical, provided the circuit structures are similar.

Abstract: A device for logic synthesis that can be used to synthesize LUT logic circuit having intermediate outputs for multiple-output logic functions.

Abstract: Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: Various embodiments of the present invention provide systems and methods for improved semiconductor design. For example, various embodiments of the present invention provide methods for semiconductor design that include receiving a semiconductor design with at least a first function circuit and a second function circuit; simulating the semiconductor design using a first instruction and a second instruction; determining a power state transition between the first instruction and the second instruction; and augmenting the semiconductor design to implement the determined power state transition. Simulating the semiconductor design using a first instruction and a second instruction identifies an indication of a first subset of the first function circuit and the second function circuit used in executing the first instruction and a second subset of the first function circuit and the second function circuit used in executing the second instruction.

Abstract: A training module is described for training a conditional random field (CRF) tagging model. The training module trains the tagging model based on an explicitly-labeled training set and an implicitly-labeled training set. The explicitly-labeled training set includes explicit labels that are manually selected via human annotation, while the implicitly-labeled training set includes implicit labels that are generated in an unsupervised manner. In one approach, the training module can train the tagging model by treating the implicit labels as non-binding evidence that has a bearing on values of hidden state sequence variables. In another approach, the training module can treat the implicit labels as binding or hard evidence. A labeling system is also described for providing the implicit labels.

Abstract: A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.

Abstract: A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.

Abstract: A method and an apparatus for obtaining an equivalent circuit model of a multi-layer circuit are disclosed. The method includes simulating the multi-layer circuit using an electromagnetic field analysis to provide a coupling network; and simplifying the coupling network using a circuit model order reduction method to generate the equivalent circuit model. The method is very simple to implement and the equivalent circuit model obtained has an apparent physical meaning.

Abstract: A digital system design method uses a higher programming language. In order to realize a digital system, an algorithm is verified based on a program written by the higher programming language and a program is programmed considering the higher programming language-hardware characteristics before the program is written in the lower programming language, and thus conversion into the lower programming language may be easily performed.

Abstract: Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate the data. In addition, the method enables read commands to be generated in a different sequence from the sequence of generated write commands, having different sizes than the sizes of the write commands, and that maximize the amount of data read (verified) and minimize the amount of unnecessary reads (re-verification).

Abstract: A system and method for implementing a unified model for integration systems is presented. A user provides inputs to an integrated language engine for placing operator components and arc components onto a dataflow diagram. Operator components include data ports for expressing data flow, and also include meta-ports for expressing control flow. Arc components connect operator components together for data and control information to flow between the operator components. The dataflow diagram is a directed acyclic graph that expresses an application without including artificial boundaries during the application design process. Once the integrated language engine generates the dataflow diagram, the integrated language engine compiles the dataflow diagram to generated application code.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient simulation to simulating the analog component with a second envelope simulation over a third simulation time period. The adaptive switching from the first envelope simulation to the transient simulation may be in response to the envelope simulation accuracy falling below a predetermined level of accuracy in comparison with a transient simulation or in response to the second simulation time period including expected digital transitions where one or more digital events may occur to change the analog input signals to the analog component.

Abstract: Techniques a race logic analysis on an integrated circuit (IC) design are described herein. In one embodiment, all hardware description language (HDL) defined system functions and/or tasks that have one or more side-effects when invoked in a first HDL language, but not when the same HDL-defined system functions/tasks are invoked in a second HDL language are identified. For all processing blocks that invoke the HDL-defined system functions/tasks that have side-effects, one or more triggering conditions of the processing blocks and HDL languages in which the processing blocks are coded are collected. When detecting a concurrent invocation race of the HDL-defined system functions/tasks statically or dynamically, checking is performed only the processing blocks that are coded in one or more HDL languages which render the HDL-defined system functions/tasks to manifest the one or more side-effects. Other methods and apparatuses are also described.

Abstract: Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.

Abstract: A system and computer program product for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation model is received by the instrumentation server from one or more simulation clients. A first and a second counter report are generated for the hardware simulation model, in which the first and second counter reports are derived from the count event data received by the instrumentation server. The first counter report is compared to the second counter report, and responsive to this comparison, a counter difference report is generated within the instrumentation server that conveys count event trends associated with the simulation model under different simulation testcases.

Abstract: In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.

Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the design. Generally, the test components complement the selected components in the design. Moreover, the test components can be automatically seeded with initial contents.

Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. Chunks are identified from the domains and sub-domain. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.

Abstract: Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in each of a plurality of these logical units is determined. The failure rate of integrated circuit portions corresponding to at least these logical units are then obtained. A feature failure coefficient indicating the likelihood that the feature will cause a defect then is determined by correlating the failure rates with the amount of occurrences of the feature.

Abstract: A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first capacitance value to match the delay characteristics of an actual receiver, and by using the second capacitance (in light of the use of the first capacitance) to match the slew characteristics of that actual receiver. Because typical EDA timing analyses focus mainly on delay and slew (and not the detailed profile of circuit signals), a two-capacitance receiver model can provide a high degree of accuracy without significantly increasing cell library size and computational complexity.

Abstract: A system for controlling reset in discrete event simulation is disclosed. The system includes a simulator configured to effect the discrete event simulation, the simulator having a plurality of shared executable files, a memory configured to store the simulator for execution, an operating system having a loading/unloading facility, and a control program configured to effect a reset operation by directing the operating system to unload the simulator from the memory and then reload the simulator into the memory using the loading/unloading facility.

Abstract: A simulation environment is disclosed wherein both analog and RF signals are simulated in a single flow by a mixed-domain simulator. The simulator includes a simulator kernel with an analog solver and an RF solver to allow both analog- and RF-type of signals to be solved in an interrelated fashion. The simulator may also include a partitioner that divides the circuit into various RF and analog modules to be solved. User input may control the partitioning process, but the simulator may refine the partitions or generate sub-partitions to provide a higher probability of convergence.

Abstract: A method and system for integrated circuit optimization to improve performance and to reduce leakage power consumption of an integrated circuit (IC). The original IC includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. The method creates an optimized standard-cell library from a standard-cell library. The standard-cell library includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. Further, an optimized IC is generated by using the optimized standard-cell library from the original IC. The optimized IC has an improved performance and reduced leakage power characteristics, as compared to the original IC.

Abstract: A method and system for handling assertion libraries in verification of a design are disclosed. The method and system include structuring and implementing at least one verification component in at least one of the assertion libraries with at least one standard assertion language supported by at least one verification tool, creating an assertion library element for a specific requirement for verification of the design without dependence on the at least one verification tool for the assertion library element, and resolving assertion status. With the disclosed method and system, visualization of assertion status at various levels of design hierarchy and at verification component level may be achieved, and implementing verification techniques may include optimization techniques during and/or after verification.

Abstract: A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.

Abstract: A circuit emulation system and method are provided, the system including at least one trace chain and a trace memory in signal communication with the at least one trace chain for sequentially receiving values and feeding them back through the chain to their original storage unit positions; and the method including modeling the circuit, providing at least one storage unit in the model, emulating the circuit with the model, extracting a state of the at least one storage unit during emulation, storing the extracted state, and restoring the stored state through a feedback loop.

Abstract: The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.

Abstract: In a method for designing a semiconductor integrated device, there are prepared a first power supply cell having a first decoupling capacitance and a second power supply cell having a second decoupling capacitance larger than the first decoupling capacitance. One of the first and second power supply cells is arranged in each of power supply cell areas of an input/output circuit area of the semiconductor integrated device in accordance with frequency-to-impedance characteristics at a predetermined point of input/output buffers of the input/output circuit area between first and second power supply lines thereof and frequency-to-noise current characteristics of the input/output buffers of the input/output circuit area between the first and second power supply lines.

Abstract: Verification of a design for a multi-voltage circuit which defines a plurality of iso-voltage rail blocks, and which comprises voltage state information for the iso-voltage-rail blocks. Verification includes generating cross-over information regarding a cross-over signal between two iso-voltage-rail blocks, identifying the voltage state relationship between the two iso-voltage-rail blocks based on the voltage state information, and verifying the validity of the cross-over signal based on the determined voltage state relationship.

Abstract: The present invention relates to a method for automatically generating HDL code, a code generator and a product for generating the code for the purpose of its implementation in programmable logic, based on a graphical representation for coding a state machine. With the method according to the invention, state transitions are executed on the basis of a modified query structure in that, starting from a target state, all the preconditions are derived which must be fulfilled in order to reach said target state.

Abstract: Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

Abstract: A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.

Abstract: Disclosed are methods, systems, and computer program products for evaluating performance aspects of electrical circuits, and particularly digital logic circuits. An exemplary method comprises obtaining access to a simulation dump file comprising state indications of the values of a plurality of signals of an electrical circuit at a plurality of simulation time points, and receiving an evaluation task that defines an output based on one or more input signals, with each input signal being a signal for which state indications are provided in the simulation dump file. The method further comprises generating, from the simulation dump file, one or more state representations for the input signals of the evaluation task, with each state representation being representative of the state of an input signal over a period of simulation time, and generating values of the output of the evaluation task at a plurality of simulation time points from the state representations.

Abstract: A verification support apparatus receives description data. Upon receiving the description data, the apparatus automatically generates and outputs a verification property, a verification scenario, specification data, review information, etc. In addition, the apparatus checks the description data for any element of deficiency or inconsistency before the automatic generation of the verification property. Therefore, the amount of description data can be reduced by sorting out the types of verification items and listing parameters, and various verification properties can be automatically generated by allowing a computer to read verification data. Furthermore, a design TAT can be reduced by generating the specification data. Furthermore, even a designer not familiar with a verification language such as PSL can easily execute assertion-based verification.

Abstract: A method of trace optimization in a flattened netlist of a circuit is disclosed. The method generally includes the steps of (A) generating a first total result by tracing a first path through the flattened netlist, (B) writing an intermediate result in a memory, the intermediate result characterizing a module having a plurality of instances in the circuit, (C) adding the intermediate result as read from the memory to the first total result upon crossing each of the instances of the module along the first path and (D) writing the first total result into the memory.