Abstract: A performance evaluation device includes: a control timing model unit for outputting a timing for inputting a control signal input/output between plural function blocks contained in a simulation model corresponding to a hardware; a control signal transfer period calculation unit for calculating a transfer period of the control signal between the plural function blocks in accordance with the timing for inputting the control signal; a data timing model unit for outputting a timing for inputting a data signal corresponding to the control signal, which is input/output between the plural function blocks; and a data signal transfer period calculation unit for calculating a transfer period of the data signal between the plural function blocks in accordance with the timing for inputting the data signal.

Abstract: A generic discovery methodology collects data pertaining to components of a computer network using various discovery technologies. From the collected data, the methodology identifies, filters and analyzes information related to inter-component communications. Using the communication and application information, the methodology determines reliable relationships for those components having sufficient information available. To qualify more components, the methodology implements a decision service to generate hypothetical relationships between components that are known and components that are unqualified or unknown. The hypothetical relationships are presented to a user for selection, and each hypothetical relationship is preferably associated with an indication of its reliability.

Abstract: A design specifications-driven platform (100) for analog, mixed-signal and radio frequency verification with one embodiment comprising a client (160) and server (150) is presented. The server comprises an analog verification database (110), a code and document generator (1020), a design to specifications consistency checker (103), a symbol generator (104), a coverage analyzer (105), a server interface (106), a web server (111), and an analog verification server application (101). The client comprises a web browser (130), generated datasheets and reports (120), generated models, regression tests, netlists, connect modules, and symbols (121), generated simulation scripts (122), a client interface (124), design data (131), simulators (132), and a design data extractor (123).

Abstract: Certain embodiments of the present invention are configured to permit development and validation of a device driver or a device application program by using improved virtual devices. Such improved virtual devices facilitate driver development without use of real devices or hardware prototypes. The present invention also may be configured to permit advanced validation of a device-driver combination that would be difficult to achieve even with a real device. Certain embodiments also may detect inconsistencies between virtual and real devices, which may be used to improve drivers and device application programs and increase compatibility of such drivers and device application programs with real devices.

Abstract: A trace associated with an abstraction of a target device is utilized to guide an execution of the target device to be substantially similar to the trace. An execution of the target device determines a non-deterministic decision based on a probability function. The probability function is configured to increase the likelihood that the execution will be substantially similar to the abstracted trace. Cross-entropy method may be utilized to guide the execution of the target device.

Abstract: Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter information. In some examples, self-configuring components obtain parameter information from adjacent components. In other examples, self-configuring components obtain parameter information from a system environment or a processor register. Component self-configuration can occur at a variety of times including preprocessing, simulation, and run-time.

Abstract: An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.

Abstract: A system, method and computer program product are provided including a catalog database with a plurality of product definitions. The product definitions includes a plurality of rules and attributes associated with a plurality of products. Further included is a pricing engine in communication with the catalog database. The pricing engine is adapted for charging for the products based on the rules and the attributes.

Abstract: A design support method of verifying control on a device of an image forming apparatus registers, in a storage device, trigger information for specifying a content of control to be executed when a start condition for switching the control state of the device is satisfied (S1002). The apparatus then registers, in the storage device, the allowable range of the state change of the device due to control switched when the start condition is satisfied (S1003). The apparatus then verifies whether the state change of the device due to the control switched when the start condition is satisfied falls outside the allowable range, by referring to the operation state of the device which is input through an input unit, and the trigger information registered in the storage device (S1004).

Abstract: In one or more embodiments, a system can simulate one or more physical mobile devices and can allow respective one or more users to utilize respective one or more simulations via a network. For example, a user, utilizing an application such as a web browser, can interact with a simulated mobile device. For instance, the user can select a function of the simulated mobile device, the simulated mobile device can provide, to the user, a simulation of the function, the first user can manipulate the simulated mobile device, and output of the function can be displayed to the user in accordance with the manipulation of the simulated mobile device. In one or more embodiments, the system can determine and display multiple images, of the simulated mobile, device based on multiple directions of a pointer path. For example, the system can determine the directions based on positions acquired at time intervals.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: Provided is to an apparatus for application testing of an embedded system which can cross-develop an application program installed in the embedded system regardless of the type of a target system. A virtual environment for testing the application program adopted in the target system is constructed on the basis of information inputted through a user interface and the application program is tested by configuring a virtual target system in the constructed virtual environment. According to the present invention, the application program adopted in the target system can be developed and tested without constructing a cross-development environment for each target system in an environment in which various kinds of embedded systems are developed.

Abstract: A computer based control system including a field network to which field devices equipped with hardware addresses and logical names are to be connected, a control device performing addressing control in relation to the field devices and their logical addresses and a simulation handling device. The simulation handling device has an own logical address, an own hardware address and is capable of obtaining a logical address, as well as possibly a logical name and/or a hardware address of at least one field device involved in the simulation. It notifies the control device that the field device is connected to the field network, detects a control signal directed towards field device addressed using the logical and/or hardware address of this field device and responds to the control signal with simulation results using the same logical and/or hardware address as the source of the response.

Abstract: Method and system to configure a common set of electronic components using software in order to simulate different electronic, mechanical and/or electro-mechanical instruments or instrument functions. For each instrument function or traditional mode of operation to be simulated, software models are created which when directed to the electronic components, cause the electronic components to respond to input in the same manner that the actual, traditional physical instrument would respond to satisfy the same test requirement input. The software models are preferably stored in a model repository which is searchable to enable a user to select the instrument function or traditional mode of operation to be simulated with the corresponding model being provided to the electronic components. Once the model, i.e., a function for each synthetic element, is downloaded and the electronic components configured according to the model functions, testing of the assemblies or other UUTs can begin.

Abstract: A system receives a model, internals associated with a target processor, and code information associated with the target processor, and obtains a bit-true model simulation for the target processor based on the model, the target processor internals, and the target processor code information.

Abstract: A testing system can perform scalability testing on a target system, including automatically identifying a performance bottleneck component of the target system when the target system includes multiple components. The testing system can specify a target load of a specified component of the target system. The testing system can provide a simulated request to the target system and measure performance of the target system. Based on the measurement, the testing system can determine a scaling factor. The testing system can scale up the simulated request by the scaling factor, and determine whether one or more components of the target system have reached full capacity. The testing system can then adjust the scaling factor and the simulated request, until the testing system identifies a component of the target system that is a performance bottleneck of the target system when a specific number of requests are provided.

Abstract: Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a simulation model is allowed to perform without synchronizing with another simulation model. The dynamic quantum may be received from a user. Respective simulation models are invoked for execution with the current value of the dynamic quantum provided to each of the simulation models. The method also comprises modifying the value of the dynamic quantum based on a simulation event.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: In a system in which a plurality of image forming devices are connected on one or more image processing devices through a network, efficiency of image formation is improved by assigning priority, or by ordering, the image forming devices according to power consumption and wait time. An image forming device is selected according to one of the power consumption and the wait time.

Abstract: A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics.

Abstract: A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices.

Abstract: The present invention concerns a mainframe data stream proxy (MDSP) (1) for caching communication of at least one emulator (2) directed to at least one mainframe (3), wherein the MDSP (1) comprises: a. a runtime application server (10), adapted for receiving (101, 201) at least one emulator action from the at least one emulator (2) and for sending (105, 209) at least one corresponding mainframe action to the at least one emulator (2); b. wherein the runtime application server (10) is further adapted for retrieving (102, 103) the at least one corresponding mainframe action to be sent to the at least one emulator (2) from a cache (20) of the MDSP (1).

Abstract: The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization.

Abstract: Formal verification of models using concurrent model-reduction and model-checking. For example, a system for formal verification of models includes: one or more model reducers to reduce a model; one or more model checkers to check the model, wherein at least one of the model reducers is to run concurrently with at least one of the model checkers; and a model synchronizer to synchronize information between at least one of the model reducers and at least one of the model checkers.

Abstract: A method for representing state transitions within a state machine includes representing a set of allowed transitions between states as a transition pair wherein a first value of the transition pair indicates a set of nodes from which to transition and a second value of the pair indicates a set of nodes to which to transition. The nodes represent states within a state machine. The method further includes defining a role of an entity within the state machine by assigning a number of transition pairs to the entity, the value pairs defining how the entity can transition through the state machine.

Abstract: A method for simulating a telecommunications network through objects that model respective network devices provides for simulating through the objects, the supply of network services according to respective quality of service profiles, by selectively identifying at least one quality of service profile, and dynamically configuring the objects to simulate the supply of the service corresponding to the selectively identified quality of service profile. In the simulation of networks having mobile terminals, the quality of service profile preferably has parameters chosen from traffic class, maximum transfer time of a data unit, guaranteed transfer speed for data transmitted by mobile terminal toward the network, maximum transfer speed for data transmitted from mobile terminal toward the network, guaranteed transfer speed for data transmitted by the network toward mobile terminal, and maximum transfer speed for data transmitted by the network toward mobile terminal.

Abstract: A computer implemented method of making an investment value decision through modeling an investment's expected cash flows, each expected cash flow represented on the display device of a computer as a graphical three-dimensional joint-probability volume encapsulating uncertainties of both time and magnitude, making it unnecessary to consider investment risk before choosing discount rates, allowing a user to discount all cash flows using only the “risk-free” rate to produce a net present value probability distribution rather than single-number estimate, and displaying the resulting net present value probability distribution as a graphical two-dimensional net present value probability area on the display device of a computer, wherein one dimension represents magnitude and the other dimension represents probability.

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.

Abstract: A system, method and computer program product are provided including a catalog database with a plurality of product definitions. The product definitions includes a plurality of rules and attributes associated with a plurality of products. Further included is a pricing engine in communication with the catalog database. The pricing engine is adapted for charging for the products based on the rules and the attributes.

Abstract: An X display may be dynamically rerouted to a different graphics terminal, or to several graphics terminals, without disrupting X clients. The corresponding X server architecture includes a static, protocol router part which acts as an endpoint for client connections and which routes X protocol to one or more X server displays, and a dynamic X display part which maintains the state and contents of the display. An X display may maintain its state and display contents entirely in memory without any need for physical display or input devices, in which case it is termed a “headless X display” and provides a virtual X server display that appears to the host as if it were a user-interactive display. The architecture allows for any number of X displays to be attached to the protocol router for multi-user, fault tolerant or suspend/resume functionality.

Abstract: A solar simulator for measuring the current-voltage characteristics of photovoltaic devices, in which an irradiated test plane of the object to be measured is disposed opposite an illuminating surface of the light source, the whole test plane of the photovoltaic devices is divided imaginarily into a plurality of sections, and a selected member for adjusting irradiance is disposed opposite the test plane of each imaginary sections so as to equalize or substantially to equalize the irradiance by the light source at every irradiated test plane of the sections, after which light from the light source is directed onto the test plane of the object to be measured.

Abstract: A method and apparatus automatically determines equilibrium operating conditions of a system model. The automated method enables users of block diagram models of dynamic systems to utilize simulation to define operating conditions for linearization. The automated method further allows users to generate operating conditions during simulation instead of explicitly specifying them by hand or using trim analysis. In accordance with one example, the method of generating a linear time invariant model includes providing a system model. A user specifies at least one event at which a linearization analysis should be performed. A simulation of the system model is executed. The electronic device automatically performs the linearization analysis upon occurrence of the at least one event as the simulation is running. Output results are generated of the linearization analysis to form the linear time invariant model.

Abstract: Crawling a browser-accessible application by causing a target application and a bridge application to run concurrently in a browser-controllable player, and iteratively receiving from the bridge application current state information of the target application, storing the state information on a data storage device if the state information is not found on the data storage device, where the state information is stored as a descendant state of an initial state of the target application, and interacting with the target application in accordance with a predefined simulation algorithm, thereby effecting a new state of the target application, until a predefined termination condition is reached.

Abstract: A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.

Abstract: A framework for maintenance, repair and overhaul business management includes a first layer identifying business areas in an MRO business, a second layer identifying one or more processes within each business area and a third layer identifying one or more sub-processes within each process wherein the business area include flight operations management, maintenance execution, maintenance management, engineering and maintenance support, material management, product development, enterprise management, strategic management, and demand generation.

Abstract: A method for building a magnetic bead mathematical model includes defining component elements of the model of the magnetic bead, building the model of the magnetic bead, obtaining a characteristic curve of an impedance of a magnetic bead in a standard magnetic bead specification of the magnetic bead, ascertaining parameters of the component elements, simulating the model of the magnetic bead, and comparing the characteristic curve with the characteristic curve in the standard magnetic bead specification, to further optimize the mode of the magnetic bead.

Abstract: An area partitioning processing unit equally partitions a power source network analysis object area of an LSI according to the number or size of partitioned areas specified by a user or partitions the power source network analysis object area according to the user's specification. A border processing unit extracts and adds a range-of-influence part of the power source network that can electrically influence a border between the partitioned area partitioned by the area partitioning processing unit and an adjacent power source network area. A modeling processing unit performs processing of resistance modeling of the partitioned area or a correction spot with the range-of-influence part added thereto by the border processing unit. A power source network analyzing processing unit analyzes a resistance model modeled by the modeling processing unit and calculates potential of each via as a current source to a load element.

Abstract: Formal verification of models using concurrent model-reduction and model-checking. For example, a system for formal verification of models includes: one or more model reducers to reduce a model; one or more model checkers to check the model, wherein at least one of the model reducers is to run concurrently with at least one of the model checkers; and a model synchronizer to synchronize information between at least one of the model reducers and at least one of the model checkers.

Abstract: The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized.

Abstract: An object-oriented software analysis framework is provided for enabling software engineers and hardware engineers to gain insight into the behavior of software applications on emerging hardware platforms even before the hardware is fabricated. In this analysis framework, simulation data containing instruction, address and/or hardware register information is sent to interchangeable and parameterizable analyzer and profiler modules that decode the data and perform analysis of the data according to each module's respective analysis function. This detailed analysis is performed by constructing a tree of such modules through which the data travels and is classified and analyzed or filtered at each level of the tree.

Abstract: A system receives a model, internals associated with a target processor, and code information associated with the target processor, and obtains a bit-true model simulation for the target processor based on the model, the target processor internals, and the target processor code information.

Abstract: An emulator, a system, and a method for emulating at least one controller of at least one technical facility, wherein an emulator is extended by at least one simulation of an operating system functionality and by a simulation of at least one system functional building block of the controller for high-availability communication to specify an emulation solution which is able to communicate with high reliability with real components from the automation environment through at least one network card and/or a communications processor and at least one communications layer for producing the high-availability communication. The system is networked with the technical facility following the loading of a facility configuration.

Abstract: A system for providing a virtual electronic device, which allows a user to experience the use of an actual electronic device like a real experience before purchasing the actual electronic device, is disclosed. The system may include a virtual electronic providing apparatus which includes a virtual electronic device having software and hardware interfaces for executing functions of an actual electronic device and executes the virtual electronic device in response to a request of a user terminal or transmits the virtual electronic device to the user terminal. Thus, the user can experience the major features of the actual electronic device in advance before purchasing the actual electronic device and sufficiently review the basic and additional features of the actual electronic device that the user wants to purchase.

Abstract: A method for designing a system on a target device is disclosed. A first plurality of components in the system are assigned to be placed by an computer aided design (CAD) tool based on a criterion. A second plurality of components in the system are assigned to be placed by a hardware placement unit based on the criterion. Placement results from the CAD tool and the hardware placement unit are used to generate a placement solution for the system on the target device. Other embodiments are described and claimed.

Abstract: A diagnostic support device supports a diagnosis of a display state of a composite image displayed on a display device that is arranged to display a composite image obtained by combining a plurality of composite target images corresponding to pieces of information supplied from respective devices mounted on a vehicle, the plurality of composite target images being combined with reference to layout information, the diagnostic support device including a layout information obtaining section arranged to obtain the layout information, a layout information output section arranged to output to an image combining apparatus, the layout information, per composite target image, the image combining apparatus combining the plurality of composite target images, and the layout information being obtained by the layout information obtaining section.