Abstract: A method for implementing at least one additional function of a field device in automation technology, wherein the field device is parametered and/or configured via a servicing device using a device description, wherein the method has the following method steps: the original device description, which comprehensively describes the field device, is made available; the original device description is expanded by a script or a supplemental device description fragment; wherein the script or the device description fragment comprehensively describes the additional function; and the field device is serviced from the servicing device by means of the expanded device description and is able to execute the additional function.

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.

Abstract: Verification tests perform hardware and software co-verification on a system under verification. Each signal interface controller coupled to the system performs a test action transferring at least one of stimulus signals and response signals between a corresponding portion of the system under verification and the signal interface controller during verification. A debugger controls an associated processing unit that executes software routines. A debugger signal interface controller performs test actions transferring stimulus signals and response signals between the debugger and the debugger signal interface controller during verification. A test manager transfers test controlling messages to these interface controllers identifying the test actions to be performed. As a result, the test manager controls the processing unit via the debugger signal interface controller and the debugger in order to coordinate the execution of the software routines with a sequence of verification tests.

Abstract: A method of reducing startup time of an embedded system can include: instantiating a circuit, specified by a first circuit design, within an integrated circuit (IC), booting a first build of an operating system executed by a processor to a steady state, and responsive to achieving the steady state, storing a circuit operational state of the circuit instantiated within the IC, an operational state of the processor, and a state of an executable memory utilized by the processor. A second circuit design can be created and a second build of the operating system can be created that collectively specify the circuit operational state, the operational state of the processor, and a state of an executable memory. The second circuit design and the second build of the operating system can be stored in the memory.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: The invention is directed to validating a specified manufacturing test rule, which pertains to an electronic component. The method includes generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected. The method further comprises constructing a testbench to prepare testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase.

Abstract: Method and system to configure a common set of electronic components using software in order to simulate different electronic, mechanical and/or electro-mechanical instruments or instrument functions. For each instrument function or traditional mode of operation to be simulated, software models are created which when directed to the electronic components, cause the electronic components to respond to input in the same manner that the actual, traditional physical instrument would respond to satisfy the same test requirement input. The software models are preferably stored in a model repository which is searchable to enable a user to select the instrument function or traditional mode of operation to be simulated with the corresponding model being provided to the electronic components. Once the model, i.e., a function for each synthetic element, is downloaded and the electronic components configured according to the model functions, testing of the assemblies or other UUTs can begin.

Abstract: The present disclosure provides systems and methods for a simulation environment that simulates hardware at a fiber level, a data plane level, a card level, and a chassis level. The simulation environment may be utilized in development and testing of complex, real time, embedded software systems, such as, for example, routers, switches, access devices, base stations, optical switches, optical add/drop multiplexers, Ethernet switches, and the like. In an exemplary embodiment, the simulation environment operates on one or more workstations utilizing a virtual machine to operate a virtualized module, line card, line blade, etc. Further, a plurality of virtual machines may operate together to operate a virtualized chassis forming a network element and with a plurality of virtualized chassis forming a network. Advantageously, the present invention provides state of the art data plane traffic and control plane simulation that reduces development time and cost while increasing design flexibility.

Abstract: In one embodiment, a system model models characteristics of a real-world system. The system model includes a plurality of sub-portions that each correspond to a component of the real-world system. A plurality of test vectors are applied to the system model and coverage achieved by the test vectors on the sub-portions of the system model is measured. In response to a failure of the real world system, a suspected failed component of the real-world system is matched to a particular sub-portion of the system model. A test vector to be applied to the real-world system to test the suspected failed component is selected in response to coverage achieved on the particular sub-portion of the system model.

Abstract: Methods and systems for simulating an electronic system in a high level modeling system (HLMS). A design block and certain signals of the electronic system are selected. The selected signals include internal signals of the design block that are not ports of the design block. The electronic system is simulated in the HLMS, which includes a hardware-based co-simulation platform and a software-based co-simulation platform. A hardware realization of the design block is automatically generated and the design block is emulated in the hardware based co-simulation platform using the hardware realization of the design block. A sequence of values is displayed for the selected signals of the electronic system. During the simulation of the electronic system in the HLMS, the sequence of values for the internal signals of the design block and another sequence of values for the ports of the design block are transferred between the co-simulation platforms.

Abstract: According to one embodiment, a simulation apparatus includes a hardware model execution unit that executes a hardware model, a software model execution unit that executes a software model, a simulation time management unit that sets a first simulation time indicating a total elapsed time of a simulation time of the hardware model, ahead by the simulation time of which the HW model notified, and sets the second simulation time indicating a total elapsed time of a simulation time of the software model, ahead by the simulation time of which the SW model notified, and a scheduler that compares the first simulation time with the second simulation time, causes the SW model or the HW model to be executed based on the comparison result, and causes only the hardware model to be executed instead of execution of an idle loop when the SW model awaits an interrupt from the HW model.

Abstract: Simulating an application. A method that may be practiced in a computing environment configured for simulating an application modeled by an application model deployed in a performance scenario of a computing system by deploying service models of the application model to device models modeling devices. The method includes referencing a performance scenario to obtain a transaction being modeled as originating from a first device model. The transaction invokes of a first service model. The first service model specifies hardware actions for simulation. The first service model is referenced to determine the hardware actions for simulation and the next referenced service. The next referenced service specifies hardware actions to be added to the transaction and may specify invocation of other service models. A chain of hardware actions is generated by following the invocation path of the service models. The hardware actions are applied to device models to simulate the transaction.

Abstract: An integrated development environment for rapid device development is described. In an embodiment the integrated development environment provides a number of different views to a user which each relate to a different aspect of device design, such as hardware configuration, software development and physical design. The device, which may be a prototype device, is formed from a number of objects which are selected from a database and the database stores multiple data types for each object, such as a 3D model, software libraries and code-stubs for the object and hardware parameters. A user can design the device by selecting different views in any order and can switch between views as they choose. Changes which are made in one view, such as the selection of a new object, are fed into the other views.

Abstract: Device, system, and method of storage controller simulating data mirroring. For example, an apparatus for simulating data mirroring includes: a storage controller to control a primary storage unit that has data stored therein, wherein the storage controller is able to simulate a process of mirroring data stored in the primary storage unit in response to a mirroring simulation command.

Abstract: A method and apparatus for web-based tool management are implemented. A tool object model provides a logical representation of the physical tool. The tool object model defines a hierarchical set of tool objects that characterize the tool, and additionally a set of method for performing actions on the tool objects. These actions also correspond to operations, which may include reporting as well as processing tasks, performed by the tool. A user may remotely control and monitor a tool using a conventional web browser. For example, a user may execute methods of the tool object model, or obtain detailed information about a tool object. User actions are passed to a server by embedding them in hypertext transfer protocol (HTTP) requests. The server receives the HTTP request, and passes the request to a corresponding page server in accordance with the action requested. Depending on the action requested, the page server may generate a web page in response, or may invoke a method of the tool object model.

Abstract: The links and chains (LNC) of this invention is an applications verification and validation (AVV) methodology. LNC is a hierarchical and systematic approach emphasizing conservation and reuse of effort expended. LNC creates objective metrics for validation. This invention ensures that the device will work in a system environment. LNC is an independent and complementary validation of the design before committing release to tape-out. The chip support library (CSL) and diagnostics used by LNC are natural outputs of the validation and are thus gating items to tape-out release. This ensures a fully tested device.

Abstract: An abstract trace may be defined based on a coverage goal. An execution of a System Under Test (SUT) is guided in accordance with the coverage goal. Non-deterministic decision, which correlates to receiving a stimulus to the SUT, is decided based on a probability function. After one or more executions, the probability function is modified based on a measurement of similarity between the abstract trace and each of the one or more executions. The modification of the probability function may be performed using on Cross-Entropy method. The modification is performed in order to cause determination of non-deterministic decisions in executions to better correlate with the abstract trace. In some exemplary embodiments, a determination whether the abstract trace is reachable is determined based on a rate of convergence of the executions to the abstract trace.

Abstract: A trace associated with an abstraction of a target device is utilized to guide an execution of the target device to be substantially similar to the trace. An execution of the target device determines a non-deterministic decision based on a probability function. The probability function is configured to increase the likelihood that the execution will be substantially similar to the abstracted trace. Cross-entropy method may be utilized to guide the execution of the target device.

Abstract: An operating environment emulation system includes a separate peripheral emulation system having a memory device. The memory device is operable to store one or more executable programs, referred to as emulators. The emulators are operable to emulate an original operating environment. Multiple emulators may be deployed on the emulation system to allow execution and presentation of an original operating environment on several different host computers. The system also includes a method for connecting the emulation system to a host computer or accessory device upon which the emulation will run. The emulator may employ insulation processes to limit interaction between the emulation system and host computer resources.

Abstract: Closed-loop control is applied to the field of automated on-line business bandwidth planning tools by comparing measured business bandwidth with a baseline for providing a difference indication, changing the baseline according to the difference, and reporting the change as an event relating to a service level agreement.

Abstract: A method and a respective apparatus for simulating a behaviour of a device does not have to change the mode of operation of the device. Furthermore it is possible to simulate improvement strategy step-wise and therefore calculate an impact of a process improvement project. Therefore an iterative simulation procedure is provided, which may find application in process improvement, such as software engineering process improvement, as well as optimization of performance parameters of devices and machines.

Abstract: A method is provided for constructing at least a functional model of a complex system including a plurality of components. The method includes constructing the functional model of the complex system, including a hierarchized set of modelled functional components. Each of the functional modelled components is an instance of an object class belonging to a specific set of object classes. The specific set of object classes includes a “Functional Router” class, representing an abstract model of a dummy router, which describes a set of interconnections between at least two modelled functional components, each instance of the “Functional Router” class being called a modelled functional router. The functional model of the system includes at least one functional modelled router.

Abstract: In a graphical modeling environment supporting a model having at least two different analysis frameworks operating therein, a system and corresponding method of processing the graphical model modify the model to group model portions together for processing in the same analysis framework. Model parts are identified and associated with the analysis framework in which they operate. Model parts are then grouped based on their association with their analysis framework to form model portions that operate in one of the different analysis frameworks. In instances where topological separation of model portions operating in the same analysis framework occurs, the system and method reconfigure intervening model portions to be amenable with operation in the analysis framework of the surrounding model portions to improve processing efficiency.

Abstract: A mechanism for exploiting the data gathered about a system model during the system design phase to aid the identification of errors subsequently detected in a deployed system based on the system model is disclosed. The present invention utilizes the coverage analysis from the design phase that is originally created to determine whether the system model as designed meets the specified system requirements. Included in the coverage analysis report is the analysis of which sets of test vectors utilized in simulating the system model excited individual components and sections of the system model. The present invention uses the information associated with the test vectors to select appropriate test vectors to use to perform directed testing of the deployed system so as to confirm a suspected fault.

Abstract: An efficient, cycle-accurate processor execution simulator models a target processor by executing a program execution image comprising instructions having run-time dependencies resolved by execution on an existing processor compatible with the target processor. The instructions may have been executed upon a processor in an I/O environment too complex to model. In one embodiment, the simulator executes instructions that were directly executed on a processor. In another embodiment, a markup engine alters a compiled program image, with reference to instructions executed on a processor, to remove run-time dependencies. The marked up program image is then executed by the simulator. The processor execution simulator includes an update engine operative to cycle-accurately simulate instruction execution, and a communication engine operative to model each communication bus of the target processor.

Abstract: A non-sensitive building is extracted according to radio environment data indicating the current condition of the radio communication environment in the search target area and digital map data including attribute information concerning the buildings in the search target area, thereby acquiring attribute information corresponding to the non-sensitive building. The known use condition data on target radio communication system or the similar system and the digital map data are used to obtain an equation for estimating the affect given to the effect of benefits by the attribute information parameter. According to the extracted non-sensitive building attribute information and the obtained equation, the effect obtained by performing the non-sensitive area countermeasure to each of the non-sensitive buildings is estimated. The priority of performing the non-sensitive area countermeasure is decided in accordance with the effect scale.

Abstract: Device, system and method for verification of a hardware system-under-test including at least one processor. A method includes building an executable image of a hardware exerciser adapted for execution on a test platform selected from: a simulation accelerator, a hardware emulator, a prototype hardware system, and a hardware production wafer. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.

Abstract: A method to validate data used in a design of a semiconductor product currently in a partially fabricated state is disclosed. The partially fabricated state having a plurality of layers up to and including a first conductive layer. The method generally includes the steps of (A) adding a second conductive layer from a user specification to an application set, the application set having a plurality of resources that define the semiconductor product, (B) validating a new resource in the user specification against the resources in the application set, (C) adding the new resource to the application set upon passing the validating and (D) propagating the new resource throughout a description of the semiconductor product, the description being stored in a computer-readable medium.

Abstract: A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools comprises less than all of the plurality of available tools. Each of the plurality of available tools is associated with one or more documents. Access to only those one or more documents associated with tools in the selected combination of tools is provided.

Abstract: Methods and systems for estimating the hypothetical performance of a messaging application are disclosed. A number of pool sizes may be identified, each pool size being a potential size for the memory allocated to the messaging application. An online simulation is running during the execution of the messaging application. The online simulation tracks the requests made by the messaging application and predicts the operation of the messaging application for each pool size. The data predicted includes the number of spill and unspill operations that read and write to disk. In addition, a method for calculating the age of the oldest message in a memory pool is disclosed. The age is used in determining the number of spill and unspill operations.

Abstract: A method of accurately simulating a target machine on a simulator, wherein, a mapping table is set up in a main program to record correspondence relations between target machine instructions and host machine instructions, and a signal handler is registered in a host machine for calling said mapping table. When an interrupt occurs while said simulator is performing simulation for a target program on the host machine, signal handler searches the mapping table to obtain or dynamically calculates to obtain host machine instruction corresponding to the next target machine instruction to be executed in target program; and replacing said host machine instruction with a return instruction, thus when executing said return instruction, the simulator will return to main program in checking said interrupt and proceeding with necessary proceedings required. Through the present invention, when said interrupt occurs, said simulator may return to main program in time for handling the interrupt.

Abstract: A method and corresponding equipment for emulation of a target programmable unit, which has at least one CPU, by means of an external emulation device, which is coupled to the target programmable unit by means of a communication link, comprising: transferring predetermined initialization data through the communication link to the emulation device for initializing the emulation; transferring through the communication link to the emulation device a CPU clock signal and emulation data; emulating the target programmable unit in the external emulation device using the transferred emulation data; ascertaining respective trace data from the emulation in the external emulation device and storing and/or outputting the trace data; deriving respective target integrity-control data and emulation integrity-control data from respective target-internal data and emulation-internal data; and transferring the derived target integrity-control data from the target programmable unit to the external emulation device.

Abstract: A method allocating firmware objects between different types of memory in a product model based on a frequency of access of each firmware object in trace data. The allocated firmware objects and trace data are used to simulate the performance of the product model. Memory access statistics obtained during the simulation may be used to analyze product model performance in the frequency and time domains.

Abstract: A high-speed multicore model simulator is realized. A multicore model simulator having a plurality of threads, and a plurality of core models executing the aforesaid plurality of threads is provided. The plurality of core models are a plurality of processor core models, each of which executes one thread, and they are synchronized with each other every predetermined number of execution instructions of each thread.

Abstract: A graphical modeling environment is provided for a user to build a model for physical systems using blocks connected through signals. The user may build a model with the flexibility of user-defined implementations available in the graphical modeling environment and with the architecture provided by modeling tools for modeling physical systems. A two-way connection port may be provided for adopting an architecture that supports modeling of physical systems in the graphical modeling environment. The user may use the two-way connection port to make the model built in the graphical modeling environment look architecturally like a model built using physical modeling tools.

Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: A production program creating system creates a production program having a module in which a processing for producing a board is described. The board is produced by mounting an electronic component supplied from a component feeding device onto the board by means of a component mounting device. The component mounting device is described in model form, and a configuration information of the component mounting device is stored in a database. The module is created such that the module works with respect to the component mounting device that is described in model form, and such that the module performs a generalized processing by acquiring the configuration information of the component mounting device from the database.

Abstract: A system and method for simulating an attention (AT) command test of a mobile phone reads an AT function from an AT script file. If the AT function is a passive request function, the AT function is executed directly. If the AT function is an active request function, the system receives an AT request from an application program of the mobile phone. The AT request is converted into environment variables recognizable by the AT script file. If the environment variables match the AT function, the AT function is executed and an AT response is generated. The application program receives the AT response.

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract: A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.

Abstract: A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools comprises less than all of the plurality of available tools. Each of the plurality of available tools is associated with one or more documents. Access to only those one or more documents associated with tools in the selected combination of tools is provided.

Abstract: A method and system reuse data logs generated from testing of programmable devices in order to provide an input file of parameter values and settings for use in automatically configuring a device simulator. The programmable device testing process generates a data log output with data formatted so that parameter data are associated with unique variable labels. The data log output file is processed in a parser operation that filters out private and unnecessary information, organizes the data and generates a simulation input file in a format compatible with the simulator. The process can be fully automated.

Abstract: Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate the data. In addition, the method enables read commands to be generated in a different sequence from the sequence of generated write commands, having different sizes than the sizes of the write commands, and that maximize the amount of data read (verified) and minimize the amount of unnecessary reads (re-verification).

Abstract: A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model.

Abstract: A simulation method includes obtaining an execution log generated while a predetermined processing is executed by simulating a series of operations in a test model that is a modeled version of a test target device by causing a predetermined processing to be executed in the test model, extracting a processing unit log constituted by a predetermined processing unit from the execution log obtained in the obtaining, and simulating an operation in which processing corresponding to the processing unit log extracted in the extracting is executed in a test model in which a part of function of the test target device is modified, the operation being simulated on the basis of a setting condition set by a user.

Abstract: A system and method for implementing a unified model for integration systems is presented. A user provides inputs to an integrated language engine for placing operator components and arc components onto a dataflow diagram. Operator components include data ports for expressing data flow, and also include meta-ports for expressing control flow. Arc components connect operator components together for data and control information to flow between the operator components. The dataflow diagram is a directed acyclic graph that expresses an application without including artificial boundaries during the application design process. Once the integrated language engine generates the dataflow diagram, the integrated language engine compiles the dataflow diagram to generated application code.

Abstract: A partitioning method for an integrated circuit (IC) design includes providing a textual file representing the design as library-specific cells and interconnections, including timing data for the cells and timing data derived from the design after placement and routing. The design is flattened to cell level. Edge-triggered flip-flops (ETFF's) are selected and divided into two groups by communications attributes. First group is subdivided into the number of subsets in the partition. The ETFF's in each subset are analyzed by their communications attributes, and divided into those that connect to circuit elements outside the particular subset, and those that do not, reducing intersubset communications and placing them under external clock control. The partition is electrically equivalent to the design. The design is simulated by placing each subset on its own computer with simulator software. The computers are interconnected. User interventions may be allowed.

Abstract: A system for subjective evaluation of a vehicle design within a virtual environment includes a scaleable physical property representative of the vehicle design and a computer system for digitally creating a virtual environment having a virtual human immersed within. The system also includes a motion capture system for sensing a motion of an evaluator and communicating the sensed motion of the evaluator to the computer system and a virtual reality display mechanism for providing the evaluator a view of the virtual environment while evaluating the vehicle design.