Abstract: A method for changing operation of a device, comprising: sending target device descriptors to the device's device emulator, which processes and stores the descriptors as the current descriptors in memory, and the device emulator responding to a query from a host simulating operation of the target device. Using the method, the host recognizes the device as a different, target device, such as printers, MFPs, peripherals, digital cameras, etc. Device emulation enables installation and other testing of a new and yet unavailable target device under development. The methods also include USB device enumeration, making a print job containing extended PJL commands and sending it using a generic device driver, emulator firmware analyzing and storing the descriptors in registers, sending a line reset command to simulate device detachment and reattachment, and meeting timing requirements of USB detached and attached states.

Abstract: A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for example. A defined time region associated with the particular IC block event is divided into multiple time segments, whereupon at least a first current value and a second current value for each time segment is obtained based on the current demand curve. Thereafter, the current demand curve is approximated, on a segment-by-segment basis, using a select approximate waveform depending on a relationship between the first and second current values.

Abstract: The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating (80) a first file (FCH1) for configuring the test environment, and a second phase of generating (81) a second file (FCH2) for configuring at least a part of the design under test, the delivery of the first configuration file to a first reconfigurable hardware part (BTR) forming a reconfigurable test bench so as to configure the test bench, and the delivery of the second configuration file to a second reconfigurable hardware part (EML) so as to configure an emulator of the design under test, the two hardware parts being distinct and mutually connected.

Abstract: A circuit analyzing device includes: a peripheral input signal setting part configured to make a signal setting by a predetermined requirement for a peripheral input which does not logically affect operation of the predetermined circuit part, upon analyzing a signal delay in operation of a predetermined circuit part, and wherein: analysis is made for a signal propagation operation delay in operation of the predetermined circuit part, in consideration of influence of the signal input from the signal setting.

Abstract: A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.

Abstract: Techniques are presented for a multi-tier distributed frame work for mass configuration of products by design and synthesis. Products are represented as components having hierarchical relationships with one another. The components include form information, function information, behavioral information, and constraint information. Components may be created from scratch or retrieved from a plurality of sources over a network. In some embodiments, the components may include optimization constraints and derived from other components to meet the optimization constraints.

Abstract: A method of initiating re-enumeration of a USB device without manual intervention is provided. The method involves a sequence emulating detachment and re-attachment of a device to the host while the device remains attached to the host. As the device remains attached to the host throughout the sequence, the host OS is manipulated to receive a plurality of preset device states in order for it to perceive a device change and to eventually initiate device enumeration. The sequence, which involves a series of command exchanges between the device and the host, may be initiated by a software application residing in the host upon an event requiring device enumeration.

Abstract: A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

Abstract: In accordance with certain aspects of the model-based policy application, each of a plurality of policies is associated with appropriate parts of a model of a heterogeneous system. A deployment agent is invoked to apply each of the plurality of policies to components associated with the parts of the model. An identification of a change to one of the plurality of policies is received, and the deployment agent is also invoked to apply the changed policy to selected ones of the components associated with the parts of the model.

Abstract: A method, apparatus, and computer program product for identifying dissimilarity indices for a structure is presented. A first test signal is sent into a baseline model of the structure. An estimated response signal to the first test signal sent into the baseline model of the structure is received. A second test signal is sent into the structure. A second response single to the second test signal is received. A value is assigned to a model-based dissimilarity index using the first response compared to the second response.

Abstract: A portable device is connected to a host system that operates according to a first industry standard architecture (e.g., a personal computer built according to the IBM Personal Computer standard). The user initiates a session in the host system using the software and data in the portable device. The user suspends the state of the session, the state is stored in the portable device, and the user disconnects the portable device from the host. The user later connects the portable device to a second host that operates according to a second industry standard architecture (e.g., Apple Macintosh™ computer). The second host boots an autoconfiguring host operating system stored in the portable device and starts a virtual machine layer also stored in the portable device. The user then resumes operation of the suspended virtual machine layer session.

Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple physical domains. A graphical program may be received which includes a first portion of a first physical domain for simulating a first portion of a physical system. The graphical program may include a second portion of a second physical domain for simulating a second portion of the physical system. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to simulate the physical system.

Abstract: A software development technique is provided using target system virtualization software simulating behaviour of a target system. A target device driver running on a host system issues memory access commands to the target system virtualization software rather than to a memory interface unit of the host system. The memory interface unit may be an SRAM (Static Random Access Memory) interface. The target system may be an EGPRS (Enhanced General Packet Radio Service) modem.

Abstract: A method, apparatus, and computer program product are presented for automatically evaluating Bayesian network models. Operations performed comprise receiving a Bayesian Network (BN) model including evidence nodes and conclusion nodes that are linked with the evidence nodes by causal dependency links, and where the evidence nodes have evidence states and the conclusion nodes have conclusion states. The states of conclusion nodes are set to desired conclusion states and corresponding probabilities of occurrence of evidence states are determined by propagating these states down the causal dependency links. Thus, samples of most likely states of the evidence nodes are generated. Then, states of the evidence nodes are set corresponding to the samples of the evidence states. These states are propagated back up the causal dependency links to obtain probabilities of the resulting states of the conclusion nodes. Finally, a representation is outputted for the probabilities of the states of the conclusion nodes.

Abstract: A simulation method and system. The method includes receiving by a simulation engine in a device driver, input simulation parameters data associated with a simulation process. The simulation engine calculates a simulated scale down process time period for a device associated with the device driver. The simulation engine simulates the device. The simulation engine calculates an overall runtime period for the device. The overall runtime period is calculated based on the simulated scale down process time period. The simulation engine transmits the overall runtime period to a simulator software application for generating an operating schedule for operating the device.

Abstract: A technique for emulation of a data storage system. The invention allows the level of services to be provided by a data storage system to be specified in terms of the level of services provided by another storage system. In one aspect, a performance characterization of a data storage device to be emulated is obtained (e.g., by experimental techniques). A specification of a workload is also obtained that includes a specification of a plurality of data stores for the workload. The data stores are assigned to an emulation data storage device according to the performance characterization and according to the specification of the workload such that sufficient resources of the emulation data storage device are allocated to the workload to meet the performance characterization of the data storage device to be emulated. The emulation data storage device is then operated under the workload. Quality-of-service (QoS) control may be performed so as to provide a degree of performance isolation among the workloads.

Abstract: A simulation that integrates historical data and real-time data as a test or simulation tool can capture an entry that relates to a desired output as function points. A determination can intellectually be made as to which activities can achieve the desired output. The activities can be process steps that can represent a workflow that can be automatically implemented by an MES Appliance or other enterprise components. If a simulation reveals that the desired output might not be achieved, a change to one or more function points can be analyzed in an attempt to achieve the desired result. This change can be input into a simulation tool through a feedback loop, for example. Another simulation can performed on the modified data until a determination is made that the desired output can be achieved.

Abstract: The present invention provides for native execution of an application on a client using code segments transmitted from a server over a network. The server includes an application code source, and a server code segment manager. The server may also include an application code transformation manager if the code source is not in the native binary format of the client. The client includes a client code segment manager, a code cache linker and manager, a code cache, and a CPU. When the client seeks to execute an application, code segments are transmitted from the server to the client and are stored in the code cache. The CPU then executes the code segments natively. When a code segment branches to a segment not in the cache, control passes to the client code segment manager, which requests the needed code segment from the server code segment manager of the server.

Abstract: A method of emulating a service in a computer infrastructure includes the steps of providing a service proxy instance as a stand-in for the service and running the service proxy instance on a computer accessible to the computer infrastructure. The service proxy instance is configured at run time in accordance with a configuration file, wherein the configuration file includes an operating mode specification. The service proxy instance communicates with at least one destination in adherence to the operating mode specification and a communication protocol.

Abstract: A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.

Abstract: A firmware providing method in which firmware for an electronic device is downloaded from a service server provided on a communication network to a communication terminal. Display information to be displayed on a display of the electronic device is stored in the service server as language standard data that responds to a plurality of languages in accordance with a model of the electronic device. The communication terminal downloads, from among the language standard data, data in which a model of the electronic device and a language are specified, edits at least a portion of the language standard data, and then transmits the edited display information to the service server. In response thereto, the service server generates firmware for the electronic device of the same model based on the edited display information and returns the firmware to a return target terminal.

Abstract: A method of verifying a chip design includes: a software side operation step of transmitting output data generated by an operation of a software block to an interface unit, determining whether output data of a hardware block received via the interface unit is valid by executing a chip design verification program, and applying only valid output data of the hardware block to the software block; and a hardware side operation step of transmitting output data generated by an operation of the hardware block to the software block, determining whether the output data of the software block received is valid by executing the chip design verification program in the interface unit, and applying only valid output data of the software block to the hardware block.

Abstract: A network troubleshooting framework is described. In an implementation, a method includes generating a first estimation of network performance by a simulator based on network settings obtained from a network, estimating the new performance under an alternative setting by providing the alternative setting to the network simulation and observing the simulation output, repeating the procedure for other alternative settings, and suggesting the alternative setting that improves network performance.

Abstract: The present invention relates to an electronic device for emulating other electronic devices comprising an interface (6) for enabling communication within a network (11), an embedded emulation system (10) for emulating at least a second electronic device (12), said embedded emulation system (10) comprising transmission emulation means (9) for creating messages to be sent via the interface (6), said messages having as sender address the address of the second electronic device (12). The present invention further relates to a method for operating an electronic device.

Abstract: Multiple users may simultaneously edit a shared area of a printed circuit board design. In order to prevent conflicts between multiple users, a user draws a protection border around a portion of his or her workspace so as to temporarily reserve the protected portion and prevent editing by other users. The protection border may be broadcast to other users. The protection border may also define a protected region in which a user may evaluate alternative design changes without requesting corresponding changes to a master PCB design.

Abstract: Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating the stop. The other processing core receives the first hardware signal and stops operation. Both processing cores stop at approximately the same time based on the first hardware signal. Thereafter, the first or second processing core receives another software command to resume operation and generates a second hardware signal indicating resumption of operation. The other processing core receives the second hardware signal and resumes operation. Both processing cores resume at approximately the same time based on the second hardware signal. The first and second hardware signals may come from the same or different processing cores.

Abstract: A fixed MAC address of a cable modem is used to generate a series of unique MAC Addresses in order to simulate multiple cable modems from the CMTS's point of view. Before a scheduled maintenance operation, a simulated MAC address value is disbursed to pertinent hardware registers in the cable modem. When the station maintenance occurs, the simulated MAC address value is sent in place of the fixed original address.

Abstract: Aspects of the subject matter described herein relate to simulating storage devices. In aspects, a test automation engine instructs a simulator to simulate a storage device having certain characteristics such as a storage area network. The test automation engine then tests an application against the simulated storage device. Tests may include storage management requests and storage access requests. A provider may translate a request to one or more operations suitable to perform the request on the underlying simulated device. Shadow copies and the results of other storage management-related operations may be shared across computers via aspects of a simulation framework described herein.

Abstract: A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.

Abstract: Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Abstract: A method for evaluating performance of DMA-based algorithmic tasks on a target multi-core processing system includes the steps of: inputting a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; evaluating performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and providing results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Abstract: A test method for a data processing device includes determining both a current state of the device and a desired state of the device. A set of instructions to transition the data processing device from the current state to the target state is obtained by initially selecting a first source state from a set of possible source states and corresponding instructions that can transition the device to the desired state. The instruction associated with the first source state is placed on an instruction stack. The source state and instruction selection process is repeated until the selected source state corresponds to the current state of the device under test. The instructions in the stack are applied to the device under test, and the resulting device state compared to the specified state to determine a test result.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to optimization profile generation and provide a method, system and computer program product for user guided generation of network link optimization profiles. In one embodiment of the invention, a network optimization profile generation method can be provided. The method can include ranking different performance criterion for a target network, testing the target network for the different performance criterion, weighting results of the testing according to the ranking of the different performance criterion, generating a set of target network configuration parameters through optimization of the weighted results, for instance simulated annealing, and applying the set of target network configuration parameters to the target network as a profile.

Abstract: A computer implemented method and system for the generation of software thermal profiles for applications executed on a set of processors in a simulated environment. Execution of a software program being run on a software simulator is detected and hardware operations for the software program being executed by the set of processors are analyzed to create analyzed information. Then, a thermal index is generated based on the analyzed information.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to process modeling and provide a method, system and computer program product for modeling alternate processing times based on user supplied expressions. In one embodiment of the invention, a method for modeling alternate processing times based on user supplied expressions can be provided. The method can include loading simulation variables for a simulated task in a model, computing a duration of time for the simulated task based upon the simulation variables, and simulating execution of the simulated task for the computed duration of time. For example, loading simulation variables for a simulated task in a model can include loading a level of expertise for a role assigned to the task, loading a time of day for executing the task, or loading a time of year for executing the task.

Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.

Abstract: Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

Abstract: Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

Abstract: A system for applying distributed software simulation techniques to hardware emulation may include a first hardware emulator mounted on a first expansion board at a first host, and a second hardware emulator mounted on a second expansion board at a second host. The first hardware emulator may be configured to emulate a first portion of a system under test, and the second hardware emulator may be configured to emulate a second portion of the system under test, and the first and second hardware emulators may coordinate an emulation of the system under test using one or more messages, i.e., a coordination of an emulation of the system under test may be accomplished using communications between the first and second hardware emulators.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: In one embodiment, a distributed simulation system may include a first node configured to participate in a simulation and a second node configured to transmit a hot pull command designating the first node. The first node does not participate in the simulation responsive to the hot pull command. In another embodiment, A distributed simulation system may include a first node configured to participate in a simulation and a second node configured to transmit a hot plug command designating the first node. The first node does not participate in the simulation prior to the hot plug command. Additionally, the first node begins participation in the simulation responsive to the hot plug command.

Abstract: An object of the present invention is to provide a bridge program capable of achieving common use of the interface between a plurality of modules having different configurations and a hardware model obtained by modeling hardware with software. A bridge program allows a computer to execute: an acquisition step that acquires an operation instruction issued from the module to hardware model; a conversion step that converts the interface of the module into a common interface corresponding to the hardware model; and a discrimination step that acquires the operation instruction acquired by the acquisition step via the common interface into which the interface of the module is converted by the conversion step, discriminates to which hardware model the operation instruction is issued, and outputs the operation instruction to the discriminated hardware model.

Abstract: A system for providing a runnable computer simulation model comprises a design automation software product for enabling a designer to create a simulation model including interconnected component and/or subsystem models. The system also comprises a simulation content file creation means for creating a simulation content file that includes information describing the simulation model; and a simulation player software product including means for reading the simulation content file. The simulation player software product enables an end user to run the simulation model based upon the information in the simulation content file, but does not allow the end user to add or remove component models, subsystem models or interconnections of the simulation model.

Abstract: Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: An apparatus, system, and storage medium that, in an embodiment, simulate allocation of a simulated resource to simulated partitions in a simulated logically-partitioned computer and determine whether the allocation conflicts. The simulation may include summing amounts of the simulated resource for the simulated partition in an order, where the order of the simulated partitions is received via a user interface. In various embodiments, the allocation may conflict if the allocation exceeds the capacity of the simulated logically-partitioned computer or if the simulated resource is restricted to exclusive allocation. The result of the simulation, including whether the allocation conflicts, is presented via the user interface. In various embodiments, the simulated resource may be memory, an I/O controller, or a storage device.

Abstract: A system for interfacing hardware emulation to software simulation environments may include a simulation node configured to simulate a first portion of a system under test and a hardware emulation node configured to emulate a second portion of the system under test. The hardware emulation node may also be configured to exchange simulation information (such as representations of signal values obtained as output from the emulated portion of the system under test) with the simulation node. The hardware emulation node may contain a field programmable gate array devices (FPGA) configured to perform the hardware emulation. The FPGA may be mounted on an expansion board, such as a PCI (Peripheral Component Interconnect) board.

Abstract: Disclosed is an architecture for automating testing tasks, which would otherwise have to be done manually using actual hardware, by providing the capability to dynamically create many types of networked computing devices with different network configurations, eliminating the need to have actual test machines physically networked. Virtual endpoints are virtual computing devices networked to virtual adapters on a real computer. The virtual endpoints architecture comprises a miniport driver, a filter engine, virtual networked computing devices, a virtual stack, and a user mode to kernel mode interface. The virtual endpoints architecture technology can be used to test bridge and Internet connection sharing features as well as for testing any NDIS driver or client/server application. The virtual endpoints architecture lowers the cost of testing and allows for the ability to run the aforementioned types of tests in a batch nodal stress suite and without the need for large test network topologies.

Abstract: A method for simulating analog behavior of a circuit in a simulation system includes representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that has one or more subcircuits and a second branch that also has one or more subcircuits. The first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches.