Abstract: A method for configuring and executing card content management (CCM) operations in a declarative manner includes composing a CCM operation declaration, wherein each CCM operation includes one or more CCM scripts and storing the CCM operation declaration in memory. When provisioning is needed, applicable scripts for the CCM operation declaration are fetched from the memory. An execution context needed for each script in the CCM operation declaration is prepared. The scripts are executed in an order specified in the CCM operation declaration.

Abstract: A computer implemented method receives a request to run a group of instruction sets. Each instruction set is associated with a sequence of common instructions. The method executes the sequence of common instructions in a first virtual machine (VM) to generate a result which is stored in a first memory associated with the first VM. The method then clones a second VM that shares the first memory with the first VM. The method continues by executing a first instruction set in the second VM. Since the second VM shares memory with the first VM, the second VM can use the result stored in the first memory and the sequence of common instructions does not need to be executed on the second VM. In one example, the result is a run-time model of a circuit and the second VM runs the first instruction set on the run-time model.

Abstract: Systems and methods for providing one or more services via a remote device are disclosed. One method can comprise identifying one or more services available at a location, transmitting identification data to a remote device disposed remotely from the location, the identification data relating to the one or more services identified, receiving a selection of the one or more services available, and providing the selected one or more services available to the remote device.

Abstract: A control-circuit of an emulation system may include one or more serial link inputs communicatively coupled to a serial bus, a serial link input receiving an input control bit from the serial bus. A configurable logic circuit may be configured to receive multiple control bits from the one or more serial link inputs, execute one or more operations on the plurality of input control bits according to programmable logic, and transmit an output control bit to a serial output link.

Abstract: Disclosed are various embodiments enabling a saved state of an application to be stored at a central location and to be retrieved by multiple computing devices executing the application. Accordingly, saved states of applications and interfaces are also enabled to follow a user from one personal computing device to the next.

Abstract: Example implementations relate to a server including a platform controller hub (PCH), where the PCH includes a peripheral device manager, a management processor coupled to the peripheral device manager, and a peripheral device interface to couple with a peripheral device and provide out of band access of the peripheral device via the management processor and peripheral device manager to a memory of the server.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: Techniques to facilitate demonstrating changes to mobile applications are disclosed herein. In at least one implementation, an instance of a virtual mobile device is executed on a computing system, wherein the virtual mobile device comprises at least one mobile application. Instructions are received to change at least one visual element of the at least one mobile application. The instructions are processed to generate a screenshot of the change to the at least one visual element. The screenshot of the change is transferred for delivery to a remote computing system, wherein the remote computing system displays the screenshot of the change.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: Systems and methods are disclosed for initiating data transfer operations between data storage devices based at least in part on relative physical orientation or position of the data storage devices. Data storage devices are disclosed that include a physical enclosure, a non-volatile memory disposed within the physical enclosure, one or more sensors, and a controller configured to determine a physical orientation of the data storage device relative to another data storage device using the one or more sensors and initiate a data storage operation involving the data storage device and the other data storage device based on the physical orientation.

Abstract: A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.

Abstract: Disclose are systems and methods for execution of program code by an interpreter. One exemplary method comprises: executing, by the interpreter, instructions of the program code in an emulated computer environment; when detecting, by the interpreter, an instruction of the program code associated with an unknown object for which the interpreter lacks a rule of interpretation, halting by the interpreter further execution of the instructions of the program code; obtaining, by the interpreter, an auxiliary code whose result of execution corresponds to the result of the execution of the unknown object, wherein the auxiliary code contains known objects for which the interpreter has a rule of interpretation; executing, by the interpreter, the instructions of the auxiliary code; and after completion of the execution of the auxiliary code, by the interpreter, resuming the execution of the instructions of the program code.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: A load control device is able to receive radio-frequency (RF) signals from a Wi-Fi-enabled device, such as a smart phone, via a wireless local area network. The load control device comprises a controllably conductive device adapted to be coupled in series between an AC power source and an electrical load, a controller for rendering the controllably conductive device conductive and non-conductive, and a Wi-Fi module operable to receive the RF signals from the wireless network. The controller controls the controllably conductive device to adjust the power delivered to the load in response to the wireless signals received from the wireless network. The load control device may further comprise an optical module operable to receive an optical signal, such that the controller may obtain an IP address from the received optical signal and control the power delivered to the load in response to a wireless signal that includes the IP address.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a page walk using a guest physical address (GPA) and to detect whether a page identified with the GPA is mapped with sub-page permissions; a sub-page control storage to store at least one GPA and other data related to a sub-page; the page miss handler to determine whether the GPA is programmed in the sub-page control storage; and the page miss handler to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page control storage when an access matches a TLB entry with sub-page protection indication.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: Exemplary methods, apparatuses, and systems include a first network edge device configuring a mapping between a physical network interface and a plurality of logical interfaces. A second network edge device also configures a mapping between a physical network interface and a copy of the plurality of logical interfaces. Each of the logical interfaces is assigned a corresponding set of first and second layer networking addresses that is replicated across the first and second network edge devices. The first network edge device receives a first address resolution request via the physical network interface of the first network edge device that includes a source and a destination. The destination is an address assigned to one of the plurality of logical interfaces. The first network edge device determines a second layer networking address assigned to the destination logical interface and transmits an address resolution response including the determined second layer networking address.

Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.

Abstract: System, method and media are shown for detecting potentially malicious code by iteratively emulating potentially malicious code, that involve, for each offset of a memory image, emulating execution of an instruction at the offset on a first platform and, if execution fails, determining whether the instruction at the offset has relevance to at least a second platform and, if so, emulating execution of the instruction at the offset on the second platform. If execution succeeds, it involves checking the behavior of the executing code for suspect behavior, and identifying the executing code as malicious code if suspect behavior is detected. Refinements involve applying this process to also determine aspects of information related to the target of any discovered code, malicious or otherwise.

Abstract: Techniques for handling dynamic cascade port/LAG changes in an extended bridge are provided. According to one embodiment, a first network device in an extended bridge can maintain a shadow table that stores information regarding one or more ports and one or more LAGs used to interconnect the network devices in the extended bridge. The first network device can further receive, from a user via a device UI, a command relating to a change to a port or a LAG, update the shadow table based on the change, transmit a change message to one or more other network devices affected by the change, and start a timer associated with the one or more other network devices. In various embodiments, the updating and the transmitting can be performed without blocking the user from entering further commands via the device UI.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: An approach to dynamic run-time alias checking comprising creating a main thread and a helper thread, computing an optimized first region of code in a rollback-only transactional memory associated with the main thread checking for one or more alias dependencies in an un-optimized first region of code, responsive to a determination in a predetermined amount of time that no alias dependencies are present in the un-optimized first region of code, committing a transaction and responsive to at least one of a failure to determine results of the check for one or more alias dependencies in the predetermined amount of time and a determination in the predetermined amount of time that alias dependencies are present in the un-optimized first region of code, performing a rollback of the transaction and executing the un-optimized first region of code.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: An information processing device includes an identification part configured to, in response to a user's operation to start any given one of a plurality of first application programs, determine whether the start of the one of the first application programs is allowed; and a request part configured to request the one of the first application programs to display a first screen which indicates the start of the one of the first application programs is not allowed when the identification part determines that the start of the one of the first application programs is not allowed, and request a second application program to display a second screen including a message when the identification part determines that the start of the one of the first application programs is allowed and when the message needs to be given.

Abstract: The methods and systems can include a database management component configured to manage database instances, the database management component also configured to receive a first data request operation on the distributed database, an execution component configured to process the first data request operation including at least one write request on at least one database instance managed by the database management component, and a fault prediction component configured to detect a potential page fault responsive to a target data of the write request, wherein the execution component is further configured to suspend execution of the first data request operation, request access a physical storage to read the target data into active memory, and re-execute the first data request operation after a period of time for suspending the first data request operation.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing a framework for collaborative debugging. In one aspect, a method includes generating a session for an application executing on a remote debugging system and during the session, receiving one or more application inputs for the application from one or more remote users and providing outputs generated by the application for presentation to the one or more remote users. The method further includes receiving a request to restart the session from a particular remote user, in response to receiving the request to restart the session, resubmitting the one or more application inputs to the application to replicate an ending application state for the session, and providing, for presentation to the particular remote user, a restarted session for the application starting from the ending application state.

Abstract: A method of operation of an automatic back-up system includes: providing a mobile device; coupling a removable media device to the mobile device; automatically launching an application on the mobile device; and backing-up user data selected by the application from the mobile device to the removable media device.

Abstract: A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.

Abstract: A baseboard management controller (BMC) of a system can receive a first serial output from a first server device and a second serial output from a second server device. The BMC can send the first serial output and the second serial output to a network interface controller (NIC) for transmission over a network to a computing device.

Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

Abstract: Methods and systems are disclosed for determining a CPU usage adjustment factor and for automatically applying the CPU usage adjustment factor to provide a CPU usage estimate for an SMT processor. In one implementation, the methods and systems obtain samples of CPU usage reported by the operating system at a predefined sampling rate over a predefined sampling interval. Thread states for the threads substantially corresponding to the reported CPU usage are so obtained at the predefined sampling rate and over the predefined sampling interval. This sampling may be performed for servers running different applications and having diverse processing loads. An estimate of the distribution of the number of threads running for the CPU usages reported may then be determined from the sampled data. A CPU usage adjustment factor may then be derived, based on the distribution, and used to provide a CPU usage estimate.

Abstract: Systems and methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multi-core processors to reduce system latencies and increase system performance. In one arrangement, a multicore processor includes a vertical pre-fetch random data buffer structure that stores random data being continuously generated by a random data generator (RNG) so that such random data is ready for consumption upon request from one or more of a plurality of processing cores of the multicore processor. Random data received at one data buffer from a higher level buffer may be automatically deposited into the lower level buffer if room exists in the lower level buffer. Requesting strands of a core may fetch random data directly from its corresponding first level pre-fetch buffer on demand rather than having to trigger a PIO access or the like to fetch random data from the RNG.

Abstract: A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory conflicts for shared logical memory in transactional memory based on logical (virtual) addresses comparisons.

Abstract: Changes to information are managed by storing information as a plurality of objects. Each object has one or more states. One or more temporal histories are maintained for each object based on the plurality of states of the object at a plurality of time instances. For each state of the object, whether or not the state is a user of another state of the object or another object is determined. When a request to change the information is received, at least one state of at least one of the plurality of objects is selectively changed. When it is determined that the at least one state is the user of another state, then the changing is further responsive to changes in the another state.

Abstract: A computing system in which a software component executing on a platform can reliably and efficiently obtain state information about a component supported by the platform through the use of a shared memory page. State information may be supplied by the platform, but any state translation information needed to map the state information as supplied to a format as used may be provided through the shared page. In a virtualized environment, the state translation information can be used to map the value of a virtual timer counter or other component from a value provided by a virtual processor to a normalized reference time that will yield the same result, regardless of whether the software component is migrated to or from another virtual processor. Use of a shared page avoids the inefficiency of an intercept into a virtualized environment or a system calls in native mode operation.

Abstract: A data storage system implements out-of-order data transfer. In one embodiment, the data storage system can retrieve from a host system a scatter gather list (SGL) associated with a data read command and generate a memory access table based on the retrieved SGL. The data storage system can further retrieve data from memory, and at least some data may be retrieved out of order. Retrieved data can be provided to the host system using the memory access table, and at least some data may be provided out of order. Data retrieval performance can be increased.

Abstract: A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a desired partition within the emulator. The emulator automatically determines the availability of the partition requested. If the partition is not available, the design is dynamically remapped to a different partition that is available. In another embodiment, clocks associated with the integrated circuit design are also dynamically remapped. In yet another embodiment, the user can control the size of the partitions (e.g., the number of printed circuit boards in a partition).

Abstract: Described herein are a processor and a method of operating the processor to simulate a many-core target machine. The processor includes a plurality of processing cores arranged in a predetermined manner and a global target clock counter (GTCC) configured to count a number of simulated clock cycles in the target machine. A global stall controller (GSC) configured to halt execution of all the processing cores based on a determination of at least one processing core being in a fault condition; and wherein the processor acquires a base clock per instruction (CPI) of a target machine, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, translates an application of the target machine to a compact executable trace to be executed by the processor, and adjusts a speed of simulation by adjusting an update rate of the global target clock counter.

Abstract: An approach to dynamic run-time alias checking comprising creating a main thread and a helper thread, computing an optimized first region of code in a rollback-only transactional memory associated with the main thread checking for one or more alias dependencies in an un-optimized first region of code, responsive to a determination in a predetermined amount of time that no alias dependencies are present in the un-optimized first region of code, committing a transaction and responsive to at least one of a failure to determine results of the check for one or more alias dependencies in the predetermined amount of time and a determination in the predetermined amount of time that alias dependencies are present in the un-optimized first region of code, performing a rollback of the transaction and executing the un-optimized first region of code.

Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.

Abstract: A programmable controller includes a command executing engine unit that performs a user program and performs a computing process and nonvolatile memory that stores the result of the computing process. The command executing engine unit transitions to a temporary stop state in which a new cycle of computing process is not performed and stores the result of a cycle of computing process in the nonvolatile memory when the cycle of computing process of the user program ends, and releases the temporary stop state and transmits the result of the cycle of computing process stored in the nonvolatile memory to a simulation device when a stop release instructing command instructing to release the temporary stop state is received from the simulation device.

Abstract: Methods and systems for recognizing textual identifiers within a plurality of words are described. A textual representation of a voice input is received from a user. The textual representation includes a plurality of words. A keyword is identified in the textual representation. It is determined whether one or more words adjacent to the keyword correspond to a textual identifier of a collection of textual identifiers. Responsive to a determination that the one or more adjacent words correspond to a textual identifier, the keyword and the one or more adjacent words are replaced with the textual identifier.

Abstract: The subject disclosure relates to a method and system for packaging a post-processed definition of a programming module. Contents of a constraint-based and/or order-independent execution model are received, in which the contents include a declarative source code. The contents are stored into an extensible storage abstraction such that the source code is stored in a declarative format. Metadata describing attributes of the contents stored in the extensible storage abstraction is also defined. A file is then created, which includes the extensible storage abstraction and the metadata.