Abstract: A system to prototype a system-on-chip design is presented. In one embodiment, the system includes an electronic board comprising a logic device programmable to emulate system components. The system further comprises a processor to execute a virtual machine monitor which redirects an input/output request to the system components via an interconnect.

Abstract: Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract: A method of restructuring a source computer program to a target computer program. A defined source computer program has source code. A set of tasks is defined for the source computer program to be performed by the source computer program. For each task, a corresponding set of input data sets is defined. For each input data set, a corresponding set of programs is determined such that each program in the set of programs includes declarations and executable statements, from the source code of the source computer program, required to execute the task in each input data set. Each set of programs is processed to generate a component that executes the respective task, resulting in generation of a set of components. A target computer program is generated from the set of components.

Abstract: A method and corresponding equipment for emulation of a target programmable unit, which has at least one CPU, by means of an external emulation device, which is coupled to the target programmable unit by means of a communication link, comprising: transferring predetermined initialization data through the communication link to the emulation device for initializing the emulation; transferring through the communication link to the emulation device a CPU clock signal and emulation data; emulating the target programmable unit in the external emulation device using the transferred emulation data; ascertaining respective trace data from the emulation in the external emulation device and storing and/or outputting the trace data; deriving respective target integrity-control data and emulation integrity-control data from respective target-internal data and emulation-internal data; and transferring the derived target integrity-control data from the target programmable unit to the external emulation device.

Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.

Abstract: A replay analyzer is disclosed. The replay analyzer is able to capture traffic from a transmission medium such as a buss and store it in a trace buffer. The replay analyzer can replay that captured data repeatedly as desired and can trigger activity based on patterns found in the captured data. If desired, the captured data may be used for purposes of traffic generation.

Abstract: A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.

Abstract: A hardware emulator having a variable input emulation group is described. Each emulation group comprises two or more processors, where one of the processors (a first processor) is coupled to a data input selector and another one of the processors (a second processor) processes a first amount of data received from a data array. The data input selector receives the first amount of data and a second amount of data from the data array, and selects a third amount of data from among the first and second amounts of data. The third amount of data is provided to the first processor for evaluation.

Abstract: A design verification apparatus includes a dataset generator to generate verification datasets which associate each unit process of a plurality of procedures (processing scenarios) described in a design specification of a target product with an identifier (label) designating which portion of the design specification is to be verified. A process priority setting unit assigns a process priority to each verification dataset according to specified identifiers. An output processor outputs data identifying the verification datasets, together with explicit indication of their process priorities.

Abstract: A virtual testbed for system verification test is provided in which emulated responses are associated with certain steps of a system verification test. The emulated responses can be manually entered or populated with previous test results obtained from execution of the emulation-enabled steps on a real testbed. When the emulation-enabled steps are executed, the system verification test uses the emulated responses as the responses corresponding to the actions of the emulation-enabled steps as if the steps were executed on the real testbed, without actually executing the emulation-enabled steps on the real testbed. Therefore, the virtual testbed of the present invention allows development of test scripts for system verification test without constant, actual access to the real testbed.

Abstract: A debug system includes: a microcomputer mounted on a target system; an emulator configured to execute emulation of the microcomputer based on a user program embedded in the microcomputer; and a computer connected with the emulator in radio communication and configured to instruct start of the emulation and to execute a debugging operation of the microcomputer based on a result of the emulation. The emulator includes: a control section configured to execute the emulation of the microcomputer based on control data from the computer; a radio communication state monitoring section configured to monitor a state of the radio communication between the computer and the emulator when the emulation is performed; and a storage section configured to store substitution control data.

Abstract: A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus arid an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.

Abstract: An electricity-generating backpack that is substantially lighter in weight, has the multiple springs replaced with one large spring whose spring constant can be adjusted in the field in seconds, and replaces a DC generator with a brushless AC generator that permits approximately 70% generator efficiency and the generation of up to 20 W of electrical power by converting mechanical energy to electrical power. A device is provided that always removes some electricity, but not too much, as necessary to extract large levels of the electricity while controlling damping by providing electrical damping circuits including a DC-DC converter designed to emulate a desired load at its input terminals. Additional electricity generating E-MOD devices may be used for generating additional power by hooking an E-Mod device to a generator and to the backpack belt at the wearer's hip and includes a wand that fits against the wearer's femur so as to move through a range of motion as the patient walks.

Abstract: A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time, such as after a periodic update. In one embodiment, a monitoring portion of the emulator periodically monitors the emulator boards and power supplies for physical information. The physical information is communicated to a workstation for communication to a user. For example, the workstation can display the physical information in a graphical user interface (GUI) that shows which boards are plugged in the system and which slots are empty. In yet another aspect, the user can select a particular board in the system and view communication information, such as data errors, status, link errors, global errors, etc.

Abstract: A unitary control module having adjustable input and output mapping functionality, including methods of configuring such devices for use in different applications, are disclosed. The unitary control module can include a unit type selector such as a DIP-switch that can be used by an installer to configure the control module to emulate a particular type of controller. The control module can be configured to run a selection algorithm for configuring the mapping of the input terminals and output terminals for the device based on the controller type selected. In use, the control module may run different control algorithms for controlling the system components based on the controller type selected.

Abstract: A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.

Abstract: A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Abstract: The invention relates to a binary value input/output processing apparatus and method for automatically inputting binary values. A binary value that is inputted first is temporarily stored in a buffer. When a symbol indicating a binary value, such as “0x” or “0X”, is detected from the next input character string, the binary value stored in the buffer is automatically outputted to the screen, following the symbol. Then, a user selects to output, to the output device, the binary value automatically outputted to the screen or to output a new binary value to the output device, instead of the binary value. When the new binary value is outputted, the binary value stored in the buffer is deleted, and the new binary value is stored in the buffer.

Abstract: A method and apparatus for a generating a tape format like file with an associated look-up table on a non-tape storage medium is disclosed. In one configuration, a data storage arrangement can comprise a host computer in communication with a storage system by means of a streaming protocol. The storage system can comprise a non-tape storage medium having at least one file comprising a plurality of records each having user data and meta data wherein the meta data comprises data fields for and about the record. A table associated with the file is adapted to contain information related to at least one of the records. The table can be accessed by the storage system to reduce the amount of time spent locating the records.

Abstract: A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Abstract: Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory system implements a memory operable as different memory technologies. The processor-memory system includes a logic subsystem and a memory subsystem, which includes third dimension memory cells. The logic subsystem implements memory technology-specific signals to interact with the third dimension memory cells as memory cells of a different memory technology. As such, the memory subsystem can emulate different memory technologies. The logic subsystem can be fabricated FEOL on a substrate and the memory subsystem can be fabricated BEOL directly on top of the substrate. An interlayer interconnect structure can electrically couple the logic subsystem with the memory subsystem.

Abstract: An In-Circuit Emulation system. A real microcontroller (device under test) operates in lock-step with a virtual microcontroller so that registers, memory locations and other debugged data can be retrieved from the virtual microcontroller without disrupting operation of a real microcontroller. When an I/O read instruction is carried out followed by a conditional jump instruction dependent upon the I/O read data, the virtual microcontroller does not have adequate time to compute the jump address after receipt of I/O read data from the real microcontroller. Thus, when this sequence of instructions is detected, the virtual microcontroller pre-calculates the jump address and makes the jump decision after receipt of the I/O read data from the real microcontroller.

Abstract: In support of data processing emulation, a data processing condition indicated by a predetermined number of digital data processing signals can be detected by applying the digital data processing signals to a lookup table (LUT) that is programmable according to how the digital data processing signals (23) indicate the data processing condition. The lookup table is responsive to said digital data processing signals for determining whether said data processing condition exists.

Abstract: A modeling system and process for computer-aided, block-based modeling by preparing a first block diagram in a first model plane that relates to a first abstraction stage, in which at least one block is placeable in the first model plane and several blocks are connectable to one another by horizontal data transfer devices for horizontally exchanging data. At least one other block diagram is arrangeable on at least one other model plane assigned to the first abstraction stage that is separated from the first model plane. The first block diagram of the first model plane and the other block diagram of the other model plane form an overall block diagram that can be arranged on a selection of at least two model planes from the first model plane and the other model planes, so that a vertical exchange of data between at least two selected model planes can be produced.

Abstract: An exemplary system includes a development subsystem configured to facilitate development of a software application and a simulation subsystem selectively and communicatively coupled to the development subsystem. The simulation subsystem is configured to emulate a plurality of processing device platforms, receive data representative of a selection of at least one of the plurality of processing device platforms, and simulate an execution of the software application by one or more processing devices associated with the at least one selected processing device platform.

Abstract: An apparatus, protocol and methods for configuration of a platform for prototyping and emulation of a system-on-chip (SOC) device. The apparatus is an extensible platform for configurable prototyping of SOCs using an integrated circuit board comprised of a configurable board controller and a plurality of configurable modules which implement the SOC functionality. A plurality of such platform boards may be linked together to provide emulation and prototyping functionality for a multi-core system. The protocol specifies the SOC platform configuration data, commands for configuration and reading and writing data to each module and the communications between the host computer and the platform. The apparatus uses methods for configurable execution of the configuration commands by the board controller, and for the preparation of the configuration specification by the host computer. The host computer provides a user interface for management of the configuration specification preparation.

Abstract: A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based on the internal PLD signals for the corresponding trigger units; and receiving trigger expression information of the logic analyzer via the software interface as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals. The method may further include generating configuration data based on the trigger unit information and the trigger expression information; and providing the configuration data to the PLD, wherein a trigger expression based on the trigger expression information is stored within memory of the PLD.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: An equivalent circuit of an inductor is provided with a five wire structure. A first wire has a first resistor, an inductor, and a third resistor connected in series. A second wire is connected in parallel with the first wire and has a second resistor. A third wire is connected in parallel with the first and second wires and has a third capacitor. A fourth wire is serially connected to a first common node of the first, second, and third wires, and has a first capacitor connected between the first common node and a first sub capacitor and a first sub resistor connected in parallel. A fifth wire is serially connected to a second common node of the first, second, and third wires, and has a second capacitor connected between the second common node and a second sub capacitor and a second sub resistor connected in parallel.

Abstract: In an aspect of the present invention, a microcomputer includes a CPU core section, and a plurality of external input terminals. A testing section selects a selection external input terminal from the plurality of external input terminals, detects an intermediate voltage of the selection external input terminal, and outputs an interrupt processing signal related to the detection of the intermediate voltage to the CPU core section.

Abstract: A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.

Abstract: Techniques for simulation of multi top-level graphical-containers (e.g., frames) in an object-oriented computing environment are disclosed. A Multi Top-level Graphical-Container Simulator (MTGS) can be provided to simulate multi top-level graphical container support for applications that expect to use a plurality of top-level graphical containers (e.g., frames, windows). A MTGS may be implemented as a layer between a GUI-based application and an operating system and/or hardware/device with limited or virtually no graphical support capability. The Multi Top-level Graphical Simulator (MTGS) can effectively isolate the operating systems and/or hardware/device from the GUI-based application, and yet hide this simulation from the operating system and/or hardware/device. MTGS may be implemented in a platform independent programming language (e.g., Java™ programming language using a set of Java™ classes which have been provided in the Java™ Swing development toolkit.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation, coupled to the emulator system by a high-speed cable, provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded number of cycles to the burst clock logic via the high-speed cable. The host workstation then generates a trigger signal within the high-speed cable, which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal.

Abstract: An in-circuit emulation system with a programming function includes a system power supply, a DC/DC converter, a processing device, a programmer socket and a connector. The system power supply produces a first DC voltage. The DC/DC converter converts the first DC voltage into a second DC voltage and a third DC voltage. The processing device has a processor and a parallel/serial converter. For executing a programming function, the processor uses the parallel/serial converter to convert programming codes into corresponding programming signals. The programmer socket receives the programming signals, the second DC voltage and the third DC voltage to accordingly execute a programming function on an IC plugged in the socket. The connector has one end connected to the processing device and the other end connected to a target board to thereby drive and receive electrical signals of the target board on performing an in-circuit emulation.

Abstract: Configuring reconfigurable interconnect resources employing a switch matrix and configuration bit look-up table are disclosed. Reconfigurable interconnect resources include multiplexors to decrease the number of bits needed to load a configuration. Distributed processing resources configure a selected reconfigurable interconnect resource, interconnecting each input of the reconfigurable interconnect resource with a particular output of the reconfigurable interconnect resource using configuration bits scalably extracted from a row of configuration bits of a look-up table. Use of a configuration bit look-up table allows for compression of the bits needed to load the configuration for a reconfigurable interconnect resource.

Abstract: The present invention relates to a method for automatically generating HDL code, a code generator and a product for generating the code for the purpose of its implementation in programmable logic, based on a graphical representation for coding a state machine. With the method according to the invention, state transitions are executed on the basis of a modified query structure in that, starting from a target state, all the preconditions are derived which must be fulfilled in order to reach said target state.

Abstract: Multiple versions of a runtime system, such as a software emulation application that emulates a legacy hardware architecture, are allowed to co-exist in the memory of a new hardware architecture. The operating system software of the new hardware architecture reads configuration data from a database or table to decide which version of the runtime system is desirable for an application program or game that is being loaded or is currently running, and, if a match is found, only that runtime system is invoked. To reduce storage footprint, the different versions of the runtime system may be stored using “differential patching” techniques. In this configuration, the operating system will always launch the same basic runtime system binary, but it will select a different differential patch to apply at run-time based on the title as determined during the database lookup.

Abstract: Provided is a verification system which improves the efficiency of operation verification in the development of digital LSIs. In the verification system, a verification device can communicate with a verifying apparatus through a bus interface. In the verification device, first and second partial circuits communicating with each other constitute a target for operation verification, i.e., a to-be-verified circuit. The verifying apparatus includes a software emulator which causes a CPU to execute, through a program, calculation corresponding to processing executed by the first partial circuit. A destination selection circuit is installed in a connection path between the first and second partial circuits, and is capable of switching a communication destination of the second partial circuit between the first partial circuit and the software emulator.

Abstract: A two-level transformation scheme to enable a practical fast mesh-free method is disclosed. The first level transformation transforms the original chosen mesh-free shape function to a first transformed mesh-free shape function that preserves Kronecker delta properties. The first transformed mesh-free function allows the essential boundary conditions to be imposed directly. The second-level transformation scheme employs a low pass filter function served as a regularization process that filters out the higher-order terms in the monomial mesh-free approximation obtained from the first-level transformation scheme with desired consistency and completeness conditions. This integration scheme requires only a low-order integration rule comparing to the high order integration rule used in the traditional mesh-free methods. The present invention simplifies the boundary condition treatments and avoids the usage of high-order integration rule and therefore is more practical than the traditional mesh-free methods.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

Abstract: Embodiments of the invention provide a platform-independent application development framework for programming an application. The framework comprises a content interface configured to provide an Application Programming Interface (API) to program the application comprising a programming code to be executed on one or more platforms. The API provided by the framework is independent of the one or more platforms. The framework further comprises an application environment configured to provide an infrastructure that is independent of the one or more platforms and one or more plug-in interfaces configured to provide an interface between the application environment and the one or more platforms.

Abstract: A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time, such as after a periodic update. In one embodiment, a monitoring portion of the emulator periodically monitors the emulator boards and power supplies for physical information. The physical information is communicated to a workstation for communication to a user. For example, the workstation can display the physical information in a graphical user interface (GUI) that shows which boards are plugged in the system and which slots are empty. In yet another aspect, the user can select a particular board in the system and view communication information, such as data errors, status, link errors, global errors, etc. In a further aspect, power supply information can be viewed, such as current and voltage levels, air temperature, fan speed, board temperatures at particular points, etc.

Abstract: A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources.

Abstract: An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit.

Abstract: An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the first deserializer and interprets the test instructions and data using the first format. A frame capture module receives test results according to the interpreted test instructions and data. A first control module communicates with the frame capture module and generates first format control data. The frame capture module packages the test results and the first format control data into frames. A first serializer serializes the frames.

Abstract: The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CPU state and causes the change signal to toggle, and the trace logic notes the state change in the signal. It then exports the internal state presented to it. Once it completes the export, it changes the state of advance and the process begins anew.

Abstract: A system and method for integrated circuit emulation. One embodiment provides a system for in-circuit emulation of an integrated circuit device with program-controlled components. The system includes an integrated circuit device with program-controlled components used in a system for normal operation. The integrated circuit device having at least one program-controlled emulation unit emulating at least one of the program-controlled components of the integrated circuit device, and at least one statistics memory for storing statistical data of the program-controlled emulation unit during emulation.