Abstract: A system and process for restarting a turbomachine includes a shutdown cooldown protection process implemented by a plant level control system or direct control system of the turbomachine. The system and process for restarting ensure rotating components are cooled as expected prior to a unit restart. This system and process for restarting will lockout an ability to restart if an improper cooldown of rotating components is detected. If this lockout is enabled, delaying restart for the rotating components to cool naturally is needed, or the operator could decide to force cool the components.

Abstract: An arithmetic processing apparatus includes: a plurality of nodes (N nodes) capable of communicating with each other, each of the plurality of nodes including a memory and a processor, the memory being configured to store a value and an operation result, the processor being configured to execute first processing when N is a natural number of 2 or more, n is a natural number of 1 or more, and N?2n, wherein the first processing is configured to divide by 2 a value held by a first node, the first node being any of the plurality of nodes and a last node in an order of counting, obtain one or more node pairs by pairing remaining nodes among the plurality of nodes exception for the first node, and calculate repeatedly an average value of values held by each node pair of the one or more node pairs.

Abstract: Systems and methods that address an optimized method in the area of optimization by showing how to generate Ising Hamiltonians automatically for a large class of optimization problems specially handling the constraints. The innovation facilitates qubit reduction in connection with an optimization problem by representing respective integer variables as linear sums of binary variables, wherein depending on the representation, additional equality constraints are provided. Additional slack variables are introduced to change inequality constraints to equality constraints. Based on the equality constraints, an unconstrained pseudo-boolean optimization problem is created. The pseudo-boolean optimization problem is quadratized to generate a quadratic pseudo-boolean function (QPBF) and the number of variables in the QPBF is reduced to facilitate qubit reduction. This results in an automated, problem instance dependent qubit reduction procedure.

Abstract: Approaches for managing how the passage of time is observed by a software execution environment, such as a virtual machine or a sandbox environment. A computer system maintains a set of physical time sources. A set of virtual time sources are computed based on the set of physical time sources. The virtual time sources operate independently of the set of physical time sources. For example, the virtual time sources may observe time passing faster or slower than the set of physical time sources. The set of virtual time sources are presented to the software execution environment as the set of time sources. Many benefits may be obtained such as higher utilization of allocated resources and avoidance of timeouts.

Abstract: Embodiments of the present disclosure provide a method, an electronic device and a computer program product for processing a task. The method comprises: obtaining a first group of processing results generated from processing, by a first group of processing resources of a first device, a first group of sub-tasks in the task; performing a first AllReduce operation on the first group of processing results to obtain a first AllReduce result; obtaining a second AllReduce result from a second device, the second AllReduce result being obtained by performing a second AllReduce operation on a second group of processing results generated from processing, by a second group of processing resources of the second device, a second group of sub-tasks in the task; and performing a third AllReduce operation on the first AllReduce result and the second AllReduce result to obtain a processing result of the task.

Abstract: The inventive disclosures described herein generally pertain to an improved runtime-calibratable analog-computing system. In many embodiments, the improved analog-computing system comprises at least two analog computers, wherein after initial calibration, the system is designed to stagger the runtime calibration modes of each of the at least two analog-computers such that at least one of the analog computers is always in service, thus preventing any downtime for the overall system. In other words, a system user sees one initial calibration, and computing by the overall system is never interrupted.

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

Abstract: An apparatus stores plural pieces of reference data selected based on operation data input from a host OS executed by an information processing device. The apparatus selects one or more pieces of selection reference data from the plural pieces of reference data, based on a plurality of correlation coefficients which are calculated upon receiving a predictive demand and which respectively indicate correlations between predictive target reference data indicating reference data to be predicted and other reference data. The apparatus calculates predictive values of the predictive target reference data, based on the selected one or more pieces of selection reference data, and controls the plurality of calculation resources for the information processing device, based on the predictive values of the predictive target reference data and a predetermined reference value.

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

Abstract: As disclosed herein a method, executed by a computer, includes storing, by one or more processors, entries associated with an index to a first buffer of at least two buffers allocated to the index, and moving, by a batch operation, by one or more processors, entries in the first buffer into an index page for the index in response to an entry movement condition being met. The method further includes storing, by one or more processors, new entries associated with the index to another buffer of the at least two buffers while moving the entries in the first buffer. A computer program product corresponding to the above method is also disclosed herein. A computer program product and computer system corresponding to the above method are also disclosed herein.

Abstract: A method is proposed for controlling a device for distribution of audio, video, data and control signals. The device has a number of inputs and outputs, which can be connected by the switching of takes, and which cover signal paths. Tally signaling signals inputs or outputs as being transmission-relevant. The method comprises the following steps: successful switching operations of takes are locked against further switching operations automatically and without any intervention by an operator. Signal paths are completely locked or unlocked on the basis of tally signaling of an input or output by automatic locking or unlocking of the takes involved. Signal paths are combined to form signal bundles. When signal bundles are locked or unlocked on the basis of tally signaling of the bundle, all of the signal paths involved are automatically locked or unlocked.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: A method for protecting a calculation, by an electronic circuit, of a modular exponentiation of a digital quantity, wherein: a first variable is initialized with a random quantity; at least one second variable is initialized with a value which is a function of the digital quantity; at least for a bit at 1 of an exponent of the modular exponentiation, the first variable is updated by: a) the quotient of its content and a power of the random quantity; and b) the product of its content by that of the second variable; and once all the exponent bits have been processed, the content of the first variable is divided by the random quantity to provide the result of the modular exponentiation.

Abstract: A virtual machine monitor for a virtual machine. The virtual machine monitor makes the processor in the virtual machine: receive a timer setting from the guest OS in place of the timer, the timer setting being for making the timer generate a timer interrupt after a lapse of a setting period; change, when the guest OS inputs or outputs data from or to the I/O device via the virtual machine monitor, the setting period set in the timer so that a relation between I/O wait time recognized by the guest OS and I/O process time other than the I/O wait time becomes approximate to a relation between the I/O wait time recognized by the virtual machine monitor and the I/O process time; set the timer setting with the changed setting period in the timer; and notify, when receiving the timer interrupt, the guest OS of occurrence of the timer interrupt.

Abstract: A fast filter calibration system comprises a multi clock generator, an analog filter comprising a variable capacitor and a fast calibration apparatus. The fast calibration apparatus further comprises a phase comparator, a frequency detector and a fast calibration unit. The fast calibration unit stores a binary code corresponding to a bandwidth frequency of a filter and initiates a fast filter calibration by calibrating the filter from a binary code close to a guaranteed-by-design binary code for the bandwidth frequency to be calibrated.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: The present invention relates to an iterative method and an apparatus for distribution-independent detection of intermediate outliers and outliers in the distribution tail of streamed data. A considerable sequence of streamed data is sequentially read and subsequently assigned to matching bins. The bins are adaptively allocated when, where and if they are needed. Each bin range expands concurrently with the distribution range of the accumulating items assigned to the bin, adding a margin. For every N'th read item, overlapping or adjoining bins are merged, whereupon the bins are assessed for insider preclusion. Information regarding outliers is extracted from the remaining outlier bins when the entire data sequence has been processed.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: Site optimizer is a tool that enables A/B testing of merchandising offers for your online store to help you determine which offers work best on your storefront. A/B testing compares multiple offers simultaneously to randomly selected groups of shoppers. The A/B testing approach provides a unique and effective way to optimize online store performance because it is metrics-driven, objective, and more efficient than other site optimization techniques.

Abstract: A system comprises a workload evaluator that is operable to receive a representative workload that is representative of competing demands for capacity of at least one shared computing resource. The workload evaluator evaluates the representative workload and computes a metric representing a degree of burstiness of demands present in the representative workload. The metric representing degree of burstiness of the representative workload may be used for estimating an upper bound on quality of service provided by a workload manager to the representative workload. The metric may also be used for evaluating at least one scheduler parameter setting of the workload manager to aid in determining an optimal parameter setting based at least in part on the estimated impact of the representative workload on QoS provided by the workload manager.

Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires.

Abstract: The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) used to effect continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.

Abstract: In an input process, a circuit and an input bit to the circuit are inputted to a plurality of computers. Firstly, one computer performs calculation and transmits the calculation result to another computer of the computers. Next, the another computer which has received the calculation result performs the next calculation. Thus, calculation is performed by one computer after another. When all the computers have performed calculation once, the last computer which has performed calculation transmits the calculation result to the first computer which has performed calculation. After this, calculation is performed by one computer after another and the calculation result is transmitted to the next computer, thereby repeating the calculation of each cycle. Thus, it is possible to realize calculation of a value of a given function by using a device including a plurality of computers, with a simpler configuration.

Abstract: An authentication system and a method for signing data are disclosed. The system uses a hardware software partitioned approach. In its implementation the system of the invention compares favourably with performance and other parameters with a complete hardware or full software implementation. Particularly, advantageously there is a reduced gate count. Also as disclosed in the invention the system makes it difficult for hackers to attack the system using simple power analysis.

Abstract: Methods and apparatus, including computer systems and program products, for normalizing computer-represented collections of objects. A first minimum value can be normalized based on a second minimum value of a universal set object that corresponds to the first set object. The second minimum value is both a minimum value supported by a data type (e.g., 1-byte integer) and a minimum value defined to be in the universal set object (e.g., 0 for a universal set of all natural numbers). Similarly, a first maximum value can be normalized based on a second maximum value of the universal set object where the second maximum value is both a maximum value supported by a data type and in the universal set object. Intervals can be normalized, which can involve replacing half-open intervals with equivalent half-closed intervals. Also, a consecutively ordered, uninterrupted, sequence of values of a set object can be normalized.

Abstract: A system and method that optimizes reduce operations by consolidating the operation into a limited number of participating processes and then distributing the results back to all processes to optimize large message global reduce operations on non power-of-two processes. The method divides a group of processes into subgroups, performs paired exchange and local reduce operations at some of the processes to obtain half vectors of partial reduce results, consolidates partial reduce results into a set of regaining processes, performs successive recursive halving and recursive doubling at a set of remaining processes until each process in the set of remaining process has a half vector of the complete result, and provides a full complete result at every process.

Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires.

Abstract: Methods and apparatus provide for accumulating bit streams from four partial products and producing a carry-save output pair, including: producing the save, S, portion of the carry-save output pair, in accordance with the following Boolean expression: S=d3 XOR ((d0 XOR d1) XOR (d2 XOR Cin)), wherein d0, d1, d2, d3 are the bit streams from the four partial products, and Cin is a carry in bit stream receivable from an adjacent compression circuit of an overall partial product reduction array.

Abstract: Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes, and defect-and-fault tolerant systems embodying the methods. An electronic-device embodiment including an array of nanowire crossbars, the nanoscale memory elements within the nanowire crossbars addressed through conventional microelectronic address lines, and a method embodiment for providing fault-tolerant interconnection interfaces with electrically distinguishable signal levels are described.

Abstract: A nanoscale or partial nanoscale interface within an electronic device, and a method for producing such interfaces without the need for precise nanoscale alignment of nanoscale elements of a first circuit layer to elements of a second circuit layer, is disclosed. In one embodiment, dimensions of conductive windows fabricated on microelectronic elements are carefully specified, and redundant nanoscale elements are introduced, in order to produce functional nanoscale-to-microscale interfaces despite imprecise nanoscale alignment of nanoscale elements to microscale elements.

Abstract: The improved AES processing method provides an efficient alternative to both Mips intensive multiplication and to conventional table lookup, used to multiply terms over a Galois field (GF). The improved method takes advantage of the fact that in the GF, any non zero element X can be represented by a power of a primitive element P. The improved method thereby results in a 2 by 256 table. The log base P of the terms being multiplied are looked up and summed, and the anti-log of the sum is looked up in the same table.

Abstract: The present invention is directed to an analog, oligomer-based method for determining a mathematical result of carrying out an operation of matrix algebra on input data. The method comprises representing at least one m-component vector V=&Sgr;iViei by a set of single-stranded oligomers Ei and Ei which are in 1:1 correspondence with the basis vectors ei, i=1, 2, . . . , m in an abstract m-dimensional vector space. A composition comprising at least one set of oligomers Ei and Ei representing the components of a vector is obtained as input date and is subjected to at least one physical or chemical treatment having an effect on the oligomers that is an analog representation of an operation of matrix algebra. The method can be used to represent the operations of a neural network; for example, to produce a content-addressable memory, or a multilayer perceptron.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: This invention describes an algorithm and implementation of overflow prediction for addition without the use of an expensive addition operation. This overflow prediction is particularly applicable to the implementation of addition operation using the carry-save format in high speed arithmetic units.

Abstract: Disclosed herein is an apparatus and method for hyper-rectangle based multidimensional data segmentation and clustering. The segmentation apparatus has threshold calculation means, segment generation means, geometric condition determination means, segment merging means, and segment updating means. The threshold calculation means inputs a multidimensional sequence Si and the minimum number of points per segment minPts, and calculates bounding threshold values for a volume and an edge. The segment generation means initialize a segment set and an outlier set to empty sets and generates a current segment using a first point of the sequence Si. The geometric condition determination means determines whether a next point of the sequence Si satisfies a geometric condition using the bounding threshold values for the volume and the edge. The segment merging means merges the next point of the sequence Si into the current segment if geometric condition is satisfied.

Abstract: The present invention is to provide a molecular computer comprising an electronic operation section and a molecular operation section, wherein, in addition to general computation processing, said electronic operation section controls a function of the molecular operation section substantially, and the molecular operation is performed under control thereof.

Abstract: A molecular computer is formed by establishing arrays of spaced-apart input and output pins on opposing sides of a containment, injecting moleware in solution into the containment and then allowing the moleware to bridge the input and output pins. Moleware includes molecular alligator clip-bearing 2-, 3-, and molecular 4-, or multi-terminal wires, carbon nanotube wires, molecular resonant tunneling diodes, molecular switches, molecular controllers that can be modulated via external electrical or magnetic fields, massive interconnect stations based on single nanometer-sized particles, and dynamic and static random access memory (DRAM and SRAM) components composed of molecular controller/nanoparticle or fullerene hybrids. The current-voltage characteristics that result from the bridging between input and output arrays can be ascertained using another computer to identify the bundles of inputs and corresponding outputs that provide a truth table for the specific functions of the computer.