Abstract: A method for a multi-channel acoustic event detection and classification for weak signals, operates at two stages; a first stage detects a power and probability of events within a single channel, accumulated events in the single channel triggers a second stage, wherein the second stage is a power-probability image generation and classification using tokens of neighbouring channels.

Abstract: The present disclosure relates to a neural network system comprising: a data input configured to receive an input data signal and analog neural network circuitry having an input coupled with the data input. The analog neural network circuitry is operative to apply a weight to a signal received at its input to generate a weighted output signal. The neural network system further comprises compensation circuitry configured to apply a compensating term to the input data signal to compensate for error in the analog neural network circuitry.

Abstract: An analog to digital converter comprises an input for receiving an analog input signal; a plurality of outputs for outputting parallel bits of a digital signal that represents said analog input signal; and a neural network layer providing connections between each of said outputs respectively, each connection having an adjustable weighting. The synapses of the neural networks may be memristors and training may use online gradient descent.

Abstract: Components are extracted from user data being read from a reader of a hard disk drive. The components collectively indicate both a magnitude and direction of a read offset of the reader over a track. The components are input to a machine-learning processor during operation of the hard disk drive, causing the machine-learning processor to produce an output. A read offset of the reader is estimated during the operation of the hard drive head based on the output of the machine learning processor. While reading the user data, a radial position of the reader over the track is adjusted via an actuator based on the estimated read offset.

Abstract: A method and apparatus for selecting frequency modulated continuous wave waveform parameters for multiple radar coexistence by a user equipment is described. The user equipment may transmit a radar waveform consisting of a number of chirps, with each chirp having a same duration. The user equipment may vary waveform parameters of the radar waveform for at least a subset of the number of chirp, where the waveform parameters may be chosen from a codebook comprising at least one codeword of parameters. Reflected radar waveforms are received and processed where the processing includes applying a fast time discrete Fourier transform to reflected radar waveforms to produce a one dimension peak in a time delay dimension for each reflected waveform; and applying a slow time discrete Fourier transform to the reflected radar waveforms, where peaks for the reflected waveforms are added.

Abstract: A system for conditioning a gas includes an inlet configured to receive the gas from a gas source. The system also includes a strainer downstream from the inlet. The strainer is configured to remove debris from the gas. The system also includes a first flowpath downstream from the strainer. The first flowpath includes a first pressure regulator that is configured to regulate a pressure of the gas by a first amount. The system also includes a second flowpath downstream from the strainer. The first and second flowpaths are parallel. The second flowpath includes a second pressure regulator that is configured to regulate the pressure of the gas by a second amount. The system also includes one or more flowpath valves downstream from the strainer and upstream from the first pressure regulator, the second pressure regulator, or both.

Abstract: A method for compensating for power supply ripple that is present in a supply voltage that is generated by a switched-mode power supply, the method including: calculating an estimated power supply ripple that is expected to be generated by the switched-mode power supply; generating a digital ripple compensation signal, based on the estimated power supply ripple; combining a digital baseband (BB) signal and the digital ripple compensation signal to generate a digital modified BB signal; converting the digital modified BB signal to an analog radio frequency (RF) signal; and amplifying the analog RF signal, based on the supply voltage, to generate a RF transmission signal.

Abstract: Technologies are provided for time-to-digital conversion without reliance on a clocking signal. The technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

Abstract: The illustrative embodiments provide a method, system, and computer program product. In an embodiment, a method includes receiving a set of Pauli observables. In an embodiment, a method includes initializing a measurement basis, the measurement basis comprising a set of Pauli bases equivalent to a number of qubits of a quantum processor. In an embodiment, a method includes creating a list of a set of Bell basis candidates, each of the set of Bell basis candidates configured to measure at least one of the set of Pauli observables. In an embodiment, a method includes selecting a Bell basis candidate from the set of Bell basis candidates. In an embodiment, a method includes reconfiguring the measurement basis to replace a subset of the set of Pauli bases with the selected Bell basis candidate.

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

Abstract: A computing system implementing a design verification system can elaborate a mixed-signal circuit design having a complex sandwich hierarchy using a standard digital solver and a standard analog solver, as opposed to a tightly coupled custom elaboration engine. The design verification system can parse the mixed-signal circuit design to identify analog design blocks and flatten the analog design blocks into the structural proxy blocks having parameter connections to digital design blocks in the mixed-signal circuit design. The design verification system can replace an analog portion of the mixed-signal circuit design with the structural proxy blocks and elaborate the structural proxy blocks and digital design blocks associated with a digital portion of the mixed-signal circuit design. The design verification system can elaborate the analog portion of the mixed-signal design and simulate the elaborated analog portion with an analog simulator and the elaborated digital portion with a digital simulator.

Abstract: A testing device configured to operate as a dedicated tool for testing motor drives and motor shafts guides a user (such as a test engineer or a technician) through the steps of testing the motor drive and shaft. The testing device is configured to output testing results to the user. By configuring the testing device to output specific motor drive and shaft measurement results and by guiding a user through the steps of performing the measurement, operation of the testing device is simplified.

Abstract: The present disclosure provides a compensation method, compensation device, and a display device. The compensation method includes: adjusting charging time for multiple areas of the display screen so that the charging time for each area is positively related to a distance from the area to a data voltage input terminal; comparing a first grayscale value before compensation of a sub-pixel in an i-th row and j-th column with a second grayscale value input to a sub-pixel in an (i?1)-th row and j-th column; searching a corresponding grayscale compensation parameter from a grayscale compensation parameter table according to the first grayscale value and the second grayscale value; compensating the first grayscale value by the grayscale compensation parameter to obtain a third grayscale value; and inputting the third grayscale value to the sub-pixel in the i-th row and j-th column for display.

Abstract: A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.

Abstract: A method, system and product for circuit simulation using a recording of a reference execution. The method comprises obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution. The method further comprises obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles. The method further comprises simulating, by a processor, an execution of the circuit, wherein said simulation is performed using the recorded values of the reference execution.

Abstract: An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.

Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

Abstract: A system and method are provided to yield a QRNG based on homodyne detection of quantum noise (e.g., vacuum noise measured as shot noise) generated from a local oscillator, such as an LED. In one embodiment, a QRNG may be provided that is adjustable based on a control input to produce a random output that can be translated to one or more random data bits.

Abstract: A method and system for random number generation. The method comprises the steps of exposing first and second photodetectors to the same mode of a first electromagnetic field in the presence of a mode in a vacuum state of a second electromagnetic field, such that an illumination of the first and second photodetectors is at least substantially balanced; and generating a random noise signal based on a photocurrent difference between the first and second photodetectors.

Abstract: An analog conditioning circuit and a corresponding method for processing an analog input signal provide a conditioned analog signal for input into an analog processing circuit. The analog conditioning circuit comprises a main signal path between an input for receiving the analog input signal and an output for outputting the conditioned analog signal, wherein the transfer function of the main signal path is constrained by a transfer function requirement associated with the analog processing circuit; and a feedforward signal path comprising a first filtering block configured to attenuate desired frequencies of a first signal derived from the analog input signal to provide a filtered analog signal; wherein the feedforward signal path is configured to input the filtered analog signal into the main signal path such that the filtered analog signal is subtracted from a second signal derived from the analog input signal to provide the conditioned analog signal.

Abstract: Various embodiments are described that relate to random number generation. When a desire arises for a random number a circuit can be completed with a reverse biased semiconductor-junction element. When the circuit is completed an analog voltage spike can be produced that is random due to properties of the reverse biased semiconductor-junction element. This analog voltage spike can be converted into a digital value that serves as the random number. The digital value can be outputted and used as the random number.

Abstract: Techniques are provided for encryption and decryption of time series data using a digital filter array. A plurality of digital time series samples generated by a digital time series generation device are applied to a digital filter array (e.g., a finite impulse response filter or an infinite impulse response filter) that combines delayed versions of the digital time series samples using a plurality of coefficients to generate a plurality of encrypted digital time series samples. The plurality of coefficients comprise a portion of an encryption key associated with the digital time series generation device. The digital time series generation device has an associated device identifier, and the device identifier and the corresponding encryption key are registered with a server. The plurality of encrypted digital time series samples and the device identifier are provided to the server for decryption using an inverse digital filter array based on the encryption key.

Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

Abstract: Embodiments of the present invention concern locating targets using non-linear radar with a matched filter which uses exponential value of the transmit signal. According to embodiments, a method of non-linear radar target location includes: transmitting a signal of a transmit waveform towards a target; receiving a signal from the target; creating a matched filter by generating an exponential function of the transmit waveform corresponding to a particular harmonic of the interest; and applying the matched filter to the received signal to generate and output a signature waveform for the target of the particular harmonic of interest. In other embodiments, the matched filtering may be combined with sidelobe reduction.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

Abstract: Methods, media and apparatus for smoothing a time-varying level of a signal. A method includes estimating a time-varying probability density of a short-term level of the signal and smoothing a level of the signal by using the probability density. The signal may be an audio signal. The short-term level and the smoothed level may be time series, each having current and previous time indices. Here, before the smoothing, computing a probability of the smoothed level at the previous time index may occur. Before the smoothing, calculating smoothing parameters using the probability density may occur. Calculating the smoothing parameters may include calculating the smoothing parameters using the smoothed level at the previous time index, the short-term level at the current time index and the probability of the smoothed level at the previous time index. Calculating the smoothing parameters may include calculating the smoothing parameters using breadth of the estimated probability density.

Abstract: A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that the signal to an impedance element is the same as the previous value, then the driver of that impedance element is “turned off” or goes into a high impedance state, so that no current flows through that impedance element, and it no longer contributes to the filter output. Alternatively, if the impedance elements are the same between two adjacent taps of the delay line, the driver of one of those impedance elements may be turned off or go into a high impedance state. The technique may be particularly useful in differential output filters. Turning off a driver effectively removes the attached impedance element from the filter and reduces current flow and power consumption, thus extending battery life in mobile devices.

Abstract: A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.

Abstract: Methods and apparatuses embodied in delta sigma domain digital signal processing circuits that perform linear operation of delta sigma modulated bit stream, including adding, coefficient multiplication, and compressing. The digital processing circuits perform on-the-fly processing to generate a continuous output delta sigma bit-stream based on the continuous input delta-sigma modulated bit-streams and the input binary coefficients. The on-the-fly bit-stream processing circuit is realized via digital delta sigma modulators with input coefficient multiplexers, feedback multiplexers, and toggling multiplexers.

Abstract: A random number generator includes a light source emitting light at a first frequency, an optical unit including an optical component configured to receive light at the first frequency and emit light at a second frequency, and a measurement unit configured to receive light at the second frequency, and generate a random output value related to a phase parameter of the light at the second frequency.

Abstract: A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N?1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N?1 memory location swap operations, and resets every (N2?N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract: An analog baseband filter apparatus for a multi-mode and multi-band wireless transceiver and a method for controlling the analog baseband filter apparatus are provided. The analog baseband filter apparatus includes a plurality of Radio Frequency (RF) units, each of the plurality of RF units being for receiving RF signals of one of a plurality of frequency bands and outputting baseband signals, a plurality of filter blocks for filtering and amplifying the baseband signals, and a switching unit for connecting at least two of the plurality of RF units to at least one of the plurality of filter blocks according to a selected communication mode, wherein the at least one of the plurality of filter blocks is configured to be connected to a capacitor region of an adjacent filter block from among the plurality of filter blocks.

Abstract: A measuring device provides a synthesizer device, at least two controlling devices and at least two controlled oscillators. The synthesizer device contains at least one direct digital synthesizer and generates at least two signals of known phase ratio. Signals generated by the synthesizer device form reference signals of at least one controlling device. Signals formed by the controlling devices control the controlled oscillators. The measuring device contains only frequency splitters, which divide by integer division factors.

Abstract: Devices and methods for generating a random number that utilizes a magnetic tunnel junction are disclosed. An AC current source can be in electrical connection to a magnetic tunnel junction to provide an AC current to the magnetic tunnel junction. A read circuit can be used to determine a bit based on a state of the magnetic tunnel junction. A rate of production of the bits can be adjusted, such as by adjusting a frequency or amplitude of the AC current. A probability of obtaining a “0” or “1” bit can be managed, such as by an addition of DC biasing to the AC current.

Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein.

Abstract: A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent invocation of a function. The compiler creates a width-specific executable version of the program code by determining a vector width of a target computer system and omitting the function from the width-specific executable if the vector width meets one or more criteria. For example, the compiler may omit the function call if the vector width is greater than a minimum size.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: A random number generator device that utilizes a magnetic tunnel junction. An AC current source is in electrical connection to the magnetic tunnel junction to provide an AC current having an amplitude and a frequency through the free layer of the magnetic tunnel junction, the AC current configured to switch the magnetization orientation of the free layer via thermal magnetization. A read circuit is used to determine the relative orientation of the free layer magnetization in relation to the reference layer magnetization orientation.

Abstract: An embedded control system capable of ensuring precision in arithmetic with data in the floating-point format and also avoiding a shortage of the storage area of a memory is provided. According to an embedded control system in the present invention, when discrete data in the floating-point format is stored in a read-only memory, the discrete data in the floating-point format is converted into data in a significand-reduced floating-point format before being stored. Here, a significand-reduced floating-point number is a number obtained by deleting low-order bits of the significand of a floating-point number. Further, an interpolation search is performed using discrete data, the discrete data in the significand-reduced floating-point format stored in the read-only memory is brought back to the discrete data in the floating-point format before an interpolation search being performed.

Abstract: A filter controller. In one embodiment, the filter controller includes a first mechanism for providing an input signal to an adjustable filter. A second mechanism measures a response of the adjustable filter to the input signal and provides a second signal in response thereto. A third mechanism sets one or more parameters of the adjustable filter in response to the second signal. In a more specific embodiment, the adjustable filter includes one or more sub-filters, such as a canceller filter, which may be any filter that employs one or more portions or versions of a signal to selectively cancel one or more portions or versions, such as frequency components, of the same signal.

Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A method includes accepting an analog input signal that includes a sequence of pulses. The analog input signal is filtered so as to produce a filter output, using a filter whose time-domain response is confined to a finite time period and whose frequency-domain response is non-zero at a finite set of integer multiples of a frequency shift ??, and is zero at all other integer multiples of ??. The filter output is sampled so as to produce digital samples. Respective amplitudes and time positions of the pulses in the sequence are calculated based on the digital samples.

Abstract: A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.

Abstract: A method and system for designing a discrete-time filter having a transfer function which approximates that of an analog shelf filter is disclosed. Prior art methods include applying the bilinear transform to the analog filter, which has the drawback of warping high-frequency features of the desired transfer function. In an embodiment of the present invention, an analog filter is designed which anticipates the warping imposed by the bilinear transform. For filters whose features approach the Nyquist limit, the inventive method provides a closer approximation to the analog response than direct application of the bilinear transform.

Abstract: Provided are a receiving module and a receiver having the same. The receiving modules includes: a comparing and detecting means for comparing a current bit of a received signal having a continuous waveform to a previous bit thereof and detecting a difference between the current bit and the previous bit; an amplifying means for amplifying the difference detected by the comparing and detecting means; and a sampling means for sampling a waveform of the received signal amplified by the amplifying means to output valid data.

Abstract: A random bit generator and a method thereof are provided. The random bit generator includes an amplifier, a comparing circuit, an oscillator, a sampler, and a storage circuit. The amplifier amplifies a difference between input signals generated based on thermal noise. The comparing circuit compares an alternating current (AC) signal output from the amplifier with a direct current (DC) signal obtained by low-pass filtering the AC signal and outputs a signal according to the comparison result. The oscillator may be implemented with a resistor-capacitor (R-C) oscillator. The oscillator consumes lower current and occupies a smaller layout area than a voltage controlled oscillator (VCO) and outputs an oscillation signal. The sampler samples the oscillation signal output from the oscillator in response to the output signal of the comparing circuit. The storage circuit stores an output signal of the sampler in response to a clock signal.

Abstract: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal.