Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.

Abstract: Disclosed is a device that multiplies a first signal outputted from a CTLE and a second signal obtained by delaying the first signal by a predetermined time interval; produces a specific signal reflecting a temporal sum of the multiplied signal; determines gain control signal in a manner such that the difference between the specific signal and a predetermined target level is reduced; and provides the determined gain control signal to the CTLE so as to be applied to high-band boosting thereof. The time interval to be delayed corresponds to N (N is an integer equal to or greater than one) times a unit interval that is occupied by one symbol in the first signal.

Abstract: A noise suppression device including: a processor configured to: divide a voice signal into frames such that two successive frames overlap each other; compute a frequency spectrum for the voice signal; remove a noise component from an amplitude component of the frequency spectrum to compute a noise suppression amplitude component; compare amplitude components or noise suppression amplitude components for each pair of successive frames to compute a comparison value for each frequency; compute a gain according to the comparison value for each frequency; compute a corrected amplitude component for each frequency by multiplying the noise suppression amplitude component by the corresponding gain; and compute a corrected voice signal based on the corrected amplitude component for each frequency.

Abstract: A device includes a first terminal configured to receive a reference voltage, a second terminal configured to receive a weighted tap value, a local generator circuit configured to create a group of unsigned voltage correction values based on the reference voltage and the weighted tap value, and a sign configuring circuit configured to receive the group of unsigned voltage correction values from the local generator circuit and assign a polarity to each respective unsigned voltage correction value of the group of unsigned voltage correction values, creating correction signals from the group of unsigned voltage correction values. The device also includes an output configured to transmit the correction signals to a first input of a processing circuit, wherein the processing circuit is configured to use the correction signals to offset inter-symbol interference from a data stream on a distorted bit based at least on a control signal.

Abstract: An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.

Abstract: A digital filter circuit includes an FFT circuit (13) that transforms a complex signal in a time domain into a signal in a frequency domain, an I/Q separation circuit (15) that separates the signal in the frequency domain into a signal in a first frequency domain that corresponds to the real part of the complex signal in the time domain, and a signal in a second frequency domain that corresponds to the imaginary part of the complex signal in the time domain, a filter circuit (21) that performs filter processing on the signal in the first frequency domain, a filter circuit (22) that performs filter processing on the signal in the second frequency domain, an I/Q combination circuit (16) that combines an output from the filter circuit (21) and an output from the filter circuit (22) to generate a signal in a third frequency domain, a filter circuit (23) that performs filter processing on the signal in the third frequency domain, and an IFFT circuit (14) that transforms an output signal from the filter circuit (23

Abstract: A semiconductor device may include a candidate selector configured for generating a plurality of candidate threshold value sets from a plurality of digital values corresponding to a plurality of analog signals output from a memory cell array. The semiconductor device may include a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set. The semiconductor device may include a comparator configured for deciding logic levels of the plurality of digital values according to the selected threshold value set.

Abstract: The embodiments of the present invention provide a method and an apparatus for compensating nonlinear distortions in an intensity modulation-direct detection (IM-DD) system; wherein the method comprises: calculating, according to nonlinear coefficients and differences between values of an input signal at different time, nonlinear distortions of the input signal, so as to eliminate the nonlinearity distortions. By applying the method and the apparatus provided by the embodiments of the present invention, nonlinear cost of the IM-DD system can be effectively reduced, thereby improving the system capacity.

Abstract: A transmission circuit including an equalizer circuit, a slicer circuit, a signal detection circuit, and a control circuit is provided. The equalizer circuit performs an equalizing operation on an input signal according to preset states to output an equalizing signal corresponding to each preset state. The slicer circuit performs a slicing operation on the equalizing signal to output a slicing signal. The signal detection circuit detects and compares the equalizing signal and the slicing signal and accordingly adjusts the equalizer circuit to one of the preset states. The control circuit receives the slicing signal corresponding to each preset state, compares the slicing signal corresponding to each preset state with a plurality of signal patterns to generate a comparison result, and selects one of the preset states according to the comparison result, such that the control circuit let the equalizer circuit perform the equalizing operation according to the selected preset state.

Abstract: A receiver circuit includes a feedback filter having multiple taps for receiving a quantized signal and outputting a feedback signal and adaptation circuitry for adapting tap weights of the feedback filter. In one embodiment, the tap weights may be adapted with variable update resolution. In another embodiment, the feedback filter may have fixed and floating taps. Other embodiments relate to methods of equalizing an input signal using a feedback filter. In one embodiment, tap weights of the feedback filter are adapted using adaptation circuitry with variable update resolution. In another embodiment, the adaptation circuitry adapts fixed and floating tap weights of the feedback filter. Other embodiments and features are also disclosed.

Abstract: Systems and methods are provided for adaptively filtering a signal. A signal is received, and the received signal is filtered to generate an output signal. A difference signal is generated based on a difference between the output signal and a reference signal, and a correlation of the received signal and the different signal is evaluated. Then, a mode is selected between a first adaptive filtering mode and a second adaptive filtering mode based at least in part on the correlation, and the received signal is filtered using the selected adaptive filtering mode.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.

Abstract: The present technique relates to a reception device and a reception method which can improve equalization performance. An equalization processing unit has a time domain equalization unit which equalizes a received signal in a time domain and a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain, and performs control of switching between the time domain equalization unit and the frequency domain equalization unit. The present technique can be applied to, for example, equalize a signal of data transmitted by way of single carrier transmission or data transmitted by way of multicarrier transmission.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: The present disclosure relates to the field of network communication, and specifically discloses an adaptive equalization method, including: obtaining a first filtered signal according to a first filter coefficient; deciding the first filtered signal based on an original constellation map to obtain a first decision signal, and deciding the first filtered signal based on a level (n?1) constellation map to obtain a level (n?1) pseudo decision signal; if average energy of the level (n?1) error signal is less than a level (n?1) threshold, switching the level (n?1) constellation map to a level n constellation map; obtaining a second filter coefficient according to the update magnitude; obtaining a second filtered signal according to the second filter coefficient; and deciding the second filtered signal based on the original constellation map to obtain a second decision signal. Embodiments of the present disclosure also disclose an adaptive equalizer.

Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).

Abstract: Disclosed herein is a reception apparatus, including a first equalization section, a second equalization section, and an arithmetic operation section. The first equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses a single carrier. The second equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses multi carriers. The arithmetic operation section is adapted to carry out arithmetic operation for determining information to be used for the equalization by the first equalization section and arithmetic operation for determining information to be used for the equalization by the second equalization section.

Abstract: Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: A method and a circuit for controlling an equalizer and an equalizing system are disclosed. The method includes providing a first level from a set of levels as a peaking level of the equalizer; equalizing a transmission signal by using the equalizer with the first level to obtain a first signal; providing a second level from the set of levels as the peaking level of the equalizer; equalizing the transmission signal by using the equalizer with the second level to obtain a second signal; determining a first frequency of the first signal; determining a second frequency of the second signal; comparing the first frequency and second frequency to obtain a comparing result; and determining the peaking level of the equalizer for following equalization of the transmission signal in accordance with the comparing result.

Abstract: A tap coefficient control circuit and a method for controlling a tap coefficient for a decision feedback equalizer are disclosed. The method includes adjusting a correction voltage applied to the tap coefficient based on a first tap quantization and detecting a decision feedback equalizer tap convergence. After the decision feedback equalizer tap convergence is detected, the method adjusts the correction voltage applied to the tap coefficient based on a second tap quantization, wherein the second tap quantization is different from the first tap quantization.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.

Abstract: In an embodiment of the present invention, a feedback technique is used to track a reference signal with a DFE summing node common mode voltage. For example, in an embodiment implemented in CML, the feedback signal shifts both differential signals (e.g., the summing node common voltage and the reference voltage) by the same amount. In such an embodiment, the feedback technique preferably changes the reference common mode but not its differential mode.

Abstract: A receiver is configured to receive a sample of an inter-symbol correlated (ISC) signal, the sample corresponding to a time instant when phase and/or amplitude of the ISC signal is a result of correlation among a plurality of symbols of a transmitted symbol sequence. The receiver may linearize the sample of the ISC signal. The receiver may calculate a residual signal value based on the linearized sample of the ISC signal. The receiver may generate an estimate of one or more of said plurality of symbols based on the residual signal value. The linearization may comprise applying an estimate of an inverse of a non-linear model. The non-linear model may be a model of nonlinearity experienced by the ISC signal in a transmitter from which the ISC signal originated, in a channel through which the ISC signal passed en route to the receiver, and/or in a front-end of the receiver.

Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

Abstract: An improved receiver apparatus and algorithm for equalizing signals in a receiver device may equalize a block of data generated from N data symbols in a single carrier communication system. A first algorithm may be applied to a plurality of signal samples to generate a frequency domain representation of the samples. A channel estimate may be generated and a frequency response of a zero-forcing or a minimum-mean-square equalizer is applied. A conjugate of the computed frequency response is multiplied with a frequency domain representation for each sample to generate a product value. N-aliased frequency domain values from the generated product value may be determined for each of the samples. A second algorithm is applied to the generated N-aliased frequency domain values to generate estimates of the transmitted time domain data symbols.

Abstract: A two stage interference cancellation (IC) process includes a linear IC stage that suppresses co-channel interference (CCI) and adjacent channel interference (ACI). The linear IC stage disambiguates otherwise super-trellis data for non-linear cancellation. Soft linear IC processing is driven by a-posteriori probability (Apop) information. A second stage performs expectation maximization/Baum Welch (EM-BW) processing that reduces residual ISI left over from the first stage and also generates the Apop which drives the soft linear IC in an iterative manner.

Abstract: A method and apparatus for receiving data in high-speed applications wherein an analog-to-digital converter (ADC) samples a received signal and a data decoder implemented with a tree search algorithm detects the bits of the sampled data for timing recovery. In some embodiments, a Viterbi detector is implemented to provide accurate bit detection for data output while tree search detected data is used to determine the optimal sampling phase for the ADC. In some embodiments, after the phase acquisition stage of timing recovery has completed, the tree search decoder may decrease the rate of data detection to maintain phase tracking.

Abstract: Disclosed are a receiving equalization device and a method thereof, the receiving equalization device including a subtracter to output a first output signal, an eye monitor block to obtain a sampling timing by using the output first signal, and a slicer to generate a sampling signal by sampling the first output signal based on the sampling timing, and to return the generated sampling signal to the subtracter via a feedback filter or an algorithm determining block.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits.

Abstract: A signal processing apparatus includes a signal processing unit configured to carry out signal processing on a single-carrier signal and a multi-carrier signal by making use of a plurality of common filters shared by the single-carrier signal and the multi-carrier signal.

Abstract: Equalization techniques for compensating distortion associated with a communications channel are provided. In one aspect of the invention, a method/apparatus for equalizing an input signal received from a communications channel includes the following steps/operations. At least one sampling is generated from the received input signal based on a clock signal unrelated to a clock signal used to recover data associated with the received input signal. Distortion associated with the communications channel is then compensated for based on at least a portion of the at least one generated sampling.

Abstract: A finite impulse response filter (FIR) for processing a communication channel. The FIR comprises a delay line, a tap processor and a summer. The delay line has “N” taps to successive portions of the communication channel. The delay line shifts the successive portions of the communication channel once in each symbol processing interval. The tap processor subjects each of the “N” taps to a first scaling utilizing first scaling coefficients associated with filtering the current symbol interval and further subjects at least one of the “N” taps to a second scaling by a second scaling coefficient associated with filtering the prior symbol interval. The summer generates in each symbol interval a filtered output comprising a sum of the “N” scaled taps from the first scaling in the prior symbol interval and the second scaling of the at least one tap in the current symbol interval, thereby increasing an order of the FIR without corresponding increase in an order of the delay line.

Abstract: Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits.

Abstract: A signal detection apparatus detects the frequency of an input signal without using a PLL. The detection apparatus includes a first and a second orthogonalizer, a phase difference calculator and an integrator, to control the variable coefficient a1 of a band-pass filter. Information e[k]=M·sin(?) representing the phase difference ? between the input data x[k] and the output data y[k] is calculated with the first and second orthogonalizers and the phase difference calculator. The sign of e[k] is inverted and a predetermined integral calculation is performed with the integrator, and the calculated integral value is set as the coefficient a1 of the band-pass filter. Every time input data x[k] is input, the coefficient a1 is changed by reducing it when e[k]>0 and increasing it when e[k]<0. Thus, the frequency of the output signal of the band-pass filter is matched to the input signal.

Abstract: An adaptive finite-impulse-response filter includes a series of taps; each tap has a corresponding value of tap coefficient. Values of tap coefficients are calculated to minimize a system error function. The solution is under-constrained, and some values of tap coefficients can grow and cause overflow errors. Growth of tap coefficients is controlled by introducing tap leakage. Disclosed is a symmetric leakage algorithm, in which an updated value of the tap coefficient of a particular tap is based on the old value of the tap coefficient of the particular tap, on the old values of the tap coefficients of a set of taps preceding the particular tap, and on the old values of the tap coefficients of a series of taps following the particular tap.

Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

Abstract: Systems and methodologies are described that facilitate equalization of received signals in a wireless communication environment. Multiple transmit and/or receive antennas and utilize MIMO technology to enhance performance. A single tile of transmitted data, including a set of modulation symbols, can be received at multiple receive antennas, resulting in multiple tiles of received modulation symbols. Corresponding modulation symbols from multiple received tiles can be processed as a function of channel and interference estimates to generate a single equalized modulation symbol. Typically, the equalization process is computationally expensive. However, the channels are highly correlated. This correlation is reflected in the channel estimates and can be utilized to reduce complex equalization operations. In particular, a subset of the equalizers can be generated based upon the equalizer function and the remainder can be generated using interpolation. In addition, the equalizer function itself can be simplified.

Abstract: A data regeneration device regenerates a digital signal in a low-speed pass-through mode of operation, performs an upstream link equalization procedure on an upstream data link in an equalization mode of operation, performs a downstream link equalization procedure on a downstream data link in the equalization mode of operation, and regenerates the digital signal in a high-speed pass-through mode of operation. The data regeneration device transitions seamlessly from the low-speed pass-through mode of operation to the equalization mode of operation in compliance with a communication protocol. Moreover, the data regeneration device synchronizes completion of the upstream link equalization procedure with completion of the downstream link equalization procedure so that the data regeneration device transitions seamlessly from the equalization mode of operation to the high-speed pass-through mode of operation in compliance with the communication protocol.

Abstract: An equalizer for equalizing an input signal includes an infinitive impulse response (IIR) filtering portion for filtering the input signal to produce N filtered outputs; a gain-adjusting portion coupled to the IIR filtering portion with N gains for adjusting the N filtered outputs to produce N gained outputs, respectively; and an adder for summing the N gained outputs to generate an equalized output signal. N is an integer larger than 2.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit. The equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient. The noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient. The data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output. The data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial.

Abstract: Methods and systems are provided for coarse phase estimation for highly-spectrally efficient communications. An example method may include, equalizing, in a receiver, a received inter-symbol correlated (ISC) signal to generate an equalized ISC signal. A phase adjustment signal may be generated based on an ISC feedback signal. The ISC feedback signal may be generated using a sequence estimation process and a non-linearity function. A phase of the equalized ISC signal may be adjusted using the generated phase adjustment signal, to generate a phase adjusted partial response signal. The phase adjustment signal may be generated based on a phase difference between the equalized ISC signal and the partial response feedback signal. At least one ISC vector may be generated by buffering samples of the phase adjusted ISC signal.

Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Abstract: A signal-equalizing system for multi-rate signals and a signal-equalizing method for the system are provided. The system stores a number of compensation methods of equalization. The method includes the steps: acquiring all transmission rates of a multi-rate signal, loading output documents of a signal simulation software, wherein the output documents comprise channel loss values of all transmission rates of the multi-rate signal and selecting a compensation method based on channel loss in the course of the multi-rate signal transmitted and differences among all transmission rates of the multi-rate signal from the plurality of compensation methods of equalization.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount: The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.